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Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25380 1 T1 20 T2 19 T3 19



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 21762 1 T1 20 T2 9 T3 19
auto[ADC_CTRL_FILTER_COND_OUT] 3618 1 T2 10 T6 15 T11 10



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19231 1 T1 20 T2 9 T3 12
auto[1] 6149 1 T2 10 T3 7 T4 23



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21190 1 T1 20 T2 14 T3 3
auto[1] 4190 1 T2 5 T3 16 T6 7



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 33 1 T17 6 T271 1 T107 1
values[0] 20 1 T272 1 T233 12 T273 1
values[1] 690 1 T133 12 T135 14 T167 10
values[2] 537 1 T2 10 T15 5 T136 1
values[3] 754 1 T3 3 T26 1 T133 27
values[4] 780 1 T6 15 T11 10 T28 16
values[5] 3079 1 T3 12 T4 23 T5 36
values[6] 654 1 T14 6 T163 3 T138 9
values[7] 839 1 T24 13 T28 13 T134 1
values[8] 665 1 T11 14 T28 11 T134 1
values[9] 1500 1 T2 9 T3 4 T31 1
minimum 15829 1 T1 20 T6 80 T9 18



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 813 1 T133 12 T135 14 T167 10
values[1] 640 1 T2 10 T15 3 T136 1
values[2] 686 1 T3 3 T26 1 T28 16
values[3] 3158 1 T4 23 T5 36 T6 15
values[4] 715 1 T3 12 T11 10 T31 1
values[5] 763 1 T14 6 T24 13 T136 1
values[6] 737 1 T28 13 T134 2 T163 3
values[7] 739 1 T11 14 T28 11 T31 1
values[8] 1002 1 T2 9 T51 22 T136 1
values[9] 297 1 T3 4 T167 13 T38 16
minimum 15830 1 T1 20 T6 80 T9 18



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 20952 1 T1 20 T2 7 T3 19
auto[1] 4428 1 T2 12 T4 21 T5 33



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 185 1 T133 12 T135 1 T144 9
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 269 1 T167 10 T137 1 T139 11
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 127 1 T15 2 T136 1 T37 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 238 1 T2 10 T164 8 T130 13
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 238 1 T3 1 T133 16 T152 5
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 205 1 T26 1 T28 16 T31 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1689 1 T4 23 T5 36 T7 39
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T6 9 T135 1 T38 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T3 1 T156 1 T138 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T11 10 T31 1 T15 14
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T14 4 T39 3 T218 8
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 227 1 T24 1 T136 1 T130 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 226 1 T28 13 T134 2 T163 3
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T156 1 T38 1 T192 17
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 278 1 T11 14 T28 11 T31 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T263 18 T256 10 T230 16
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 344 1 T2 4 T51 8 T136 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 223 1 T138 1 T130 1 T152 6
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 73 1 T3 1 T167 13 T38 9
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 67 1 T149 1 T17 5 T160 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 15686 1 T1 20 T6 79 T9 18
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 158 1 T135 13 T144 2 T145 10
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 201 1 T139 11 T38 9 T144 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 110 1 T15 1 T37 1 T147 8
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T130 13 T142 12 T217 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 139 1 T3 2 T133 11 T16 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 104 1 T133 9 T15 3 T51 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1022 1 T29 29 T213 13 T16 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 241 1 T6 6 T135 8 T38 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T3 11 T138 8 T144 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T15 12 T142 11 T212 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 136 1 T14 2 T39 2 T253 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 234 1 T24 12 T130 11 T251 3
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 164 1 T246 9 T34 4 T215 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T43 1 T216 10 T274 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T15 10 T51 1 T165 10
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 114 1 T263 5 T256 11 T87 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 269 1 T2 5 T51 14 T254 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 166 1 T138 10 T130 12 T204 16
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 82 1 T3 3 T38 7 T165 13
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 75 1 T149 10 T17 1 T91 13
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 144 1 T6 1 T14 1 T15 3



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[1]] [values[0]] [auto[ADC_CTRL_FILTER_COND_IN]] 0 1 1
[auto[1]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 16 1 T271 1 T107 1 T275 14
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 5 1 T17 5 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 14 1 T272 1 T233 12 T276 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 4 1 T273 1 T277 3 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 152 1 T133 12 T135 1 T144 9
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 240 1 T167 10 T137 1 T139 11
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 119 1 T136 1 T37 3 T16 4
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T2 10 T15 2 T164 8
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 222 1 T3 1 T133 16 T15 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 228 1 T26 1 T134 1 T51 11
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 176 1 T16 1 T204 1 T240 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 252 1 T6 9 T11 10 T28 16
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1706 1 T3 1 T4 23 T5 36
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T31 1 T15 14 T142 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T14 4 T163 3 T138 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 208 1 T141 1 T204 1 T143 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 245 1 T28 13 T134 1 T146 12
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T24 1 T136 1 T130 12
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 244 1 T11 14 T28 11 T134 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 136 1 T156 1 T38 1 T263 18
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 483 1 T2 4 T3 1 T31 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 358 1 T138 1 T130 1 T152 6
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 15685 1 T1 20 T6 79 T9 18
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 11 1 T275 11 - - - -
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T17 1 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 2 1 T277 2 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T135 13 T144 2 T243 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 175 1 T139 11 T38 9 T144 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 100 1 T37 1 T16 1 T145 10
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T15 3 T130 13 T142 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T3 2 T133 11 T15 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 158 1 T51 12 T155 1 T165 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T16 1 T204 8 T149 2
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T6 6 T133 9 T135 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1027 1 T3 11 T29 29 T213 13
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T15 12 T142 11 T212 7
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 117 1 T14 2 T138 8 T39 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 187 1 T251 3 T243 4 T245 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 174 1 T78 4 T43 1 T34 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T24 12 T130 11 T43 1
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T51 1 T246 9 T228 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 110 1 T263 5 T87 1 T278 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 384 1 T2 5 T3 3 T15 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 275 1 T138 10 T130 12 T204 16
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 144 1 T6 1 T14 1 T15 3



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 209 1 T133 1 T135 14 T144 3
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 250 1 T167 1 T137 1 T139 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T15 2 T136 1 T37 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 206 1 T2 1 T164 1 T130 14
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T3 3 T133 12 T152 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 138 1 T26 1 T28 1 T31 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1364 1 T4 2 T5 3 T7 3
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 293 1 T6 9 T135 9 T38 2
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 195 1 T3 12 T156 1 T138 9
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T11 1 T31 1 T15 13
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 169 1 T14 5 T39 4 T218 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 277 1 T24 13 T136 1 T130 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T28 1 T134 2 T163 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 212 1 T156 1 T38 1 T192 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 228 1 T11 1 T28 1 T31 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T263 6 T256 12 T230 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 319 1 T2 6 T51 15 T136 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 217 1 T138 11 T130 13 T152 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 97 1 T3 4 T167 1 T38 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 93 1 T149 11 T17 3 T160 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 15830 1 T1 20 T6 80 T9 18
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T133 11 T144 8 T145 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 220 1 T167 9 T139 10 T38 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 96 1 T15 1 T37 1 T143 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 197 1 T2 9 T164 7 T130 12
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T133 15 T152 4 T16 1
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T28 15 T133 8 T51 10
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 1347 1 T4 21 T5 33 T7 36
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T6 6 T159 12 T214 1
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 160 1 T208 13 T144 12 T218 13
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T11 9 T15 13 T142 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 133 1 T14 1 T39 1 T218 7
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 184 1 T130 11 T251 2 T245 10
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T28 12 T163 2 T246 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 135 1 T192 16 T207 15 T158 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 221 1 T11 13 T28 10 T15 13
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T263 17 T256 9 T230 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 294 1 T2 3 T51 7 T140 13
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 172 1 T152 5 T231 22 T147 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 58 1 T167 12 T38 8 T165 9
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 49 1 T17 3 T279 6 T280 12



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 3 45 93.75 3


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 14 1 T271 1 T107 1 T275 12
auto[0] maximum auto[ADC_CTRL_FILTER_COND_OUT] 3 1 T17 3 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 3 1 T272 1 T233 1 T276 1
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 5 1 T273 1 T277 4 - -
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 165 1 T133 1 T135 14 T144 3
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 215 1 T167 1 T137 1 T139 12
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 131 1 T136 1 T37 3 T16 4
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T2 1 T15 5 T164 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 187 1 T3 3 T133 12 T15 2
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 194 1 T26 1 T134 1 T51 13
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 199 1 T16 2 T204 9 T240 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 246 1 T6 9 T11 1 T28 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1367 1 T3 12 T4 2 T5 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T31 1 T15 13 T142 12
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 145 1 T14 5 T163 1 T138 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 222 1 T141 1 T204 1 T143 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 210 1 T28 1 T134 1 T146 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 257 1 T24 13 T136 1 T130 12
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 229 1 T11 1 T28 1 T134 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T156 1 T38 1 T263 6
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 458 1 T2 6 T3 4 T31 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 354 1 T138 11 T130 13 T152 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 15829 1 T1 20 T6 80 T9 18
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 13 1 T275 13 - - - -
auto[1] maximum auto[ADC_CTRL_FILTER_COND_OUT] 3 1 T17 3 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 11 1 T233 11 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 1 1 T277 1 - - - -
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 110 1 T133 11 T144 8 T210 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 200 1 T167 9 T139 10 T38 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 88 1 T37 1 T16 1 T143 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 150 1 T2 9 T164 7 T130 12
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T133 15 T15 1 T152 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T51 10 T155 15 T165 14
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 134 1 T244 6 T235 12 T96 4
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 201 1 T6 6 T11 9 T28 15
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 1366 1 T4 21 T5 33 T7 36
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 132 1 T15 13 T142 11 T192 8
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 114 1 T14 1 T163 2 T39 1
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T251 2 T245 10 T234 19
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 209 1 T28 12 T146 11 T78 6
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 163 1 T130 11 T192 16 T207 15
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 190 1 T11 13 T28 10 T246 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 109 1 T263 17 T230 15 T87 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 409 1 T2 3 T15 13 T51 7
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 279 1 T152 5 T231 22 T147 12



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 20952 1 T1 20 T2 7 T3 19
auto[1] auto[0] 4428 1 T2 12 T4 21 T5 33

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