Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21600

1

T1

20

T2

10

T3

4

auto[ADC_CTRL_FILTER_COND_OUT]

3780

1

T2

9

T3

15

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18990

1

T1

20

T3

3

T6

80

auto[1]

6390

1

T2

19

T3

16

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T281	1		T282	8		-	-
values[0]	72	1			T31	1		T133	12		T210	9
values[1]	686	1			T167	10		T16	2		T165	29
values[2]	642	1			T2	19		T136	1		T167	13
values[3]	644	1			T6	15		T134	2		T163	3
values[4]	743	1			T3	4		T28	11		T15	5
values[5]	705	1			T24	13		T156	1		T15	29
values[6]	615	1			T11	14		T14	6		T28	13
values[7]	1065	1			T3	15		T11	10		T28	16
values[8]	626	1			T133	18		T156	1		T130	26
values[9]	3744	1			T4	23		T5	36		T7	39
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	882	1			T2	19		T31	1		T133	12
values[1]	611	1			T6	15		T163	3		T136	1
values[2]	703	1			T28	11		T134	2		T51	23
values[3]	601	1			T3	4		T24	13		T136	1
values[4]	819	1			T14	6		T156	1		T15	34
values[5]	818	1			T28	29		T31	1		T134	1
values[6]	3278	1			T3	15		T4	23		T5	36
values[7]	479	1			T156	1		T38	1		T142	23
values[8]	1164	1			T26	1		T31	1		T142	25
values[9]	138	1			T283	1		T168	1		T242	20
minimum	15887	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T2	10		T31	1		T133	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	4		T167	10		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T163	3		T136	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	9		T167	13		T164	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T134	1		T136	1		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T28	11		T134	1		T51	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	1		T150	1		T33	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T24	1		T136	1		T139	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T15	14		T155	16		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	4		T156	1		T15	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T134	1		T138	1		T130	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T28	29		T31	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1755	1			T4	23		T5	36		T7	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	2		T11	24		T133	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T156	1		T152	5		T231	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	1		T142	12		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T31	1		T208	7		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T26	1		T142	13		T152	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T283	1		T168	1		T284	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T242	1		T281	1		T285	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T286	18		T287	1		T248	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T37	1		T16	1		T165	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	5		T243	4		T149	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T38	1		T251	3		T212	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	6		T204	16		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T38	7		T147	8		T242	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	12		T89	13		T34	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T3	3		T33	15		T254	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	12		T139	11		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	12		T155	1		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	2		T15	4		T135	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T138	8		T130	23		T165	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T138	10		T38	9		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T29	29		T133	9		T213	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	13		T133	11		T15	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T186	12		T288	7		T257	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T142	11		T39	2		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T144	12		T228	10		T253	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T142	12		T210	14		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T274	13		T108	1		T289	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T242	19		T191	9		T290	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T286	16		T287	8		T248	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T281	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T31	1		T133	12		T210	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T291	1		T292	1		T293	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T16	1		T165	15		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T167	10		T243	1		T255	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	10		T136	1		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T2	4		T167	13		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T134	1		T163	3		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	9		T134	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T3	1		T155	16		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T28	11		T15	2		T51	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T15	14		T141	1		T165	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	1		T156	1		T15	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T134	1		T138	1		T130	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	14		T14	4		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T51	1		T137	1		T130	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	2		T11	10		T28	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T133	9		T156	1		T208	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T130	13		T38	1		T231	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1776	1			T4	23		T5	36		T7	39
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	542	1			T26	1		T142	25		T152	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T282	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T210	7		T256	11		T294	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T291	3		T293	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	1		T165	14		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T243	4		T255	2		T80	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	1		T251	3		T212	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T2	5		T149	19		T168	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T38	8		T147	8		T242	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	6		T204	16		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	3		T155	1		T33	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T15	3		T51	12		T139	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	12		T165	10		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T24	12		T15	1		T135	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	8		T130	12		T218	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	2		T135	8		T138	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T51	1		T130	11		T165	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T3	13		T133	11		T15	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	9		T144	2		T145	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	13		T144	9		T295	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1035	1			T29	29		T213	13		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T142	23		T39	2		T217	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T2	1		T31	1		T133	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T2	6		T167	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T163	1		T136	1		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	9		T167	1		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T134	1		T136	1		T38	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	1		T134	1		T51	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	4		T150	1		T33	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	13		T136	1		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	13		T155	2		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	5		T156	1		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T134	1		T138	9		T130	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T28	2		T31	1		T138	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1398	1			T4	2		T5	3		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	15		T11	2		T133	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T156	1		T152	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	1		T142	12		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T31	1		T208	1		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T26	1		T142	13		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T283	1		T168	1		T284	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T242	20		T281	1		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T286	17		T287	9		T248	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T2	9		T133	11		T37	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T2	3		T167	9		T255	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T163	2		T251	2		T212	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T6	6		T167	12		T164	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T38	8		T192	16		T96	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T28	10		T51	10		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T33	10		T254	13		T296	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	10		T231	11		T246	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T15	13		T155	15		T165	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T14	1		T15	1		T145	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T130	11		T165	9		T192	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T28	27		T38	6		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T4	21		T5	33		T7	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	22		T133	15		T15	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T152	4		T231	6		T207	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T142	11		T39	1		T231	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T208	6		T144	12		T146	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T142	12		T152	5		T140	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T274	2		T108	1		T189	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T285	15		T191	8		T290	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T286	17		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T282	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T281	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T31	1		T133	1		T210	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T291	4		T292	1		T293	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	2		T165	15		T204	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T167	1		T243	5		T255	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T136	1		T37	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	6		T167	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T134	1		T163	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	9		T134	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	4		T155	2		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T28	1		T15	5		T51	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	13		T141	1		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T24	13		T156	1		T15	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T134	1		T138	9		T130	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T14	5		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T51	2		T137	1		T130	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T3	15		T11	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T133	10		T156	1		T208	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T130	14		T38	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T4	2		T5	3		T7	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	480	1			T26	1		T142	25		T152	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T133	11		T210	1		T256	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T165	14		T143	6		T158	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T167	9		T255	4		T17	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T2	9		T37	1		T251	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	3		T167	12		T147	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T163	2		T38	8		T192	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T6	6		T164	7		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T155	15		T33	10		T254	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T28	10		T51	10		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	13		T165	15		T158	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	1		T228	6		T297	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T192	8		T218	13		T186	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T11	13		T14	1		T28	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T130	11		T165	9		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	9		T28	15		T133	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T133	8		T208	7		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T130	12		T231	11		T298	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1412	1			T4	21		T5	33		T7	36
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	453	1			T142	23		T152	5		T140	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33