Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21929

1

T1

20

T2

19

T3

16

auto[ADC_CTRL_FILTER_COND_OUT]

3451

1

T3

3

T14

6

T26

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18966

1

T1

20

T2

19

T6

95

auto[1]

6414

1

T3

19

T4

23

T5

36

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	328	1			T3	4		T14	6		T28	11
values[0]	10	1			T321	1		T183	9		-	-
values[1]	676	1			T28	13		T135	9		T167	13
values[2]	650	1			T3	12		T31	1		T134	1
values[3]	698	1			T2	9		T133	12		T136	1
values[4]	778	1			T3	3		T31	1		T135	14
values[5]	3066	1			T4	23		T5	36		T7	39
values[6]	702	1			T11	10		T134	1		T163	3
values[7]	722	1			T26	1		T28	16		T133	27
values[8]	758	1			T6	15		T11	14		T15	3
values[9]	1163	1			T2	10		T24	13		T31	1
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	583	1			T28	13		T31	1		T135	9
values[1]	742	1			T3	12		T134	1		T136	1
values[2]	616	1			T2	9		T3	3		T133	12
values[3]	3225	1			T4	23		T5	36		T7	39
values[4]	685	1			T133	18		T134	1		T136	1
values[5]	642	1			T11	10		T163	3		T156	1
values[6]	922	1			T6	15		T26	1		T28	16
values[7]	657	1			T11	14		T15	3		T51	2
values[8]	1128	1			T2	10		T3	4		T14	6
values[9]	145	1			T137	1		T157	1		T39	5
minimum	16035	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	13		T31	1		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T38	19		T140	14		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T167	10		T165	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T134	1		T136	1		T218	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T2	4		T130	13		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T133	12		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1720	1			T4	23		T5	36		T7	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T135	1		T139	11		T152	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T133	9		T134	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T152	6		T192	9		T207	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	10		T156	1		T15	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T163	3		T15	14		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T6	9		T28	16		T165	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T26	1		T133	16		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	14		T15	2		T251	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T51	1		T38	1		T140	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T2	10		T3	1		T24	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T14	4		T28	11		T15	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T137	1		T157	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T145	12		T93	1		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15734	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T140	7		T228	12		T84	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T135	8		T144	9		T210	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T38	16		T243	12		T306	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	11		T165	14		T218	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T80	5		T234	18		T98	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	5		T130	13		T234	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T3	2		T224	1		T322	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T29	29		T213	13		T155	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T135	13		T139	11		T228	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T133	9		T246	9		T89	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T254	9		T243	4		T210	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	10		T51	14		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T15	12		T37	1		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	6		T165	13		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T133	11		T138	10		T130	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T251	3		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T51	1		T38	1		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T3	3		T24	12		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T14	2		T15	3		T51	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T39	2		T323	7		T225	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T145	10		T169	11		T324	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T228	10		T190	11		T325	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	1		T137	1		T143	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	4		T28	11		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T321	1		T183	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T28	13		T135	1		T167	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T38	9		T140	21		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T31	1		T165	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T134	1		T136	1		T38	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T2	4		T167	10		T130	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T133	12		T136	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T31	1		T155	16		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	1		T135	1		T152	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1724	1			T4	23		T5	36		T7	39
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T139	11		T152	6		T192	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T11	10		T134	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T163	3		T15	14		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T28	16		T165	10		T204	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	1		T133	16		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	9		T11	14		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T51	1		T206	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T2	10		T24	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T15	2		T51	11		T130	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T3	3		T145	20		T228	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T14	2		T216	10		T263	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T183	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T135	8		T144	9		T253	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T38	7		T228	10		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	11		T165	14		T147	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	9		T80	5		T234	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	5		T130	13		T218	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T224	1		T322	12		T326	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T155	1		T144	12		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	2		T135	13		T43	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T29	29		T133	9		T213	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	11		T228	6		T149	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	10		T51	14		T165	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	12		T37	1		T142	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T165	13		T204	16		T226	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	11		T138	10		T130	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	6		T15	1		T251	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T51	1		T38	1		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T24	12		T138	8		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T15	3		T51	12		T130	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T28	1		T31	1		T135	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	21		T140	1		T240	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	12		T167	1		T165	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T134	1		T136	1		T218	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	6		T130	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	3		T133	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T4	2		T5	3		T7	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T135	14		T139	12		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T133	10		T134	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T152	1		T192	1		T207	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	1		T156	1		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T163	1		T15	13		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T6	9		T28	1		T165	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T26	1		T133	12		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	1		T15	2		T251	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T51	2		T38	2		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	364	1			T2	1		T3	4		T24	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T14	5		T28	1		T15	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T137	1		T157	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T145	11		T93	1		T169	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15888	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T140	1		T228	11		T84	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T28	12		T167	12		T158	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T38	14		T140	13		T302	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T167	9		T165	14		T231	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T218	7		T234	19		T98	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	3		T130	12		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T133	11		T322	14		T320	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1375	1			T4	21		T5	33		T7	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T139	10		T152	4		T207	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T133	8		T164	7		T208	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T152	5		T192	8		T207	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	9		T15	13		T51	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T163	2		T15	13		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T6	6		T28	15		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T133	15		T16	1		T245	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	13		T15	1		T251	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	11		T168	3		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T2	9		T142	11		T33	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	1		T28	10		T51	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T39	1		T225	3		T310	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T145	11		T324	16		T220	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T274	2		T296	1		T232	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T140	6		T228	11		T190	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T3	4		T137	1		T143	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T14	5		T28	1		T216	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T321	1		T183	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T28	1		T135	9		T167	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T38	8		T140	2		T240	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	12		T31	1		T165	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T134	1		T136	1		T38	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T2	6		T167	1		T130	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T133	1		T136	1		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T31	1		T155	2		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	3		T135	14		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T4	2		T5	3		T7	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T139	12		T152	1		T192	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	1		T134	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T163	1		T15	13		T37	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T28	1		T165	14		T204	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T26	1		T133	12		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	9		T11	1		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T51	2		T206	1		T38	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T2	1		T24	13		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T15	5		T51	13		T130	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T143	15		T145	12		T228	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T14	1		T28	10		T263	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T183	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T28	12		T167	12		T210	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T38	8		T140	19		T302	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T165	14		T231	22		T158	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T38	6		T218	7		T234	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	3		T167	9		T130	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T133	11		T322	14		T326	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T155	15		T207	3		T144	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T152	4		T207	15		T43	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T4	21		T5	33		T7	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T139	10		T152	5		T192	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T11	9		T15	13		T51	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T163	2		T15	13		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T28	15		T165	9		T146	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T133	15		T245	10		T319	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	6		T11	13		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T140	11		T16	1		T104	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	9		T142	11		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T51	10		T130	11		T192	26

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33