Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25380

1

T1

20

T2

19

T3

19

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21566

1

T1

20

T3

4

T4

23

auto[ADC_CTRL_FILTER_COND_OUT]

3814

1

T2

19

T3

15

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19026

1

T1

20

T3

3

T6

80

auto[1]

6354

1

T2

19

T3

16

T4

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21190

1

T1

20

T2

14

T3

3

auto[1]

4190

1

T2

5

T3

16

T6

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	304	1			T26	1		T205	1		T283	1
values[0]	32	1			T31	1		T133	12		T292	1
values[1]	729	1			T2	9		T167	10		T16	2
values[2]	613	1			T2	10		T136	1		T167	13
values[3]	647	1			T6	15		T134	1		T163	3
values[4]	772	1			T3	4		T28	11		T134	1
values[5]	724	1			T24	13		T156	1		T15	34
values[6]	632	1			T11	14		T14	6		T28	13
values[7]	1080	1			T3	15		T11	10		T28	16
values[8]	528	1			T133	18		T156	1		T130	26
values[9]	3490	1			T4	23		T5	36		T7	39
minimum	15829	1			T1	20		T6	80		T9	18

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	734	1			T2	19		T133	12		T167	13
values[1]	594	1			T6	15		T163	3		T136	1
values[2]	670	1			T134	2		T51	23		T206	1
values[3]	667	1			T3	4		T24	13		T28	11
values[4]	765	1			T14	6		T156	1		T15	34
values[5]	832	1			T11	14		T28	29		T31	1
values[6]	3247	1			T3	15		T4	23		T5	36
values[7]	602	1			T156	1		T130	26		T38	1
values[8]	1118	1			T26	1		T31	1		T142	25
values[9]	116	1			T283	1		T242	20		T274	16
minimum	16035	1			T1	20		T6	80		T9	18

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

4428

1

T2

12

T4

21

T5

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T133	12		T37	3		T16	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T2	14		T167	13		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T163	3		T136	1		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	9		T164	8		T204	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T134	1		T136	1		T38	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T134	1		T51	11		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T150	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T24	1		T28	11		T139	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T156	1		T15	14		T155	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T14	4		T15	4		T135	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T134	1		T130	13		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	14		T28	29		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1764	1			T4	23		T5	36		T7	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	2		T11	10		T133	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T156	1		T38	1		T152	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T130	13		T142	12		T39	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T31	1		T141	1		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	440	1			T26	1		T142	13		T152	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T283	1		T274	3		T189	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T242	1		T327	1		T191	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15730	1			T1	20		T6	79		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T31	1		T167	10		T243	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	1		T16	1		T165	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T2	5		T149	19		T255	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T38	1		T251	3		T212	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	6		T204	16		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T38	7		T147	8		T235	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	12		T89	13		T34	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T3	3		T33	15		T254	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	12		T139	11		T246	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T15	12		T155	1		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	2		T15	4		T135	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T130	23		T165	13		T218	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T138	18		T38	9		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1062	1			T29	29		T213	13		T51	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	13		T133	20		T15	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T186	12		T187	1		T223	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T130	13		T142	11		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T144	12		T228	10		T253	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T142	12		T210	14		T78	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T274	13		T289	13		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T242	19		T327	12		T191	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	1		T14	1		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T243	4		T262	11		T191	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T283	1		T215	11		T314	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T26	1		T205	1		T210	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T133	12		T328	3		T294	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T31	1		T292	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T16	1		T165	15		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	4		T167	10		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T136	1		T37	3		T251	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	10		T167	13		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T134	1		T163	3		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	9		T136	1		T164	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T155	16		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T28	11		T134	1		T51	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T156	1		T15	14		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	1		T15	4		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T134	1		T192	9		T218	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	14		T14	4		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T51	9		T137	1		T130	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	2		T11	10		T28	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T156	1		T38	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T133	9		T130	13		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1741	1			T4	23		T5	36		T7	39
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	456	1			T142	25		T152	6		T140	21
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15685	1			T1	20		T6	79		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T215	8		T314	8		T282	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T210	14		T234	10		T98	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T328	2		T294	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	1		T165	14		T204	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T2	5		T243	4		T255	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T37	1		T251	3		T212	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T149	19		T168	3		T169	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T38	8		T147	8		T235	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	6		T204	16		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T3	3		T155	1		T33	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T51	12		T139	11		T246	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T15	12		T165	10		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	12		T15	4		T135	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T218	14		T186	2		T83	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T14	2		T135	8		T138	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T51	15		T130	23		T165	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	13		T133	11		T15	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T144	2		T145	20		T186	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T133	9		T130	13		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T29	29		T213	13		T144	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T142	23		T217	11		T159	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	1		T14	1		T15	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T133	1		T37	3		T16	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T2	7		T167	1		T149	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T163	1		T136	1		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	9		T164	1		T204	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T134	1		T136	1		T38	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T134	1		T51	13		T206	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	4		T150	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T24	13		T28	1		T139	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T156	1		T15	13		T155	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	5		T15	7		T135	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T134	1		T130	25		T165	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	1		T28	2		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T4	2		T5	3		T7	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	15		T11	1		T133	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T156	1		T38	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T130	14		T142	12		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T31	1		T141	1		T144	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T26	1		T142	13		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T283	1		T274	14		T189	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T242	20		T327	13		T191	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15888	1			T1	20		T6	80		T9	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T31	1		T167	1		T243	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T133	11		T37	1		T165	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	12		T167	12		T255	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T163	2		T251	2		T212	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	6		T164	7		T228	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T38	8		T192	16		T235	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T51	10		T140	11		T207	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	10		T254	13		T296	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T28	10		T139	10		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T15	13		T155	15		T165	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	1		T15	1		T145	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T130	11		T165	9		T192	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	13		T28	27		T38	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T4	21		T5	33		T7	36
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	9		T133	23		T15	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T152	4		T231	6		T207	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T130	12		T142	11		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T144	12		T146	16		T228	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T142	12		T152	5		T140	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T274	2		T189	4		T289	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T191	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T158	6		T329	6		T326	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T167	9		T262	10		T191	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T283	1		T215	9		T314	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T26	1		T205	1		T210	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T133	1		T328	3		T294	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T31	1		T292	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T16	2		T165	15		T204	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T2	6		T167	1		T243	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T136	1		T37	3		T251	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	1		T167	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	1		T163	1		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	9		T136	1		T164	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	4		T155	2		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	1		T134	1		T51	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T156	1		T15	13		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T24	13		T15	7		T135	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T134	1		T192	1		T218	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T14	5		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T51	17		T137	1		T130	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	15		T11	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T156	1		T38	1		T157	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T133	10		T130	14		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T4	2		T5	3		T7	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T142	25		T152	1		T140	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15829	1			T1	20		T6	80		T9	18
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T215	10		T314	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T210	9		T234	10		T98	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T133	11		T328	2		T294	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T165	14		T143	6		T158	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T2	3		T167	9		T255	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T37	1		T251	2		T212	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T2	9		T167	12		T168	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T163	2		T38	8		T192	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	6		T164	7		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T155	15		T33	10		T254	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T28	10		T51	10		T139	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	13		T165	15		T244	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	1		T228	6		T297	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T192	8		T218	13		T158	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T11	13		T14	1		T28	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T51	7		T130	11		T165	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	9		T28	15		T133	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T208	7		T231	6		T207	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T133	8		T130	12		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T4	21		T5	33		T7	36
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T142	23		T152	5		T140	19

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20952

1

T1

20

T2

7

T3

19

auto[1]

auto[0]

4428

1

T2

12

T4

21

T5

33