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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.37


Total test records in report: 918
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T798 /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2907937287 Apr 28 02:52:12 PM PDT 24 Apr 28 02:58:39 PM PDT 24 578911149286 ps
T200 /workspace/coverage/default/11.adc_ctrl_fsm_reset.2799997347 Apr 28 02:46:02 PM PDT 24 Apr 28 02:53:02 PM PDT 24 124350329752 ps
T799 /workspace/coverage/default/22.adc_ctrl_filters_polled.2197002091 Apr 28 02:47:50 PM PDT 24 Apr 28 02:57:41 PM PDT 24 488839639553 ps
T800 /workspace/coverage/default/46.adc_ctrl_fsm_reset.1941209138 Apr 28 02:53:14 PM PDT 24 Apr 28 03:01:03 PM PDT 24 136353135405 ps
T801 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1806619735 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:11 PM PDT 24 305566661 ps
T48 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2953175105 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:16 PM PDT 24 4372093478 ps
T802 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1198785744 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:11 PM PDT 24 511532665 ps
T49 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2050897663 Apr 28 01:19:29 PM PDT 24 Apr 28 01:19:39 PM PDT 24 3807225418 ps
T52 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2165258708 Apr 28 01:19:45 PM PDT 24 Apr 28 01:20:08 PM PDT 24 8661359613 ps
T55 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1920386422 Apr 28 01:19:46 PM PDT 24 Apr 28 01:19:48 PM PDT 24 411568899 ps
T123 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2390326611 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:10 PM PDT 24 302155626 ps
T803 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3850256652 Apr 28 01:19:51 PM PDT 24 Apr 28 01:19:52 PM PDT 24 541511233 ps
T50 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4011622547 Apr 28 01:19:31 PM PDT 24 Apr 28 01:19:35 PM PDT 24 476689552 ps
T53 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3821755198 Apr 28 01:19:37 PM PDT 24 Apr 28 01:19:39 PM PDT 24 4806283908 ps
T804 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2142339936 Apr 28 01:20:08 PM PDT 24 Apr 28 01:20:09 PM PDT 24 390413508 ps
T124 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.213718869 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:16 PM PDT 24 4820215695 ps
T59 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.867446187 Apr 28 01:19:51 PM PDT 24 Apr 28 01:19:54 PM PDT 24 327770593 ps
T805 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1983138320 Apr 28 01:19:49 PM PDT 24 Apr 28 01:19:52 PM PDT 24 479948347 ps
T125 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2163506717 Apr 28 01:19:50 PM PDT 24 Apr 28 01:19:59 PM PDT 24 2638333354 ps
T60 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1014805438 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:09 PM PDT 24 1051479998 ps
T806 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2656366527 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:09 PM PDT 24 497678163 ps
T109 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3550256301 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:12 PM PDT 24 535799348 ps
T97 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1314193915 Apr 28 01:19:40 PM PDT 24 Apr 28 01:19:42 PM PDT 24 442188913 ps
T69 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4269277881 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:13 PM PDT 24 580604226 ps
T807 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2763144715 Apr 28 01:20:08 PM PDT 24 Apr 28 01:20:10 PM PDT 24 484316312 ps
T54 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2806919285 Apr 28 01:19:33 PM PDT 24 Apr 28 01:19:39 PM PDT 24 8516923608 ps
T808 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1590011082 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:09 PM PDT 24 512988081 ps
T70 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2793106512 Apr 28 01:20:02 PM PDT 24 Apr 28 01:20:26 PM PDT 24 8439461243 ps
T64 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4187462273 Apr 28 01:19:56 PM PDT 24 Apr 28 01:19:58 PM PDT 24 630244095 ps
T126 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3087729622 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:08 PM PDT 24 465923209 ps
T110 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2581602320 Apr 28 01:19:49 PM PDT 24 Apr 28 01:19:53 PM PDT 24 731794401 ps
T61 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.986862613 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:09 PM PDT 24 463592420 ps
T62 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2472257268 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:08 PM PDT 24 1087293999 ps
T65 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1414377126 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:08 PM PDT 24 522841792 ps
T352 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.381602741 Apr 28 01:20:00 PM PDT 24 Apr 28 01:20:07 PM PDT 24 4329914192 ps
T127 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.661556280 Apr 28 01:20:04 PM PDT 24 Apr 28 01:20:06 PM PDT 24 2053485112 ps
T809 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2845710749 Apr 28 01:19:47 PM PDT 24 Apr 28 01:20:50 PM PDT 24 52774210894 ps
T71 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3474717736 Apr 28 01:20:01 PM PDT 24 Apr 28 01:20:04 PM PDT 24 689553680 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.315220762 Apr 28 01:19:28 PM PDT 24 Apr 28 01:19:55 PM PDT 24 40769914765 ps
T128 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1143785326 Apr 28 01:19:59 PM PDT 24 Apr 28 01:20:01 PM PDT 24 2461852689 ps
T129 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2076080012 Apr 28 01:19:51 PM PDT 24 Apr 28 01:19:58 PM PDT 24 2523012317 ps
T810 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1510681297 Apr 28 01:19:53 PM PDT 24 Apr 28 01:19:54 PM PDT 24 315939928 ps
T63 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2203242899 Apr 28 01:19:59 PM PDT 24 Apr 28 01:20:02 PM PDT 24 618462122 ps
T811 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3143665494 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:13 PM PDT 24 399435918 ps
T812 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.940361742 Apr 28 01:19:30 PM PDT 24 Apr 28 01:19:34 PM PDT 24 395265959 ps
T353 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.188513446 Apr 28 01:19:53 PM PDT 24 Apr 28 01:20:04 PM PDT 24 4024048937 ps
T813 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4199092666 Apr 28 01:19:50 PM PDT 24 Apr 28 01:19:52 PM PDT 24 558109777 ps
T814 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1058055206 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:12 PM PDT 24 560086713 ps
T815 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1264728512 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:07 PM PDT 24 309169982 ps
T72 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2034802973 Apr 28 01:19:39 PM PDT 24 Apr 28 01:19:42 PM PDT 24 903494876 ps
T816 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1325649094 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:12 PM PDT 24 2400733917 ps
T817 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3874750774 Apr 28 01:19:58 PM PDT 24 Apr 28 01:20:00 PM PDT 24 600141828 ps
T818 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4127882101 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:10 PM PDT 24 456871449 ps
T819 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4136093819 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:12 PM PDT 24 407264202 ps
T820 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4248560736 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:10 PM PDT 24 334411328 ps
T821 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2072990985 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:11 PM PDT 24 377877780 ps
T822 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2797189699 Apr 28 01:19:38 PM PDT 24 Apr 28 01:19:40 PM PDT 24 462629366 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2731107100 Apr 28 01:19:29 PM PDT 24 Apr 28 01:19:34 PM PDT 24 571077925 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1669903026 Apr 28 01:20:04 PM PDT 24 Apr 28 01:20:06 PM PDT 24 538456223 ps
T824 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1617786747 Apr 28 01:19:55 PM PDT 24 Apr 28 01:19:59 PM PDT 24 531994654 ps
T825 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2976622064 Apr 28 01:19:59 PM PDT 24 Apr 28 01:20:01 PM PDT 24 654935083 ps
T826 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3889359050 Apr 28 01:19:36 PM PDT 24 Apr 28 01:19:41 PM PDT 24 2566636968 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.979594671 Apr 28 01:19:59 PM PDT 24 Apr 28 01:20:02 PM PDT 24 2473513282 ps
T828 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3324157323 Apr 28 01:19:41 PM PDT 24 Apr 28 01:19:45 PM PDT 24 2212202088 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.966904502 Apr 28 01:19:32 PM PDT 24 Apr 28 01:20:31 PM PDT 24 25989269921 ps
T829 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3782261780 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:08 PM PDT 24 459575727 ps
T830 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3045863860 Apr 28 01:20:04 PM PDT 24 Apr 28 01:20:06 PM PDT 24 592095449 ps
T831 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1798348187 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:11 PM PDT 24 478887800 ps
T832 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2344354332 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:15 PM PDT 24 7921425274 ps
T114 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2894159617 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:06 PM PDT 24 358087595 ps
T833 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2688531365 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:09 PM PDT 24 3364176378 ps
T834 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2311051239 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:13 PM PDT 24 342766922 ps
T835 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.616976698 Apr 28 01:20:01 PM PDT 24 Apr 28 01:20:03 PM PDT 24 586561588 ps
T836 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4214408283 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:09 PM PDT 24 418702818 ps
T73 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4006562705 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:28 PM PDT 24 8736580227 ps
T837 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3562048409 Apr 28 01:19:59 PM PDT 24 Apr 28 01:20:01 PM PDT 24 449062579 ps
T838 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1433160674 Apr 28 01:19:52 PM PDT 24 Apr 28 01:19:54 PM PDT 24 438404063 ps
T839 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1337050880 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:12 PM PDT 24 432251508 ps
T840 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.866881881 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:14 PM PDT 24 2910032785 ps
T841 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.845738399 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:09 PM PDT 24 288558848 ps
T354 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.441115598 Apr 28 01:19:57 PM PDT 24 Apr 28 01:20:09 PM PDT 24 4316126533 ps
T842 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3315293963 Apr 28 01:19:50 PM PDT 24 Apr 28 01:19:51 PM PDT 24 590884469 ps
T843 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.362202270 Apr 28 01:19:56 PM PDT 24 Apr 28 01:20:04 PM PDT 24 4874264051 ps
T74 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3213010915 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:11 PM PDT 24 5023821530 ps
T844 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2969012517 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:12 PM PDT 24 545260532 ps
T75 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3323869396 Apr 28 01:19:48 PM PDT 24 Apr 28 01:19:55 PM PDT 24 4228161738 ps
T845 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.510995725 Apr 28 01:19:58 PM PDT 24 Apr 28 01:20:01 PM PDT 24 522891525 ps
T846 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3808437071 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:08 PM PDT 24 303194521 ps
T847 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.71117294 Apr 28 01:19:55 PM PDT 24 Apr 28 01:19:57 PM PDT 24 575162187 ps
T848 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2082329800 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:12 PM PDT 24 417197062 ps
T849 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2745823334 Apr 28 01:19:37 PM PDT 24 Apr 28 01:19:39 PM PDT 24 584592724 ps
T850 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1085708536 Apr 28 01:19:35 PM PDT 24 Apr 28 01:19:38 PM PDT 24 763392182 ps
T851 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.623094706 Apr 28 01:19:57 PM PDT 24 Apr 28 01:20:00 PM PDT 24 461730588 ps
T115 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.167517060 Apr 28 01:19:31 PM PDT 24 Apr 28 01:19:35 PM PDT 24 498667881 ps
T852 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2270919257 Apr 28 01:20:00 PM PDT 24 Apr 28 01:20:02 PM PDT 24 329230865 ps
T853 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1874944042 Apr 28 01:19:45 PM PDT 24 Apr 28 01:19:48 PM PDT 24 992644765 ps
T854 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3790084508 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:07 PM PDT 24 528058307 ps
T855 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4028272606 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:13 PM PDT 24 367274717 ps
T856 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.159047521 Apr 28 01:19:59 PM PDT 24 Apr 28 01:20:02 PM PDT 24 2258257653 ps
T857 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2657367934 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:21 PM PDT 24 2465695650 ps
T858 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.451366914 Apr 28 01:19:34 PM PDT 24 Apr 28 01:19:36 PM PDT 24 1136141559 ps
T859 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.222825000 Apr 28 01:19:49 PM PDT 24 Apr 28 01:20:00 PM PDT 24 4459983797 ps
T860 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1418688663 Apr 28 01:19:50 PM PDT 24 Apr 28 01:19:52 PM PDT 24 448070013 ps
T861 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1047474897 Apr 28 01:19:55 PM PDT 24 Apr 28 01:19:56 PM PDT 24 329289889 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1255651850 Apr 28 01:19:28 PM PDT 24 Apr 28 01:19:34 PM PDT 24 591310673 ps
T863 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3436461824 Apr 28 01:19:31 PM PDT 24 Apr 28 01:19:37 PM PDT 24 535747243 ps
T864 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3984018897 Apr 28 01:19:40 PM PDT 24 Apr 28 01:20:00 PM PDT 24 8263874534 ps
T865 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1214525411 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:20 PM PDT 24 8388733010 ps
T866 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1034527280 Apr 28 01:20:02 PM PDT 24 Apr 28 01:20:04 PM PDT 24 432265247 ps
T867 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2425282889 Apr 28 01:19:39 PM PDT 24 Apr 28 01:19:41 PM PDT 24 616246741 ps
T868 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2746333623 Apr 28 01:19:34 PM PDT 24 Apr 28 01:19:36 PM PDT 24 697426461 ps
T869 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2768796123 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:12 PM PDT 24 491963896 ps
T870 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2070496912 Apr 28 01:19:48 PM PDT 24 Apr 28 01:19:49 PM PDT 24 348345866 ps
T871 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.252407281 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:09 PM PDT 24 509541906 ps
T116 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3848887302 Apr 28 01:19:40 PM PDT 24 Apr 28 01:19:44 PM PDT 24 828426012 ps
T872 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3479360676 Apr 28 01:20:00 PM PDT 24 Apr 28 01:20:01 PM PDT 24 578889138 ps
T873 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2360218760 Apr 28 01:19:55 PM PDT 24 Apr 28 01:20:05 PM PDT 24 3848408685 ps
T117 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3666264892 Apr 28 01:19:40 PM PDT 24 Apr 28 01:19:43 PM PDT 24 1148913862 ps
T874 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.778760256 Apr 28 01:19:31 PM PDT 24 Apr 28 01:19:36 PM PDT 24 819755900 ps
T875 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3781859435 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:14 PM PDT 24 593876182 ps
T118 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1507828886 Apr 28 01:19:38 PM PDT 24 Apr 28 01:19:42 PM PDT 24 1279319114 ps
T876 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3312882733 Apr 28 01:19:35 PM PDT 24 Apr 28 01:19:37 PM PDT 24 650705095 ps
T877 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.626159606 Apr 28 01:19:52 PM PDT 24 Apr 28 01:19:55 PM PDT 24 678693790 ps
T119 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3376730107 Apr 28 01:19:34 PM PDT 24 Apr 28 01:19:37 PM PDT 24 441911753 ps
T878 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2491248489 Apr 28 01:19:51 PM PDT 24 Apr 28 01:19:52 PM PDT 24 444290878 ps
T879 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.979974793 Apr 28 01:19:38 PM PDT 24 Apr 28 01:19:40 PM PDT 24 470338361 ps
T880 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1840531893 Apr 28 01:19:59 PM PDT 24 Apr 28 01:20:03 PM PDT 24 4733506049 ps
T881 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3122414812 Apr 28 01:19:51 PM PDT 24 Apr 28 01:20:02 PM PDT 24 5220069292 ps
T882 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.36344332 Apr 28 01:19:51 PM PDT 24 Apr 28 01:19:53 PM PDT 24 582035080 ps
T883 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2810586237 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:09 PM PDT 24 356913177 ps
T884 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.277949162 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:07 PM PDT 24 344097468 ps
T885 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3697097361 Apr 28 01:19:56 PM PDT 24 Apr 28 01:19:58 PM PDT 24 430737471 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.422125074 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:10 PM PDT 24 507328406 ps
T887 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2802014751 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:07 PM PDT 24 498472454 ps
T888 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1101312550 Apr 28 01:20:04 PM PDT 24 Apr 28 01:20:08 PM PDT 24 4060792414 ps
T122 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.559257116 Apr 28 01:20:01 PM PDT 24 Apr 28 01:20:03 PM PDT 24 573190363 ps
T889 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3131833349 Apr 28 01:20:01 PM PDT 24 Apr 28 01:20:03 PM PDT 24 467499889 ps
T890 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.472676985 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:12 PM PDT 24 392186423 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3649711733 Apr 28 01:19:36 PM PDT 24 Apr 28 01:19:38 PM PDT 24 1177449354 ps
T891 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2126150910 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:12 PM PDT 24 449652658 ps
T892 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3097892699 Apr 28 01:20:08 PM PDT 24 Apr 28 01:20:10 PM PDT 24 396320764 ps
T893 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.401912194 Apr 28 01:19:57 PM PDT 24 Apr 28 01:19:59 PM PDT 24 517661104 ps
T894 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3546445973 Apr 28 01:20:04 PM PDT 24 Apr 28 01:20:08 PM PDT 24 4243625578 ps
T895 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.197016366 Apr 28 01:20:08 PM PDT 24 Apr 28 01:20:10 PM PDT 24 385961951 ps
T896 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.814454376 Apr 28 01:19:28 PM PDT 24 Apr 28 01:19:34 PM PDT 24 2801670156 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3718778257 Apr 28 01:19:32 PM PDT 24 Apr 28 01:19:35 PM PDT 24 318683996 ps
T898 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2176483967 Apr 28 01:19:51 PM PDT 24 Apr 28 01:19:56 PM PDT 24 4508577387 ps
T899 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2758815573 Apr 28 01:19:55 PM PDT 24 Apr 28 01:19:57 PM PDT 24 281552749 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1752135789 Apr 28 01:19:40 PM PDT 24 Apr 28 01:19:53 PM PDT 24 4569771173 ps
T901 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.903763901 Apr 28 01:19:55 PM PDT 24 Apr 28 01:20:07 PM PDT 24 8279150768 ps
T121 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3169866710 Apr 28 01:20:03 PM PDT 24 Apr 28 01:20:04 PM PDT 24 376509437 ps
T902 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2561752580 Apr 28 01:20:09 PM PDT 24 Apr 28 01:20:23 PM PDT 24 4586346216 ps
T903 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.506723 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:25 PM PDT 24 8039331296 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2722965725 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:07 PM PDT 24 601782318 ps
T905 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3899408378 Apr 28 01:20:04 PM PDT 24 Apr 28 01:20:05 PM PDT 24 313975729 ps
T906 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2666281233 Apr 28 01:19:55 PM PDT 24 Apr 28 01:19:58 PM PDT 24 543820241 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1586231788 Apr 28 01:19:38 PM PDT 24 Apr 28 01:21:18 PM PDT 24 43523244501 ps
T908 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1215300758 Apr 28 01:19:55 PM PDT 24 Apr 28 01:19:57 PM PDT 24 521782633 ps
T909 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2997394687 Apr 28 01:20:06 PM PDT 24 Apr 28 01:20:08 PM PDT 24 368892064 ps
T910 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3156736292 Apr 28 01:20:07 PM PDT 24 Apr 28 01:20:10 PM PDT 24 355726496 ps
T911 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2031787765 Apr 28 01:20:10 PM PDT 24 Apr 28 01:20:12 PM PDT 24 292369114 ps
T912 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.823235877 Apr 28 01:20:05 PM PDT 24 Apr 28 01:20:07 PM PDT 24 486785838 ps
T913 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3334124895 Apr 28 01:19:29 PM PDT 24 Apr 28 01:19:33 PM PDT 24 428378521 ps
T914 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.293357610 Apr 28 01:19:45 PM PDT 24 Apr 28 01:19:48 PM PDT 24 603947591 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2878859278 Apr 28 01:19:40 PM PDT 24 Apr 28 01:20:04 PM PDT 24 27347797525 ps
T916 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2425534106 Apr 28 01:19:46 PM PDT 24 Apr 28 01:19:48 PM PDT 24 394610728 ps
T917 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3318983237 Apr 28 01:20:01 PM PDT 24 Apr 28 01:20:03 PM PDT 24 435093584 ps
T918 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2235712463 Apr 28 01:20:03 PM PDT 24 Apr 28 01:20:04 PM PDT 24 647010178 ps

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.78874196
Short name T6
Test name
Test status
Simulation time 126328751922 ps
CPU time 329.56 seconds
Started Apr 28 02:53:14 PM PDT 24
Finished Apr 28 02:58:44 PM PDT 24
Peak memory 210972 kb
Host smart-225b32df-df40-49ed-bb1d-b222dc2f1175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78874196 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.78874196
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.307869920
Short name T15
Test name
Test status
Simulation time 492600382328 ps
CPU time 256.26 seconds
Started Apr 28 02:47:33 PM PDT 24
Finished Apr 28 02:51:50 PM PDT 24
Peak memory 210680 kb
Host smart-3178155a-be5f-418e-8a93-d9c3cecd1fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307869920 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.307869920
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1308038784
Short name T28
Test name
Test status
Simulation time 576537652174 ps
CPU time 296.36 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:50:49 PM PDT 24
Peak memory 202312 kb
Host smart-441dc256-0ef4-408f-95b8-70d82ee48984
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308038784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1308038784
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3282502898
Short name T3
Test name
Test status
Simulation time 484107721675 ps
CPU time 296.07 seconds
Started Apr 28 02:51:04 PM PDT 24
Finished Apr 28 02:56:01 PM PDT 24
Peak memory 202392 kb
Host smart-89adf375-606a-4374-bbf5-eb9092ec4081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282502898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3282502898
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2118547580
Short name T38
Test name
Test status
Simulation time 503267267149 ps
CPU time 351.6 seconds
Started Apr 28 02:49:55 PM PDT 24
Finished Apr 28 02:55:47 PM PDT 24
Peak memory 218496 kb
Host smart-8b8a0262-0158-445f-81ce-d8bb86eb9460
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118547580 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2118547580
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1936987281
Short name T130
Test name
Test status
Simulation time 586496846701 ps
CPU time 1389.07 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 03:09:01 PM PDT 24
Peak memory 202292 kb
Host smart-64706a36-6c40-4816-85f4-0df7064473ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936987281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1936987281
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2035886947
Short name T44
Test name
Test status
Simulation time 117760804070 ps
CPU time 596.71 seconds
Started Apr 28 02:49:35 PM PDT 24
Finished Apr 28 02:59:32 PM PDT 24
Peak memory 202728 kb
Host smart-41e1d241-9a2b-44e4-a9dc-b4b1b873c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035886947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2035886947
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3307511864
Short name T133
Test name
Test status
Simulation time 530597767042 ps
CPU time 214.4 seconds
Started Apr 28 02:51:20 PM PDT 24
Finished Apr 28 02:54:55 PM PDT 24
Peak memory 202224 kb
Host smart-a9a40249-7c20-44bd-83f3-dfcf1ade747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307511864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3307511864
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3249149030
Short name T144
Test name
Test status
Simulation time 543597366638 ps
CPU time 650.39 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:56:50 PM PDT 24
Peak memory 202308 kb
Host smart-365e1c7d-d749-4916-a288-316e4bde8556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249149030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3249149030
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.4269277881
Short name T69
Test name
Test status
Simulation time 580604226 ps
CPU time 2.97 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:13 PM PDT 24
Peak memory 201396 kb
Host smart-ae8e2ad8-584a-447c-aee6-bb2be9c656b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269277881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.4269277881
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4219236609
Short name T165
Test name
Test status
Simulation time 520990641878 ps
CPU time 280.21 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:50:13 PM PDT 24
Peak memory 202316 kb
Host smart-f1340579-1583-447b-a620-747a43154fd3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219236609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4219236609
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3713566402
Short name T148
Test name
Test status
Simulation time 571656948317 ps
CPU time 1426.4 seconds
Started Apr 28 02:46:05 PM PDT 24
Finished Apr 28 03:09:52 PM PDT 24
Peak memory 202324 kb
Host smart-66ee83cd-f87a-4abd-809e-6b30da5cd37f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713566402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3713566402
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1166584823
Short name T215
Test name
Test status
Simulation time 548093735978 ps
CPU time 1189.32 seconds
Started Apr 28 02:53:14 PM PDT 24
Finished Apr 28 03:13:04 PM PDT 24
Peak memory 202296 kb
Host smart-c4dcba58-f79e-4f7c-bf39-ffc978b58ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166584823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1166584823
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1813515852
Short name T153
Test name
Test status
Simulation time 421841003 ps
CPU time 1.61 seconds
Started Apr 28 02:45:34 PM PDT 24
Finished Apr 28 02:45:36 PM PDT 24
Peak memory 202032 kb
Host smart-0969847d-a724-4025-b5d7-a330bcd6850a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813515852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1813515852
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.4193338585
Short name T12
Test name
Test status
Simulation time 600766596616 ps
CPU time 1512.17 seconds
Started Apr 28 02:47:56 PM PDT 24
Finished Apr 28 03:13:09 PM PDT 24
Peak memory 202384 kb
Host smart-622129bf-9a9c-4975-ab6d-73793c41bfd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193338585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.4193338585
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1912151704
Short name T152
Test name
Test status
Simulation time 403956307172 ps
CPU time 924.14 seconds
Started Apr 28 02:49:40 PM PDT 24
Finished Apr 28 03:05:05 PM PDT 24
Peak memory 202300 kb
Host smart-bef445af-2fc7-4542-aee4-c20ff36a9673
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912151704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1912151704
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4011622547
Short name T50
Test name
Test status
Simulation time 476689552 ps
CPU time 1.84 seconds
Started Apr 28 01:19:31 PM PDT 24
Finished Apr 28 01:19:35 PM PDT 24
Peak memory 201216 kb
Host smart-5436e91d-e52e-454b-a905-bc277dcd5c0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011622547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4011622547
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2636731461
Short name T77
Test name
Test status
Simulation time 4791176772 ps
CPU time 2.12 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:45:35 PM PDT 24
Peak memory 217936 kb
Host smart-5ebb1b28-48fb-484d-95bc-077e0a72d05b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636731461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2636731461
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2617526771
Short name T167
Test name
Test status
Simulation time 364929863569 ps
CPU time 882.72 seconds
Started Apr 28 02:46:48 PM PDT 24
Finished Apr 28 03:01:31 PM PDT 24
Peak memory 202360 kb
Host smart-dd5c4b74-7bdd-4a4c-9467-e8ede0e13cf7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617526771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2617526771
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3206762141
Short name T78
Test name
Test status
Simulation time 513024927520 ps
CPU time 276.71 seconds
Started Apr 28 02:47:33 PM PDT 24
Finished Apr 28 02:52:11 PM PDT 24
Peak memory 202408 kb
Host smart-7104c17c-0b8d-4425-a8eb-bf102f57c809
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206762141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3206762141
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2166913828
Short name T274
Test name
Test status
Simulation time 530824670235 ps
CPU time 1217.24 seconds
Started Apr 28 02:46:32 PM PDT 24
Finished Apr 28 03:06:50 PM PDT 24
Peak memory 202272 kb
Host smart-caeba164-1bf4-46f0-a4bd-9b4e0078983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166913828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2166913828
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1041681273
Short name T145
Test name
Test status
Simulation time 507260984651 ps
CPU time 305.14 seconds
Started Apr 28 02:46:43 PM PDT 24
Finished Apr 28 02:51:49 PM PDT 24
Peak memory 202284 kb
Host smart-0ef92f54-10b1-479c-a557-939588805470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041681273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1041681273
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3425145205
Short name T218
Test name
Test status
Simulation time 364097388483 ps
CPU time 787.85 seconds
Started Apr 28 02:52:28 PM PDT 24
Finished Apr 28 03:05:37 PM PDT 24
Peak memory 202272 kb
Host smart-2ca43ef6-8854-4def-9667-a2e00798b62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425145205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3425145205
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.4237028925
Short name T17
Test name
Test status
Simulation time 96887896378 ps
CPU time 92.36 seconds
Started Apr 28 02:51:19 PM PDT 24
Finished Apr 28 02:52:52 PM PDT 24
Peak memory 210716 kb
Host smart-5031e990-7b92-4e0d-8798-624b5bab9c78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237028925 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.4237028925
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.508310668
Short name T228
Test name
Test status
Simulation time 514394527640 ps
CPU time 616.87 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 02:56:08 PM PDT 24
Peak memory 202292 kb
Host smart-0a42147e-4f0a-4e82-9658-afdd761a74fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508310668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.508310668
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.900512035
Short name T220
Test name
Test status
Simulation time 501763224433 ps
CPU time 1211.1 seconds
Started Apr 28 02:46:22 PM PDT 24
Finished Apr 28 03:06:34 PM PDT 24
Peak memory 202420 kb
Host smart-a30bce9a-625e-4351-9456-83bc64ed5b94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900512035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gati
ng.900512035
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3330937374
Short name T142
Test name
Test status
Simulation time 325125142024 ps
CPU time 704.63 seconds
Started Apr 28 02:53:44 PM PDT 24
Finished Apr 28 03:05:29 PM PDT 24
Peak memory 202340 kb
Host smart-3507da24-21bf-4938-a00b-6399c94c3cd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330937374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3330937374
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2099012190
Short name T310
Test name
Test status
Simulation time 391462326326 ps
CPU time 943.92 seconds
Started Apr 28 02:45:36 PM PDT 24
Finished Apr 28 03:01:21 PM PDT 24
Peak memory 202368 kb
Host smart-c5132373-7b5d-4405-84e6-f67f3e9cce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099012190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2099012190
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.637943037
Short name T204
Test name
Test status
Simulation time 493971596291 ps
CPU time 602.05 seconds
Started Apr 28 02:52:58 PM PDT 24
Finished Apr 28 03:03:01 PM PDT 24
Peak memory 202384 kb
Host smart-869eb8ef-6380-41af-a46f-9e19ea0e1538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637943037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.637943037
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3821755198
Short name T53
Test name
Test status
Simulation time 4806283908 ps
CPU time 2.22 seconds
Started Apr 28 01:19:37 PM PDT 24
Finished Apr 28 01:19:39 PM PDT 24
Peak memory 201396 kb
Host smart-e89e5044-3a71-467c-8409-82724df9144c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821755198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3821755198
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2034233941
Short name T2
Test name
Test status
Simulation time 348623327498 ps
CPU time 630.53 seconds
Started Apr 28 02:47:04 PM PDT 24
Finished Apr 28 02:57:35 PM PDT 24
Peak memory 202292 kb
Host smart-6540b2b1-38bf-46ec-9ecd-43b175af23b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034233941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2034233941
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.977606575
Short name T210
Test name
Test status
Simulation time 332236550783 ps
CPU time 385.04 seconds
Started Apr 28 02:48:52 PM PDT 24
Finished Apr 28 02:55:18 PM PDT 24
Peak memory 202396 kb
Host smart-1523fc10-6408-4d25-bc84-4afbc2fb977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977606575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.977606575
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1297686295
Short name T304
Test name
Test status
Simulation time 489733476022 ps
CPU time 1111.24 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 03:04:23 PM PDT 24
Peak memory 202268 kb
Host smart-8f131471-f628-4763-8ee1-d0eb491a1483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297686295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1297686295
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.266512142
Short name T238
Test name
Test status
Simulation time 495024415504 ps
CPU time 260.06 seconds
Started Apr 28 02:53:31 PM PDT 24
Finished Apr 28 02:57:51 PM PDT 24
Peak memory 202236 kb
Host smart-969b194f-2a29-4d94-b6f8-6c22f9221167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266512142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
266512142
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.167517060
Short name T115
Test name
Test status
Simulation time 498667881 ps
CPU time 2.03 seconds
Started Apr 28 01:19:31 PM PDT 24
Finished Apr 28 01:19:35 PM PDT 24
Peak memory 201376 kb
Host smart-2555fd1f-d38a-4076-a519-d16d8917b955
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167517060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.167517060
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.890475220
Short name T225
Test name
Test status
Simulation time 540323765311 ps
CPU time 1325.2 seconds
Started Apr 28 02:53:03 PM PDT 24
Finished Apr 28 03:15:09 PM PDT 24
Peak memory 202288 kb
Host smart-65be7250-4672-448f-874e-9ca6eec257a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890475220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.890475220
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1405184116
Short name T188
Test name
Test status
Simulation time 531125663007 ps
CPU time 394.48 seconds
Started Apr 28 02:46:08 PM PDT 24
Finished Apr 28 02:52:43 PM PDT 24
Peak memory 202316 kb
Host smart-b3c65ce7-f583-4520-bc78-240b701e1b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405184116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1405184116
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.541542159
Short name T158
Test name
Test status
Simulation time 353673986961 ps
CPU time 187.69 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:48:51 PM PDT 24
Peak memory 202332 kb
Host smart-8ea90e57-d7fb-44ad-ba06-e16154cdc242
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541542159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.541542159
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3604248873
Short name T191
Test name
Test status
Simulation time 332238244841 ps
CPU time 433.87 seconds
Started Apr 28 02:46:26 PM PDT 24
Finished Apr 28 02:53:41 PM PDT 24
Peak memory 202316 kb
Host smart-3aecb538-2aba-428f-8f9c-6c3613af1776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604248873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3604248873
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.27720361
Short name T183
Test name
Test status
Simulation time 605214582434 ps
CPU time 276.99 seconds
Started Apr 28 02:45:42 PM PDT 24
Finished Apr 28 02:50:21 PM PDT 24
Peak memory 202304 kb
Host smart-3d84f960-47bd-4c7d-b4fd-f3f51e1472d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27720361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gating
.27720361
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2358857202
Short name T277
Test name
Test status
Simulation time 237675453821 ps
CPU time 68.96 seconds
Started Apr 28 02:48:22 PM PDT 24
Finished Apr 28 02:49:31 PM PDT 24
Peak memory 210672 kb
Host smart-0466276c-782a-4ae8-b917-404500920474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358857202 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2358857202
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2010347967
Short name T300
Test name
Test status
Simulation time 328962796547 ps
CPU time 200.81 seconds
Started Apr 28 02:46:22 PM PDT 24
Finished Apr 28 02:49:43 PM PDT 24
Peak memory 202324 kb
Host smart-034b673a-eff9-4704-acab-fb349b43688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010347967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2010347967
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3024200027
Short name T257
Test name
Test status
Simulation time 488513843943 ps
CPU time 1232.1 seconds
Started Apr 28 02:49:41 PM PDT 24
Finished Apr 28 03:10:14 PM PDT 24
Peak memory 202212 kb
Host smart-ca002d0e-60d5-4767-8879-dc205e438073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024200027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3024200027
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2472257268
Short name T62
Test name
Test status
Simulation time 1087293999 ps
CPU time 2.85 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 217744 kb
Host smart-4c413ed8-1783-4964-8d9e-d608b0179b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472257268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2472257268
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3216357973
Short name T41
Test name
Test status
Simulation time 205659829996 ps
CPU time 167.82 seconds
Started Apr 28 02:45:30 PM PDT 24
Finished Apr 28 02:48:18 PM PDT 24
Peak memory 210944 kb
Host smart-8620ba02-29b8-4846-b9f2-d9bcb390f281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216357973 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3216357973
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1053330622
Short name T248
Test name
Test status
Simulation time 328708862359 ps
CPU time 735.88 seconds
Started Apr 28 02:50:42 PM PDT 24
Finished Apr 28 03:02:58 PM PDT 24
Peak memory 202376 kb
Host smart-281e8b92-76d7-41f0-a89c-f674c2b3af8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053330622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1053330622
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3621444668
Short name T31
Test name
Test status
Simulation time 489682171292 ps
CPU time 1195.12 seconds
Started Apr 28 02:51:26 PM PDT 24
Finished Apr 28 03:11:22 PM PDT 24
Peak memory 202312 kb
Host smart-98a8c74b-5ac4-4761-a777-52e0eadeef05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621444668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3621444668
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.637307654
Short name T233
Test name
Test status
Simulation time 361897910516 ps
CPU time 228.51 seconds
Started Apr 28 02:52:38 PM PDT 24
Finished Apr 28 02:56:27 PM PDT 24
Peak memory 202284 kb
Host smart-b1dade4f-7c58-4fe0-b002-6bacc74a1fe2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637307654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.637307654
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3847912550
Short name T243
Test name
Test status
Simulation time 493418568232 ps
CPU time 1232.8 seconds
Started Apr 28 02:53:46 PM PDT 24
Finished Apr 28 03:14:19 PM PDT 24
Peak memory 202356 kb
Host smart-fcabe4d9-8a3a-4330-8761-58e468d785ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847912550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3847912550
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.386442472
Short name T34
Test name
Test status
Simulation time 328252658010 ps
CPU time 800.46 seconds
Started Apr 28 02:45:40 PM PDT 24
Finished Apr 28 02:59:02 PM PDT 24
Peak memory 202184 kb
Host smart-2cec8beb-50b3-4998-b542-a79e8976b790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386442472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.386442472
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1819794245
Short name T259
Test name
Test status
Simulation time 154004215520 ps
CPU time 379.73 seconds
Started Apr 28 02:50:57 PM PDT 24
Finished Apr 28 02:57:17 PM PDT 24
Peak memory 202292 kb
Host smart-bfe4e66d-ef8e-4ac6-85ec-d6747c458769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819794245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1819794245
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.4220266273
Short name T288
Test name
Test status
Simulation time 320649439613 ps
CPU time 198.74 seconds
Started Apr 28 02:46:06 PM PDT 24
Finished Apr 28 02:49:25 PM PDT 24
Peak memory 202312 kb
Host smart-4775a62c-e821-4df8-b4fd-fdd1f39d6556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220266273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.4220266273
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2534154678
Short name T338
Test name
Test status
Simulation time 629846446702 ps
CPU time 449.38 seconds
Started Apr 28 02:51:03 PM PDT 24
Finished Apr 28 02:58:33 PM PDT 24
Peak memory 202576 kb
Host smart-29c98b88-fc7b-4286-aa93-8c28f83d73c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534154678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2534154678
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3649286842
Short name T219
Test name
Test status
Simulation time 501984189326 ps
CPU time 297.63 seconds
Started Apr 28 02:52:07 PM PDT 24
Finished Apr 28 02:57:06 PM PDT 24
Peak memory 202376 kb
Host smart-60de33ac-34bd-4b0c-9bcf-3e3f7c4b9a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649286842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3649286842
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3333278217
Short name T266
Test name
Test status
Simulation time 194756572741 ps
CPU time 61.18 seconds
Started Apr 28 02:52:47 PM PDT 24
Finished Apr 28 02:53:49 PM PDT 24
Peak memory 202268 kb
Host smart-cb7fa4fc-ad0d-4080-9f8d-497b50c4eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333278217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3333278217
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.4211960277
Short name T275
Test name
Test status
Simulation time 190481479559 ps
CPU time 404.2 seconds
Started Apr 28 02:46:03 PM PDT 24
Finished Apr 28 02:52:48 PM PDT 24
Peak memory 202336 kb
Host smart-c75bc6e0-a9e7-4dcf-8c74-a6cc90c1baed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211960277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.4211960277
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3039888017
Short name T343
Test name
Test status
Simulation time 186169013415 ps
CPU time 112.53 seconds
Started Apr 28 02:49:04 PM PDT 24
Finished Apr 28 02:50:57 PM PDT 24
Peak memory 202308 kb
Host smart-c3f6ec86-771c-4902-be1a-f28e717238d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039888017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3039888017
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.3435817531
Short name T282
Test name
Test status
Simulation time 335202294855 ps
CPU time 313.3 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:51:06 PM PDT 24
Peak memory 202292 kb
Host smart-e2cb6f73-955d-4ca3-81c0-fe908f46c1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435817531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.3435817531
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2515713892
Short name T260
Test name
Test status
Simulation time 352272379663 ps
CPU time 335.56 seconds
Started Apr 28 02:52:28 PM PDT 24
Finished Apr 28 02:58:04 PM PDT 24
Peak memory 202360 kb
Host smart-9eedac8a-503e-4141-b623-4017a1646ab8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515713892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2515713892
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2455262179
Short name T250
Test name
Test status
Simulation time 205612564165 ps
CPU time 527.78 seconds
Started Apr 28 02:53:41 PM PDT 24
Finished Apr 28 03:02:29 PM PDT 24
Peak memory 202212 kb
Host smart-df1e1433-0b7d-4335-8a37-3834e4198d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455262179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2455262179
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3323869396
Short name T75
Test name
Test status
Simulation time 4228161738 ps
CPU time 6.88 seconds
Started Apr 28 01:19:48 PM PDT 24
Finished Apr 28 01:19:55 PM PDT 24
Peak memory 201492 kb
Host smart-0b3eb71c-4a1b-4b74-98d5-df4de3835edd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323869396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3323869396
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.762253544
Short name T202
Test name
Test status
Simulation time 81075432433 ps
CPU time 408.52 seconds
Started Apr 28 02:46:43 PM PDT 24
Finished Apr 28 02:53:32 PM PDT 24
Peak memory 202704 kb
Host smart-aefc17bc-cdf2-4d52-9e04-07e5e2bd045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762253544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.762253544
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2530667660
Short name T293
Test name
Test status
Simulation time 331392028761 ps
CPU time 508.91 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:54:02 PM PDT 24
Peak memory 202184 kb
Host smart-40ea8ab5-c9ee-485a-a9eb-192922a03812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530667660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2530667660
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.1672199519
Short name T104
Test name
Test status
Simulation time 492061402936 ps
CPU time 202.83 seconds
Started Apr 28 02:48:52 PM PDT 24
Finished Apr 28 02:52:16 PM PDT 24
Peak memory 202360 kb
Host smart-5a2c7807-8ce9-46b7-8129-fddb972b3eb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672199519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.1672199519
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1989040255
Short name T319
Test name
Test status
Simulation time 370496792575 ps
CPU time 248.42 seconds
Started Apr 28 02:49:04 PM PDT 24
Finished Apr 28 02:53:13 PM PDT 24
Peak memory 202376 kb
Host smart-ecd60a21-860a-495d-ab62-d43232129383
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989040255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1989040255
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4225657679
Short name T98
Test name
Test status
Simulation time 341859861983 ps
CPU time 390.75 seconds
Started Apr 28 02:51:03 PM PDT 24
Finished Apr 28 02:57:34 PM PDT 24
Peak memory 219068 kb
Host smart-05c2f6fc-0e35-4462-96f3-d38a61954394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225657679 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4225657679
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3508821417
Short name T675
Test name
Test status
Simulation time 70407226305 ps
CPU time 277.56 seconds
Started Apr 28 02:52:04 PM PDT 24
Finished Apr 28 02:56:43 PM PDT 24
Peak memory 202632 kb
Host smart-ba70a2b7-fe62-4338-a82d-696be8fb2a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508821417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3508821417
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.2972841175
Short name T306
Test name
Test status
Simulation time 484469377146 ps
CPU time 443.72 seconds
Started Apr 28 02:52:15 PM PDT 24
Finished Apr 28 02:59:39 PM PDT 24
Peak memory 202304 kb
Host smart-803107ac-7cac-4884-a50e-e276deae8894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972841175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.2972841175
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.2680545608
Short name T265
Test name
Test status
Simulation time 178782533040 ps
CPU time 374.89 seconds
Started Apr 28 02:53:53 PM PDT 24
Finished Apr 28 03:00:08 PM PDT 24
Peak memory 202384 kb
Host smart-a960cf89-0232-417e-aa2e-97ff0ea52339
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680545608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.2680545608
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2799997347
Short name T200
Test name
Test status
Simulation time 124350329752 ps
CPU time 419.56 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:53:02 PM PDT 24
Peak memory 202644 kb
Host smart-030fce9b-f285-47d8-844e-4730808599ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799997347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2799997347
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3766216057
Short name T235
Test name
Test status
Simulation time 354554836900 ps
CPU time 802.68 seconds
Started Apr 28 02:47:07 PM PDT 24
Finished Apr 28 03:00:30 PM PDT 24
Peak memory 202284 kb
Host smart-b98c4807-c226-481a-9df9-3413d418b541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766216057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3766216057
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1938980376
Short name T281
Test name
Test status
Simulation time 495646281103 ps
CPU time 1158.15 seconds
Started Apr 28 02:46:56 PM PDT 24
Finished Apr 28 03:06:15 PM PDT 24
Peak memory 202404 kb
Host smart-6e2f68b4-bf96-4de1-b14f-12fb18a2bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938980376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1938980376
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1844693259
Short name T313
Test name
Test status
Simulation time 515042512975 ps
CPU time 325.2 seconds
Started Apr 28 02:48:33 PM PDT 24
Finished Apr 28 02:53:58 PM PDT 24
Peak memory 202332 kb
Host smart-1fcd5abe-60b9-4d23-b42e-4aabc9f714e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844693259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1844693259
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2916176082
Short name T299
Test name
Test status
Simulation time 343328578594 ps
CPU time 836.85 seconds
Started Apr 28 02:48:34 PM PDT 24
Finished Apr 28 03:02:31 PM PDT 24
Peak memory 202376 kb
Host smart-57912723-720d-41c6-8902-f02e55373ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916176082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2916176082
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.4091486153
Short name T316
Test name
Test status
Simulation time 338504759876 ps
CPU time 808.62 seconds
Started Apr 28 02:49:01 PM PDT 24
Finished Apr 28 03:02:30 PM PDT 24
Peak memory 202380 kb
Host smart-5761260e-f2bf-4a78-ab12-95944a3150f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091486153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.4091486153
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2848663070
Short name T22
Test name
Test status
Simulation time 441039904771 ps
CPU time 422.35 seconds
Started Apr 28 02:49:46 PM PDT 24
Finished Apr 28 02:56:49 PM PDT 24
Peak memory 211204 kb
Host smart-ea68e40d-eba2-464f-a6d9-6df290a5d24f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848663070 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2848663070
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1492445109
Short name T258
Test name
Test status
Simulation time 495871602892 ps
CPU time 1115.19 seconds
Started Apr 28 02:50:08 PM PDT 24
Finished Apr 28 03:08:44 PM PDT 24
Peak memory 202304 kb
Host smart-a41d200b-0fdc-404e-9641-0db291c13079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492445109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1492445109
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.217372739
Short name T147
Test name
Test status
Simulation time 515708299554 ps
CPU time 292.08 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:50:49 PM PDT 24
Peak memory 202388 kb
Host smart-24e434ca-eaab-442e-b5a9-b9e5d8b5d5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217372739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.217372739
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1523936962
Short name T213
Test name
Test status
Simulation time 325332522839 ps
CPU time 369.81 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:52:09 PM PDT 24
Peak memory 202292 kb
Host smart-7b68ff80-fa7e-48b6-a4fd-4d99d10c37f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523936962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1523936962
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.567156379
Short name T358
Test name
Test status
Simulation time 102846636347 ps
CPU time 353.71 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:51:51 PM PDT 24
Peak memory 202660 kb
Host smart-10b04339-53da-48e4-bd73-f082856be978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567156379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.567156379
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3984835328
Short name T336
Test name
Test status
Simulation time 173168674578 ps
CPU time 323.85 seconds
Started Apr 28 02:46:10 PM PDT 24
Finished Apr 28 02:51:34 PM PDT 24
Peak memory 202340 kb
Host smart-a2c62ff1-bf89-43d4-b53e-37115c1dc32d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984835328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3984835328
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2648861198
Short name T307
Test name
Test status
Simulation time 491833565447 ps
CPU time 543.16 seconds
Started Apr 28 02:47:05 PM PDT 24
Finished Apr 28 02:56:08 PM PDT 24
Peak memory 202308 kb
Host smart-e4b16d58-4693-4486-82bf-728a02a573a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648861198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2648861198
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2961064378
Short name T198
Test name
Test status
Simulation time 113284504336 ps
CPU time 611.37 seconds
Started Apr 28 02:47:50 PM PDT 24
Finished Apr 28 02:58:02 PM PDT 24
Peak memory 202660 kb
Host smart-181fd503-5557-49b8-93a9-b1e43f9d9f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961064378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2961064378
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2505224453
Short name T605
Test name
Test status
Simulation time 164003789055 ps
CPU time 195.34 seconds
Started Apr 28 02:47:53 PM PDT 24
Finished Apr 28 02:51:08 PM PDT 24
Peak memory 202388 kb
Host smart-ddf654f8-0ea7-4844-9a68-482d5b456c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505224453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2505224453
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3289117662
Short name T328
Test name
Test status
Simulation time 335660280436 ps
CPU time 465.47 seconds
Started Apr 28 02:50:29 PM PDT 24
Finished Apr 28 02:58:15 PM PDT 24
Peak memory 202312 kb
Host smart-70c1de6b-7b7a-4820-b997-4fe054a48735
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289117662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3289117662
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2587065581
Short name T270
Test name
Test status
Simulation time 493395346498 ps
CPU time 626.84 seconds
Started Apr 28 02:50:27 PM PDT 24
Finished Apr 28 03:00:54 PM PDT 24
Peak memory 202304 kb
Host smart-0df93657-2ab3-4e51-9f4c-89bcd8f43b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587065581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2587065581
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.277719963
Short name T239
Test name
Test status
Simulation time 482096405816 ps
CPU time 1135.52 seconds
Started Apr 28 02:50:19 PM PDT 24
Finished Apr 28 03:09:15 PM PDT 24
Peak memory 202380 kb
Host smart-32dfc08b-ed6c-44fb-9e78-c4368d11f32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277719963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.277719963
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.649186381
Short name T335
Test name
Test status
Simulation time 332928949115 ps
CPU time 709.99 seconds
Started Apr 28 02:51:49 PM PDT 24
Finished Apr 28 03:03:39 PM PDT 24
Peak memory 202252 kb
Host smart-2ad4fb5a-2d21-4e9c-a76a-e4eeecaf7566
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649186381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.649186381
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2375277722
Short name T364
Test name
Test status
Simulation time 851283061856 ps
CPU time 903.54 seconds
Started Apr 28 02:52:04 PM PDT 24
Finished Apr 28 03:07:08 PM PDT 24
Peak memory 210944 kb
Host smart-e72d59ea-86f4-4679-8783-7fd44935829a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375277722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2375277722
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.4146928016
Short name T286
Test name
Test status
Simulation time 168109312747 ps
CPU time 393.33 seconds
Started Apr 28 02:52:49 PM PDT 24
Finished Apr 28 02:59:22 PM PDT 24
Peak memory 202276 kb
Host smart-efa16d05-7225-480c-beeb-6b63a9e71368
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146928016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.4146928016
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.315220762
Short name T111
Test name
Test status
Simulation time 40769914765 ps
CPU time 24.28 seconds
Started Apr 28 01:19:28 PM PDT 24
Finished Apr 28 01:19:55 PM PDT 24
Peak memory 201480 kb
Host smart-73bc1f7f-c613-4722-84a0-c71c5c76ecda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315220762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.315220762
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.451366914
Short name T858
Test name
Test status
Simulation time 1136141559 ps
CPU time 1.18 seconds
Started Apr 28 01:19:34 PM PDT 24
Finished Apr 28 01:19:36 PM PDT 24
Peak memory 201236 kb
Host smart-a6c384e7-2b15-40cd-9dc1-d19141456949
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451366914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.451366914
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1314193915
Short name T97
Test name
Test status
Simulation time 442188913 ps
CPU time 1.06 seconds
Started Apr 28 01:19:40 PM PDT 24
Finished Apr 28 01:19:42 PM PDT 24
Peak memory 201104 kb
Host smart-a05d2666-a0e1-4d26-a2f9-d6492ec5c2f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314193915 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1314193915
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.3334124895
Short name T913
Test name
Test status
Simulation time 428378521 ps
CPU time 1.13 seconds
Started Apr 28 01:19:29 PM PDT 24
Finished Apr 28 01:19:33 PM PDT 24
Peak memory 201132 kb
Host smart-41411d2a-0302-46f3-a1b0-6bc453097ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334124895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.3334124895
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2050897663
Short name T49
Test name
Test status
Simulation time 3807225418 ps
CPU time 7.27 seconds
Started Apr 28 01:19:29 PM PDT 24
Finished Apr 28 01:19:39 PM PDT 24
Peak memory 201428 kb
Host smart-a9bf4d60-2d57-4f6b-983f-442da06e6f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050897663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2050897663
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3436461824
Short name T863
Test name
Test status
Simulation time 535747243 ps
CPU time 3.63 seconds
Started Apr 28 01:19:31 PM PDT 24
Finished Apr 28 01:19:37 PM PDT 24
Peak memory 217816 kb
Host smart-5824f630-c1ee-4b60-aed2-346709b9d2de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436461824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3436461824
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1752135789
Short name T900
Test name
Test status
Simulation time 4569771173 ps
CPU time 12.92 seconds
Started Apr 28 01:19:40 PM PDT 24
Finished Apr 28 01:19:53 PM PDT 24
Peak memory 201248 kb
Host smart-8ecdb674-8b96-4cf8-8e21-00d93703e5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752135789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1752135789
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3666264892
Short name T117
Test name
Test status
Simulation time 1148913862 ps
CPU time 2.9 seconds
Started Apr 28 01:19:40 PM PDT 24
Finished Apr 28 01:19:43 PM PDT 24
Peak memory 201388 kb
Host smart-8f18ccc3-778e-403a-8d77-2924e2c5aeab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666264892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3666264892
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2878859278
Short name T915
Test name
Test status
Simulation time 27347797525 ps
CPU time 24.21 seconds
Started Apr 28 01:19:40 PM PDT 24
Finished Apr 28 01:20:04 PM PDT 24
Peak memory 201412 kb
Host smart-37c8af89-35c0-4cf6-a463-0562a2eda005
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878859278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2878859278
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.778760256
Short name T874
Test name
Test status
Simulation time 819755900 ps
CPU time 2.6 seconds
Started Apr 28 01:19:31 PM PDT 24
Finished Apr 28 01:19:36 PM PDT 24
Peak memory 201220 kb
Host smart-f9d15701-4074-4216-851e-9ae82bfd63f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778760256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.778760256
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3312882733
Short name T876
Test name
Test status
Simulation time 650705095 ps
CPU time 1.38 seconds
Started Apr 28 01:19:35 PM PDT 24
Finished Apr 28 01:19:37 PM PDT 24
Peak memory 209704 kb
Host smart-752d91aa-c060-4d7a-bdd7-b0dea56b52ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312882733 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3312882733
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2731107100
Short name T112
Test name
Test status
Simulation time 571077925 ps
CPU time 2.13 seconds
Started Apr 28 01:19:29 PM PDT 24
Finished Apr 28 01:19:34 PM PDT 24
Peak memory 201172 kb
Host smart-71d94eed-7e1d-4da5-ab97-290f149e8fbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731107100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2731107100
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.940361742
Short name T812
Test name
Test status
Simulation time 395265959 ps
CPU time 1.1 seconds
Started Apr 28 01:19:30 PM PDT 24
Finished Apr 28 01:19:34 PM PDT 24
Peak memory 201224 kb
Host smart-fb3ddf04-55fa-48a7-82f4-e50c8e302725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940361742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.940361742
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.814454376
Short name T896
Test name
Test status
Simulation time 2801670156 ps
CPU time 2.52 seconds
Started Apr 28 01:19:28 PM PDT 24
Finished Apr 28 01:19:34 PM PDT 24
Peak memory 201416 kb
Host smart-cf7530ae-76e3-4530-b846-63a17d37066e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814454376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.814454376
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1255651850
Short name T862
Test name
Test status
Simulation time 591310673 ps
CPU time 3 seconds
Started Apr 28 01:19:28 PM PDT 24
Finished Apr 28 01:19:34 PM PDT 24
Peak memory 201440 kb
Host smart-3c712f08-25e1-40ac-9879-a7dc87e50465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255651850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1255651850
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3984018897
Short name T864
Test name
Test status
Simulation time 8263874534 ps
CPU time 19.54 seconds
Started Apr 28 01:19:40 PM PDT 24
Finished Apr 28 01:20:00 PM PDT 24
Peak memory 201440 kb
Host smart-318d7577-b59e-45a6-9ccd-22074ee80370
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984018897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3984018897
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4187462273
Short name T64
Test name
Test status
Simulation time 630244095 ps
CPU time 1.31 seconds
Started Apr 28 01:19:56 PM PDT 24
Finished Apr 28 01:19:58 PM PDT 24
Peak memory 201268 kb
Host smart-c2eaca43-1dc6-4680-a264-ecd42685bf4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187462273 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4187462273
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3697097361
Short name T885
Test name
Test status
Simulation time 430737471 ps
CPU time 1.33 seconds
Started Apr 28 01:19:56 PM PDT 24
Finished Apr 28 01:19:58 PM PDT 24
Peak memory 201228 kb
Host smart-73356f04-6002-4eec-aada-7afe7da12198
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697097361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3697097361
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2758815573
Short name T899
Test name
Test status
Simulation time 281552749 ps
CPU time 1.32 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:19:57 PM PDT 24
Peak memory 201120 kb
Host smart-8f51f8de-a284-4707-9b1f-074862e64c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758815573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2758815573
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1840531893
Short name T880
Test name
Test status
Simulation time 4733506049 ps
CPU time 3.68 seconds
Started Apr 28 01:19:59 PM PDT 24
Finished Apr 28 01:20:03 PM PDT 24
Peak memory 201468 kb
Host smart-432beef9-57aa-4f31-a2c3-da477ae19e6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840531893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1840531893
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.510995725
Short name T845
Test name
Test status
Simulation time 522891525 ps
CPU time 2.39 seconds
Started Apr 28 01:19:58 PM PDT 24
Finished Apr 28 01:20:01 PM PDT 24
Peak memory 217128 kb
Host smart-e3f975b6-a3ca-4494-8374-f1887782fb50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510995725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.510995725
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.903763901
Short name T901
Test name
Test status
Simulation time 8279150768 ps
CPU time 11.92 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201520 kb
Host smart-afedc2e1-2f98-4eb7-afc4-2a39b6d005b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903763901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.903763901
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3562048409
Short name T837
Test name
Test status
Simulation time 449062579 ps
CPU time 1.45 seconds
Started Apr 28 01:19:59 PM PDT 24
Finished Apr 28 01:20:01 PM PDT 24
Peak memory 201276 kb
Host smart-046fcd09-5b16-43b3-a843-7bf9bb7fb3c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562048409 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3562048409
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2270919257
Short name T852
Test name
Test status
Simulation time 329230865 ps
CPU time 1.05 seconds
Started Apr 28 01:20:00 PM PDT 24
Finished Apr 28 01:20:02 PM PDT 24
Peak memory 201236 kb
Host smart-74ff10b5-726f-4daf-8f0c-00a599cdcf45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270919257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2270919257
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3318983237
Short name T917
Test name
Test status
Simulation time 435093584 ps
CPU time 1.66 seconds
Started Apr 28 01:20:01 PM PDT 24
Finished Apr 28 01:20:03 PM PDT 24
Peak memory 201236 kb
Host smart-965de29e-e960-4bbb-971a-f693f4c987e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318983237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3318983237
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.979594671
Short name T827
Test name
Test status
Simulation time 2473513282 ps
CPU time 2.63 seconds
Started Apr 28 01:19:59 PM PDT 24
Finished Apr 28 01:20:02 PM PDT 24
Peak memory 201264 kb
Host smart-9a436175-eb64-4caf-a8c9-865c820e0842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979594671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.979594671
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3474717736
Short name T71
Test name
Test status
Simulation time 689553680 ps
CPU time 1.96 seconds
Started Apr 28 01:20:01 PM PDT 24
Finished Apr 28 01:20:04 PM PDT 24
Peak memory 201448 kb
Host smart-9ae7c717-f891-4039-9f6a-659d4753f71b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474717736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3474717736
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.1101312550
Short name T888
Test name
Test status
Simulation time 4060792414 ps
CPU time 3.69 seconds
Started Apr 28 01:20:04 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201404 kb
Host smart-69bbe69b-a231-4c72-8813-906911b6f735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101312550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.1101312550
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3131833349
Short name T889
Test name
Test status
Simulation time 467499889 ps
CPU time 1.28 seconds
Started Apr 28 01:20:01 PM PDT 24
Finished Apr 28 01:20:03 PM PDT 24
Peak memory 201248 kb
Host smart-71ead082-b13b-409d-bfa0-0d5510ffa0fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131833349 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3131833349
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.559257116
Short name T122
Test name
Test status
Simulation time 573190363 ps
CPU time 1.26 seconds
Started Apr 28 01:20:01 PM PDT 24
Finished Apr 28 01:20:03 PM PDT 24
Peak memory 201232 kb
Host smart-8a8eca36-2d9c-4c25-9bfb-e8d9ee876c51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559257116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.559257116
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1034527280
Short name T866
Test name
Test status
Simulation time 432265247 ps
CPU time 1.55 seconds
Started Apr 28 01:20:02 PM PDT 24
Finished Apr 28 01:20:04 PM PDT 24
Peak memory 201108 kb
Host smart-130a74ff-a139-4d1a-8157-a22cf238fadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034527280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1034527280
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.661556280
Short name T127
Test name
Test status
Simulation time 2053485112 ps
CPU time 1.92 seconds
Started Apr 28 01:20:04 PM PDT 24
Finished Apr 28 01:20:06 PM PDT 24
Peak memory 201104 kb
Host smart-fa340ad8-2185-48fa-ac05-fddb3d9b630b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661556280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.661556280
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2976622064
Short name T825
Test name
Test status
Simulation time 654935083 ps
CPU time 1.46 seconds
Started Apr 28 01:19:59 PM PDT 24
Finished Apr 28 01:20:01 PM PDT 24
Peak memory 201548 kb
Host smart-436c3a65-34b7-445b-abcd-149dc93f7c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976622064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2976622064
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.381602741
Short name T352
Test name
Test status
Simulation time 4329914192 ps
CPU time 6.15 seconds
Started Apr 28 01:20:00 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201508 kb
Host smart-d827352b-5301-4173-a612-abafb9223c99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381602741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.381602741
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1669903026
Short name T823
Test name
Test status
Simulation time 538456223 ps
CPU time 1.24 seconds
Started Apr 28 01:20:04 PM PDT 24
Finished Apr 28 01:20:06 PM PDT 24
Peak memory 201168 kb
Host smart-ecc8c176-fce2-4c30-9aab-993f58e207b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669903026 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1669903026
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2235712463
Short name T918
Test name
Test status
Simulation time 647010178 ps
CPU time 0.92 seconds
Started Apr 28 01:20:03 PM PDT 24
Finished Apr 28 01:20:04 PM PDT 24
Peak memory 201112 kb
Host smart-4a3a9e1e-6d6e-4df7-bcf9-9c5c0247bf5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235712463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2235712463
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3479360676
Short name T872
Test name
Test status
Simulation time 578889138 ps
CPU time 0.72 seconds
Started Apr 28 01:20:00 PM PDT 24
Finished Apr 28 01:20:01 PM PDT 24
Peak memory 201164 kb
Host smart-8cf0cd72-4a0b-4ef7-a8e0-e4327d4e3b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479360676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3479360676
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.159047521
Short name T856
Test name
Test status
Simulation time 2258257653 ps
CPU time 2.22 seconds
Started Apr 28 01:19:59 PM PDT 24
Finished Apr 28 01:20:02 PM PDT 24
Peak memory 201160 kb
Host smart-b8d093c5-9312-483e-b731-9dce15d62770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159047521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.159047521
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2203242899
Short name T63
Test name
Test status
Simulation time 618462122 ps
CPU time 2.02 seconds
Started Apr 28 01:19:59 PM PDT 24
Finished Apr 28 01:20:02 PM PDT 24
Peak memory 201432 kb
Host smart-04db9435-fb1f-4e41-9ff8-ce53afc4a25e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203242899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2203242899
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2793106512
Short name T70
Test name
Test status
Simulation time 8439461243 ps
CPU time 23 seconds
Started Apr 28 01:20:02 PM PDT 24
Finished Apr 28 01:20:26 PM PDT 24
Peak memory 201352 kb
Host smart-a9d6bf40-de9c-452a-8953-947663da6fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793106512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2793106512
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.1014805438
Short name T60
Test name
Test status
Simulation time 1051479998 ps
CPU time 1.08 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201272 kb
Host smart-2649f825-75fd-4a66-9672-c35921dc0cf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014805438 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.1014805438
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.4214408283
Short name T836
Test name
Test status
Simulation time 418702818 ps
CPU time 1.07 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201212 kb
Host smart-636a5ed2-8755-4f3e-8363-1958eab050c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214408283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.4214408283
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2953175105
Short name T48
Test name
Test status
Simulation time 4372093478 ps
CPU time 5.94 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:16 PM PDT 24
Peak memory 201396 kb
Host smart-c2433038-8ad8-4d6a-ba9b-c9c8b0527ff7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953175105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2953175105
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.616976698
Short name T835
Test name
Test status
Simulation time 586561588 ps
CPU time 2.39 seconds
Started Apr 28 01:20:01 PM PDT 24
Finished Apr 28 01:20:03 PM PDT 24
Peak memory 210600 kb
Host smart-35d03909-262e-478d-985b-76defee934da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616976698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.616976698
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.4006562705
Short name T73
Test name
Test status
Simulation time 8736580227 ps
CPU time 22.2 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:28 PM PDT 24
Peak memory 201412 kb
Host smart-79b43748-1280-4578-98d0-176acacac1a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006562705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.4006562705
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3045863860
Short name T830
Test name
Test status
Simulation time 592095449 ps
CPU time 1.28 seconds
Started Apr 28 01:20:04 PM PDT 24
Finished Apr 28 01:20:06 PM PDT 24
Peak memory 201196 kb
Host smart-e036a0aa-31ac-4604-b8e8-249e5af9c46c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045863860 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3045863860
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2802014751
Short name T887
Test name
Test status
Simulation time 498472454 ps
CPU time 1.05 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201120 kb
Host smart-2ab0a0ac-108e-44c1-ad06-a52ce79e4555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802014751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2802014751
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1337050880
Short name T839
Test name
Test status
Simulation time 432251508 ps
CPU time 1.63 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201168 kb
Host smart-56886110-f8d3-4849-85b3-2c08f582501a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337050880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1337050880
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3546445973
Short name T894
Test name
Test status
Simulation time 4243625578 ps
CPU time 3.3 seconds
Started Apr 28 01:20:04 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201416 kb
Host smart-28652590-bb5f-4f23-bb92-b43b599b430a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546445973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3546445973
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2561752580
Short name T902
Test name
Test status
Simulation time 4586346216 ps
CPU time 12.15 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:23 PM PDT 24
Peak memory 201480 kb
Host smart-4ef7ba72-e685-42d8-bd53-46a30f3a3be7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561752580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2561752580
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2722965725
Short name T904
Test name
Test status
Simulation time 601782318 ps
CPU time 1.16 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201308 kb
Host smart-7e3485c0-1379-4790-af8f-cd505905e5eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722965725 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2722965725
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3087729622
Short name T126
Test name
Test status
Simulation time 465923209 ps
CPU time 0.96 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201228 kb
Host smart-a3fbadf3-2ee6-405a-8de5-d53ff8e3fa4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087729622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3087729622
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2997394687
Short name T909
Test name
Test status
Simulation time 368892064 ps
CPU time 1.44 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201200 kb
Host smart-d8cd0275-3cb7-4d25-846c-9a30a31754a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997394687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2997394687
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2657367934
Short name T857
Test name
Test status
Simulation time 2465695650 ps
CPU time 9.36 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:21 PM PDT 24
Peak memory 201296 kb
Host smart-ffe9522e-339e-4d95-bf3d-87e190bf473d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657367934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2657367934
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1414377126
Short name T65
Test name
Test status
Simulation time 522841792 ps
CPU time 2.02 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201388 kb
Host smart-659f6dce-6bc2-4b30-ad8a-77a1bd65f70c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414377126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1414377126
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.506723
Short name T903
Test name
Test status
Simulation time 8039331296 ps
CPU time 20.21 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:25 PM PDT 24
Peak memory 201412 kb
Host smart-0e23ab6b-7d17-4357-90ba-7338846ad982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_intg_
err.506723
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.422125074
Short name T886
Test name
Test status
Simulation time 507328406 ps
CPU time 1.71 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201284 kb
Host smart-4727d7cd-5d0a-41c8-a6b6-1d2e37d4e015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422125074 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.422125074
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2894159617
Short name T114
Test name
Test status
Simulation time 358087595 ps
CPU time 0.81 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:06 PM PDT 24
Peak memory 201128 kb
Host smart-90d5f052-cfe4-4e3d-8d48-613f3a0ca29e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894159617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2894159617
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3899408378
Short name T905
Test name
Test status
Simulation time 313975729 ps
CPU time 0.97 seconds
Started Apr 28 01:20:04 PM PDT 24
Finished Apr 28 01:20:05 PM PDT 24
Peak memory 201204 kb
Host smart-1709ac83-f3ee-4eea-87be-ce9488aa7522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899408378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3899408378
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.213718869
Short name T124
Test name
Test status
Simulation time 4820215695 ps
CPU time 4.7 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:16 PM PDT 24
Peak memory 201500 kb
Host smart-c32062d6-025e-4743-ae90-3d9b28b373c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213718869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.213718869
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.986862613
Short name T61
Test name
Test status
Simulation time 463592420 ps
CPU time 1.86 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201444 kb
Host smart-11f020c3-9166-4dea-a798-995cb7b4cfce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986862613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.986862613
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2344354332
Short name T832
Test name
Test status
Simulation time 7921425274 ps
CPU time 7.18 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:15 PM PDT 24
Peak memory 201436 kb
Host smart-dc42156d-b0cb-4c42-8d5b-000a9c4e4923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344354332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2344354332
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3782261780
Short name T829
Test name
Test status
Simulation time 459575727 ps
CPU time 1.07 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201200 kb
Host smart-f7ebdfd1-df89-4958-86f7-96371c0d45cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782261780 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3782261780
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2390326611
Short name T123
Test name
Test status
Simulation time 302155626 ps
CPU time 1.4 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201152 kb
Host smart-9203afa7-4b1c-4a0f-a14c-c1c5bf96e0d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390326611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2390326611
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4248560736
Short name T820
Test name
Test status
Simulation time 334411328 ps
CPU time 1.4 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201196 kb
Host smart-78309e25-a25c-433d-8c5e-5e2dbcd0dd20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248560736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4248560736
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1325649094
Short name T816
Test name
Test status
Simulation time 2400733917 ps
CPU time 4.81 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201292 kb
Host smart-0b2a6b75-903e-4bf0-89c9-b6a01a238406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325649094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1325649094
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.2688531365
Short name T833
Test name
Test status
Simulation time 3364176378 ps
CPU time 3.15 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 217844 kb
Host smart-1b722639-1972-40ef-ad8c-0dc87639f769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688531365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.2688531365
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1214525411
Short name T865
Test name
Test status
Simulation time 8388733010 ps
CPU time 13.16 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:20 PM PDT 24
Peak memory 201468 kb
Host smart-29d6676e-55ae-47fe-bd57-6d78bf686bf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214525411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1214525411
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3781859435
Short name T875
Test name
Test status
Simulation time 593876182 ps
CPU time 2.2 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:14 PM PDT 24
Peak memory 201244 kb
Host smart-dc957c7a-6e83-4e1c-822f-27e8d8fa24ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781859435 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3781859435
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3550256301
Short name T109
Test name
Test status
Simulation time 535799348 ps
CPU time 1.05 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201232 kb
Host smart-a606d9e1-5f70-4ac6-87e5-56db0cdef7a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550256301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3550256301
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.845738399
Short name T841
Test name
Test status
Simulation time 288558848 ps
CPU time 1.22 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201192 kb
Host smart-7cd48bdc-9758-4b2e-a9d6-f96ff4319ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845738399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.845738399
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.866881881
Short name T840
Test name
Test status
Simulation time 2910032785 ps
CPU time 2.59 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:14 PM PDT 24
Peak memory 201240 kb
Host smart-7b0fa199-2308-4230-b0c9-9443556eab4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866881881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.866881881
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3213010915
Short name T74
Test name
Test status
Simulation time 5023821530 ps
CPU time 3.09 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:11 PM PDT 24
Peak memory 201508 kb
Host smart-c019792f-2875-456c-9752-4ef26385b1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213010915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3213010915
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1507828886
Short name T118
Test name
Test status
Simulation time 1279319114 ps
CPU time 2.94 seconds
Started Apr 28 01:19:38 PM PDT 24
Finished Apr 28 01:19:42 PM PDT 24
Peak memory 201404 kb
Host smart-0ca60c88-d76c-4870-a500-ed2cbf64bf96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507828886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1507828886
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.966904502
Short name T113
Test name
Test status
Simulation time 25989269921 ps
CPU time 57.83 seconds
Started Apr 28 01:19:32 PM PDT 24
Finished Apr 28 01:20:31 PM PDT 24
Peak memory 201476 kb
Host smart-622ae12a-a528-460c-aff1-93741bab490b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966904502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.966904502
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1085708536
Short name T850
Test name
Test status
Simulation time 763392182 ps
CPU time 2.34 seconds
Started Apr 28 01:19:35 PM PDT 24
Finished Apr 28 01:19:38 PM PDT 24
Peak memory 201208 kb
Host smart-a9db2fee-bb7e-4477-84ac-f7c9d112ebf2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085708536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1085708536
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2745823334
Short name T849
Test name
Test status
Simulation time 584592724 ps
CPU time 1.32 seconds
Started Apr 28 01:19:37 PM PDT 24
Finished Apr 28 01:19:39 PM PDT 24
Peak memory 217400 kb
Host smart-6c397551-5ec9-46e7-8c27-bda816128512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745823334 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2745823334
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3376730107
Short name T119
Test name
Test status
Simulation time 441911753 ps
CPU time 1.98 seconds
Started Apr 28 01:19:34 PM PDT 24
Finished Apr 28 01:19:37 PM PDT 24
Peak memory 201256 kb
Host smart-30c585eb-ae39-413a-8b56-8d66f90e4a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376730107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3376730107
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3718778257
Short name T897
Test name
Test status
Simulation time 318683996 ps
CPU time 1.32 seconds
Started Apr 28 01:19:32 PM PDT 24
Finished Apr 28 01:19:35 PM PDT 24
Peak memory 201112 kb
Host smart-a1eb62dc-c004-41a8-94f1-2a3648b86b19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718778257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3718778257
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3889359050
Short name T826
Test name
Test status
Simulation time 2566636968 ps
CPU time 3.96 seconds
Started Apr 28 01:19:36 PM PDT 24
Finished Apr 28 01:19:41 PM PDT 24
Peak memory 201180 kb
Host smart-047ab3f9-b8aa-449b-9328-a6a70c1f3a93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889359050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3889359050
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2746333623
Short name T868
Test name
Test status
Simulation time 697426461 ps
CPU time 2.07 seconds
Started Apr 28 01:19:34 PM PDT 24
Finished Apr 28 01:19:36 PM PDT 24
Peak memory 217824 kb
Host smart-9f0b5840-d6cd-460e-90cd-53225b69946a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746333623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2746333623
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2806919285
Short name T54
Test name
Test status
Simulation time 8516923608 ps
CPU time 5.32 seconds
Started Apr 28 01:19:33 PM PDT 24
Finished Apr 28 01:19:39 PM PDT 24
Peak memory 201480 kb
Host smart-5bfa9f45-7ad5-4695-9290-38b983cb762d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806919285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2806919285
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.252407281
Short name T871
Test name
Test status
Simulation time 509541906 ps
CPU time 1.76 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201144 kb
Host smart-f90e0563-f943-4649-924a-5dcf9dd4f207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252407281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.252407281
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1590011082
Short name T808
Test name
Test status
Simulation time 512988081 ps
CPU time 0.93 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201220 kb
Host smart-7df2681d-770e-432d-b41f-f8c688d47b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590011082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1590011082
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.472676985
Short name T890
Test name
Test status
Simulation time 392186423 ps
CPU time 1.38 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201224 kb
Host smart-b86f14a9-84eb-488f-b8f1-fc7af3f078e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472676985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.472676985
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2656366527
Short name T806
Test name
Test status
Simulation time 497678163 ps
CPU time 1.21 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201216 kb
Host smart-6c84ada4-bddc-4d00-bd8a-c701988d0468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656366527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2656366527
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2810586237
Short name T883
Test name
Test status
Simulation time 356913177 ps
CPU time 1.03 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201148 kb
Host smart-976287ef-6b81-40dd-b16e-7be1a751f5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810586237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2810586237
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1058055206
Short name T814
Test name
Test status
Simulation time 560086713 ps
CPU time 0.95 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201172 kb
Host smart-edfb3eeb-f6a9-4ee6-a504-9c0a2e0f92a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058055206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1058055206
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.277949162
Short name T884
Test name
Test status
Simulation time 344097468 ps
CPU time 1.35 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201180 kb
Host smart-fd3c8b44-776b-4c70-aee2-1bf39469294d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277949162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.277949162
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3156736292
Short name T910
Test name
Test status
Simulation time 355726496 ps
CPU time 1.48 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201196 kb
Host smart-3f44673c-0f3d-49d2-8707-43508b714eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156736292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3156736292
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1806619735
Short name T801
Test name
Test status
Simulation time 305566661 ps
CPU time 1.35 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:11 PM PDT 24
Peak memory 201148 kb
Host smart-bb95f21e-4daf-484a-9db5-4d4c118f15a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806619735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1806619735
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.823235877
Short name T912
Test name
Test status
Simulation time 486785838 ps
CPU time 1.72 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201104 kb
Host smart-e9d97e21-9161-4c50-82b8-4ecaff498561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823235877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.823235877
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3848887302
Short name T116
Test name
Test status
Simulation time 828426012 ps
CPU time 3.09 seconds
Started Apr 28 01:19:40 PM PDT 24
Finished Apr 28 01:19:44 PM PDT 24
Peak memory 201304 kb
Host smart-f73ba3a2-fca7-4ae3-9dbd-4d9912775e35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848887302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3848887302
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.1586231788
Short name T907
Test name
Test status
Simulation time 43523244501 ps
CPU time 99.7 seconds
Started Apr 28 01:19:38 PM PDT 24
Finished Apr 28 01:21:18 PM PDT 24
Peak memory 201472 kb
Host smart-49160c83-6b45-4c65-b1e3-482ff7dba049
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586231788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.1586231788
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3649711733
Short name T120
Test name
Test status
Simulation time 1177449354 ps
CPU time 2.13 seconds
Started Apr 28 01:19:36 PM PDT 24
Finished Apr 28 01:19:38 PM PDT 24
Peak memory 201156 kb
Host smart-98fde6e2-11ca-4e33-90c3-d5a2de2bebf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649711733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3649711733
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2425282889
Short name T867
Test name
Test status
Simulation time 616246741 ps
CPU time 1.17 seconds
Started Apr 28 01:19:39 PM PDT 24
Finished Apr 28 01:19:41 PM PDT 24
Peak memory 201248 kb
Host smart-998787b1-a9ad-48ed-97a6-3e4c08bce08c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425282889 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2425282889
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.979974793
Short name T879
Test name
Test status
Simulation time 470338361 ps
CPU time 1.26 seconds
Started Apr 28 01:19:38 PM PDT 24
Finished Apr 28 01:19:40 PM PDT 24
Peak memory 201148 kb
Host smart-1b54f49e-75fc-4a06-bb27-bca67403669d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979974793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.979974793
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2797189699
Short name T822
Test name
Test status
Simulation time 462629366 ps
CPU time 1.66 seconds
Started Apr 28 01:19:38 PM PDT 24
Finished Apr 28 01:19:40 PM PDT 24
Peak memory 201204 kb
Host smart-ab2e1beb-edfa-49ef-ab3d-f6baf25e6038
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797189699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2797189699
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3324157323
Short name T828
Test name
Test status
Simulation time 2212202088 ps
CPU time 3.3 seconds
Started Apr 28 01:19:41 PM PDT 24
Finished Apr 28 01:19:45 PM PDT 24
Peak memory 201196 kb
Host smart-ae1b0021-2164-4010-961c-3156ff8849e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324157323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3324157323
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2034802973
Short name T72
Test name
Test status
Simulation time 903494876 ps
CPU time 2.34 seconds
Started Apr 28 01:19:39 PM PDT 24
Finished Apr 28 01:19:42 PM PDT 24
Peak memory 201368 kb
Host smart-6ec0486e-b398-4107-8528-08e866dc3be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034802973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2034802973
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3808437071
Short name T846
Test name
Test status
Simulation time 303194521 ps
CPU time 1.33 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201232 kb
Host smart-b96557e8-6584-4e6d-8001-19f78122b60e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808437071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3808437071
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3790084508
Short name T854
Test name
Test status
Simulation time 528058307 ps
CPU time 0.93 seconds
Started Apr 28 01:20:06 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201164 kb
Host smart-31ff470b-df61-49b7-a3fb-81c633990d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790084508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3790084508
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1798348187
Short name T831
Test name
Test status
Simulation time 478887800 ps
CPU time 0.92 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:11 PM PDT 24
Peak memory 201144 kb
Host smart-089c61a2-4130-42c1-8aa4-55e02cddf7e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798348187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1798348187
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4127882101
Short name T818
Test name
Test status
Simulation time 456871449 ps
CPU time 1.62 seconds
Started Apr 28 01:20:07 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201220 kb
Host smart-6df0e957-bdd0-41b4-b07b-422e3a47dd2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127882101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4127882101
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2969012517
Short name T844
Test name
Test status
Simulation time 545260532 ps
CPU time 0.85 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201172 kb
Host smart-233f013c-489e-4dfe-b37c-e4163cbebf13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969012517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2969012517
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1264728512
Short name T815
Test name
Test status
Simulation time 309169982 ps
CPU time 0.81 seconds
Started Apr 28 01:20:05 PM PDT 24
Finished Apr 28 01:20:07 PM PDT 24
Peak memory 201168 kb
Host smart-1941f11f-2c86-4ccc-9439-fbd38146832c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264728512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1264728512
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.4028272606
Short name T855
Test name
Test status
Simulation time 367274717 ps
CPU time 1.45 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:13 PM PDT 24
Peak memory 201172 kb
Host smart-f12439b4-2894-449c-8e09-687a05e24bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028272606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.4028272606
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2072990985
Short name T821
Test name
Test status
Simulation time 377877780 ps
CPU time 0.84 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:11 PM PDT 24
Peak memory 201168 kb
Host smart-e5d89551-67a4-44a3-bc6a-cc8f5d4e5fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072990985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2072990985
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4136093819
Short name T819
Test name
Test status
Simulation time 407264202 ps
CPU time 0.73 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201228 kb
Host smart-cc8a8890-3876-400f-af86-cf2112f44ec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136093819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.4136093819
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2763144715
Short name T807
Test name
Test status
Simulation time 484316312 ps
CPU time 1.01 seconds
Started Apr 28 01:20:08 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201252 kb
Host smart-a1d40712-b7c5-48f1-a5bb-08d16b36ec8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763144715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2763144715
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2581602320
Short name T110
Test name
Test status
Simulation time 731794401 ps
CPU time 3.6 seconds
Started Apr 28 01:19:49 PM PDT 24
Finished Apr 28 01:19:53 PM PDT 24
Peak memory 201448 kb
Host smart-fc1d76bf-7519-49ec-a785-a2c378344e03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581602320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2581602320
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2845710749
Short name T809
Test name
Test status
Simulation time 52774210894 ps
CPU time 62.62 seconds
Started Apr 28 01:19:47 PM PDT 24
Finished Apr 28 01:20:50 PM PDT 24
Peak memory 201496 kb
Host smart-54482fa8-f648-4025-8498-cdb258e9bbbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845710749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2845710749
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1874944042
Short name T853
Test name
Test status
Simulation time 992644765 ps
CPU time 2.89 seconds
Started Apr 28 01:19:45 PM PDT 24
Finished Apr 28 01:19:48 PM PDT 24
Peak memory 201236 kb
Host smart-7f4afe02-e5f7-4a8c-aaf5-a6f836be9aec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874944042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1874944042
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1920386422
Short name T55
Test name
Test status
Simulation time 411568899 ps
CPU time 1.68 seconds
Started Apr 28 01:19:46 PM PDT 24
Finished Apr 28 01:19:48 PM PDT 24
Peak memory 201276 kb
Host smart-3d733b25-27a3-462a-bc09-79455951c0a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920386422 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1920386422
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3169866710
Short name T121
Test name
Test status
Simulation time 376509437 ps
CPU time 0.86 seconds
Started Apr 28 01:20:03 PM PDT 24
Finished Apr 28 01:20:04 PM PDT 24
Peak memory 201216 kb
Host smart-1e5de22b-f32f-4170-b4e2-3648d93e083f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169866710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3169866710
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1983138320
Short name T805
Test name
Test status
Simulation time 479948347 ps
CPU time 1.73 seconds
Started Apr 28 01:19:49 PM PDT 24
Finished Apr 28 01:19:52 PM PDT 24
Peak memory 201220 kb
Host smart-44e0d6cb-fb24-4893-9c65-0e82c3c825ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983138320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1983138320
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.222825000
Short name T859
Test name
Test status
Simulation time 4459983797 ps
CPU time 11.18 seconds
Started Apr 28 01:19:49 PM PDT 24
Finished Apr 28 01:20:00 PM PDT 24
Peak memory 201500 kb
Host smart-45572f99-e190-4833-ae5f-ac33a2a2518f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222825000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.222825000
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2425534106
Short name T916
Test name
Test status
Simulation time 394610728 ps
CPU time 1.9 seconds
Started Apr 28 01:19:46 PM PDT 24
Finished Apr 28 01:19:48 PM PDT 24
Peak memory 201428 kb
Host smart-9e4e3a21-e4f6-4afc-8dd1-336035a2b8f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425534106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2425534106
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.197016366
Short name T895
Test name
Test status
Simulation time 385961951 ps
CPU time 0.83 seconds
Started Apr 28 01:20:08 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201196 kb
Host smart-9d8c710d-800e-4f80-ad34-679f4e8a35ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197016366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.197016366
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1198785744
Short name T802
Test name
Test status
Simulation time 511532665 ps
CPU time 1.76 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:11 PM PDT 24
Peak memory 201216 kb
Host smart-17f5f90a-46c5-4924-beea-5908d58c44e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198785744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1198785744
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2768796123
Short name T869
Test name
Test status
Simulation time 491963896 ps
CPU time 0.77 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201200 kb
Host smart-2202f09b-372a-4f01-aa62-08895831e7aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768796123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2768796123
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2031787765
Short name T911
Test name
Test status
Simulation time 292369114 ps
CPU time 1.29 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201212 kb
Host smart-a0db5b21-756f-4a7e-aa51-34996b6ce2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031787765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2031787765
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2126150910
Short name T891
Test name
Test status
Simulation time 449652658 ps
CPU time 1.64 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201212 kb
Host smart-b42d99cf-9094-487c-bc40-3081fb27d947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126150910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2126150910
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3143665494
Short name T811
Test name
Test status
Simulation time 399435918 ps
CPU time 1.65 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:13 PM PDT 24
Peak memory 201220 kb
Host smart-43931f50-e604-4793-a1ca-1e4337ce737f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143665494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3143665494
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3097892699
Short name T892
Test name
Test status
Simulation time 396320764 ps
CPU time 1.43 seconds
Started Apr 28 01:20:08 PM PDT 24
Finished Apr 28 01:20:10 PM PDT 24
Peak memory 201144 kb
Host smart-5d360594-5bac-4f2e-ba00-7945142870c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097892699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3097892699
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2311051239
Short name T834
Test name
Test status
Simulation time 342766922 ps
CPU time 1.37 seconds
Started Apr 28 01:20:10 PM PDT 24
Finished Apr 28 01:20:13 PM PDT 24
Peak memory 201164 kb
Host smart-04ad08b2-0429-49c1-80cf-5ae0e74922d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311051239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2311051239
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2142339936
Short name T804
Test name
Test status
Simulation time 390413508 ps
CPU time 0.84 seconds
Started Apr 28 01:20:08 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201128 kb
Host smart-db4a4ae1-35fb-4394-befa-a7e1bc5f7e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142339936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2142339936
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2082329800
Short name T848
Test name
Test status
Simulation time 417197062 ps
CPU time 0.96 seconds
Started Apr 28 01:20:09 PM PDT 24
Finished Apr 28 01:20:12 PM PDT 24
Peak memory 201220 kb
Host smart-c05138ff-983f-46de-93d5-cfdfe17a056a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082329800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2082329800
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1433160674
Short name T838
Test name
Test status
Simulation time 438404063 ps
CPU time 1.92 seconds
Started Apr 28 01:19:52 PM PDT 24
Finished Apr 28 01:19:54 PM PDT 24
Peak memory 201272 kb
Host smart-e263771b-d48b-4dc1-8731-1722fe5ffef1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433160674 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1433160674
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4199092666
Short name T813
Test name
Test status
Simulation time 558109777 ps
CPU time 0.93 seconds
Started Apr 28 01:19:50 PM PDT 24
Finished Apr 28 01:19:52 PM PDT 24
Peak memory 201108 kb
Host smart-6db03adb-04e5-4cc6-b1c6-6aba591e3e13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199092666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4199092666
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2070496912
Short name T870
Test name
Test status
Simulation time 348345866 ps
CPU time 0.77 seconds
Started Apr 28 01:19:48 PM PDT 24
Finished Apr 28 01:19:49 PM PDT 24
Peak memory 201196 kb
Host smart-340d57ff-bd88-4be8-8564-182d518810a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070496912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2070496912
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3122414812
Short name T881
Test name
Test status
Simulation time 5220069292 ps
CPU time 10.75 seconds
Started Apr 28 01:19:51 PM PDT 24
Finished Apr 28 01:20:02 PM PDT 24
Peak memory 201472 kb
Host smart-25032630-4952-474c-88f3-b820ac2f6fcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122414812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3122414812
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.293357610
Short name T914
Test name
Test status
Simulation time 603947591 ps
CPU time 2.98 seconds
Started Apr 28 01:19:45 PM PDT 24
Finished Apr 28 01:19:48 PM PDT 24
Peak memory 217788 kb
Host smart-83f031df-110c-48b3-9271-d023406af5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293357610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.293357610
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.2165258708
Short name T52
Test name
Test status
Simulation time 8661359613 ps
CPU time 23.02 seconds
Started Apr 28 01:19:45 PM PDT 24
Finished Apr 28 01:20:08 PM PDT 24
Peak memory 201476 kb
Host smart-e249e182-e628-495d-9905-b77251ac295b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165258708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.2165258708
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.626159606
Short name T877
Test name
Test status
Simulation time 678693790 ps
CPU time 1.8 seconds
Started Apr 28 01:19:52 PM PDT 24
Finished Apr 28 01:19:55 PM PDT 24
Peak memory 209704 kb
Host smart-c21d9a12-47bb-46d8-a7a1-8c67ab024ea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626159606 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.626159606
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3315293963
Short name T842
Test name
Test status
Simulation time 590884469 ps
CPU time 0.97 seconds
Started Apr 28 01:19:50 PM PDT 24
Finished Apr 28 01:19:51 PM PDT 24
Peak memory 201240 kb
Host smart-42eeeab9-6657-4d15-bf79-00b4ea50580c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315293963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3315293963
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1510681297
Short name T810
Test name
Test status
Simulation time 315939928 ps
CPU time 0.76 seconds
Started Apr 28 01:19:53 PM PDT 24
Finished Apr 28 01:19:54 PM PDT 24
Peak memory 201096 kb
Host smart-84575e40-232a-4e71-8052-e787f3a63a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510681297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1510681297
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2076080012
Short name T129
Test name
Test status
Simulation time 2523012317 ps
CPU time 6.61 seconds
Started Apr 28 01:19:51 PM PDT 24
Finished Apr 28 01:19:58 PM PDT 24
Peak memory 201312 kb
Host smart-b19a31b5-63d0-49ce-80da-fc28a1fd599b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076080012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2076080012
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1418688663
Short name T860
Test name
Test status
Simulation time 448070013 ps
CPU time 2 seconds
Started Apr 28 01:19:50 PM PDT 24
Finished Apr 28 01:19:52 PM PDT 24
Peak memory 201420 kb
Host smart-47246fb2-771c-46f1-9cad-99528edb755a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418688663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1418688663
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.2176483967
Short name T898
Test name
Test status
Simulation time 4508577387 ps
CPU time 4.15 seconds
Started Apr 28 01:19:51 PM PDT 24
Finished Apr 28 01:19:56 PM PDT 24
Peak memory 201504 kb
Host smart-096fbe82-7a47-499f-967c-7bd6404effc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176483967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.2176483967
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.36344332
Short name T882
Test name
Test status
Simulation time 582035080 ps
CPU time 1.45 seconds
Started Apr 28 01:19:51 PM PDT 24
Finished Apr 28 01:19:53 PM PDT 24
Peak memory 201300 kb
Host smart-1031e2f0-0e94-4278-81eb-8f03d35ad6c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36344332 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.36344332
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2491248489
Short name T878
Test name
Test status
Simulation time 444290878 ps
CPU time 0.98 seconds
Started Apr 28 01:19:51 PM PDT 24
Finished Apr 28 01:19:52 PM PDT 24
Peak memory 201236 kb
Host smart-dd6fe883-a2f9-4193-943a-26521cb211cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491248489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2491248489
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3850256652
Short name T803
Test name
Test status
Simulation time 541511233 ps
CPU time 0.94 seconds
Started Apr 28 01:19:51 PM PDT 24
Finished Apr 28 01:19:52 PM PDT 24
Peak memory 201220 kb
Host smart-e6aae915-067f-49e2-aee6-bb08c189a129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850256652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3850256652
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2163506717
Short name T125
Test name
Test status
Simulation time 2638333354 ps
CPU time 8.54 seconds
Started Apr 28 01:19:50 PM PDT 24
Finished Apr 28 01:19:59 PM PDT 24
Peak memory 201520 kb
Host smart-93d421eb-04f2-4cde-b745-19e5741250d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163506717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2163506717
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.867446187
Short name T59
Test name
Test status
Simulation time 327770593 ps
CPU time 2.34 seconds
Started Apr 28 01:19:51 PM PDT 24
Finished Apr 28 01:19:54 PM PDT 24
Peak memory 201508 kb
Host smart-fdc14b27-ab4e-4793-b1d2-b935275e5a71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867446187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.867446187
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.188513446
Short name T353
Test name
Test status
Simulation time 4024048937 ps
CPU time 10.42 seconds
Started Apr 28 01:19:53 PM PDT 24
Finished Apr 28 01:20:04 PM PDT 24
Peak memory 201376 kb
Host smart-eb7873b4-e94e-421e-986b-5d07314a01fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188513446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_int
g_err.188513446
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.71117294
Short name T847
Test name
Test status
Simulation time 575162187 ps
CPU time 1.1 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:19:57 PM PDT 24
Peak memory 201308 kb
Host smart-f9ade826-d260-4e19-aeef-1b017ac7124d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71117294 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.71117294
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3874750774
Short name T817
Test name
Test status
Simulation time 600141828 ps
CPU time 0.87 seconds
Started Apr 28 01:19:58 PM PDT 24
Finished Apr 28 01:20:00 PM PDT 24
Peak memory 201216 kb
Host smart-b330945b-8165-4ccd-9de7-b07f17471d0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874750774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3874750774
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1047474897
Short name T861
Test name
Test status
Simulation time 329289889 ps
CPU time 0.77 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:19:56 PM PDT 24
Peak memory 201228 kb
Host smart-2de64b60-69fe-401b-ba0f-412a16d03c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047474897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1047474897
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.1143785326
Short name T128
Test name
Test status
Simulation time 2461852689 ps
CPU time 2.17 seconds
Started Apr 28 01:19:59 PM PDT 24
Finished Apr 28 01:20:01 PM PDT 24
Peak memory 201272 kb
Host smart-8dc633db-1549-498f-be71-1acf026d9cb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143785326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.1143785326
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1617786747
Short name T824
Test name
Test status
Simulation time 531994654 ps
CPU time 3.49 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:19:59 PM PDT 24
Peak memory 209696 kb
Host smart-2812ade9-67cd-4e83-bc24-ef311d561523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617786747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1617786747
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2360218760
Short name T873
Test name
Test status
Simulation time 3848408685 ps
CPU time 9.68 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:20:05 PM PDT 24
Peak memory 201472 kb
Host smart-254d5756-bfb6-413a-b4d4-dd19de2c5b33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360218760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2360218760
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2666281233
Short name T906
Test name
Test status
Simulation time 543820241 ps
CPU time 1.61 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:19:58 PM PDT 24
Peak memory 201184 kb
Host smart-353a2a04-a96f-4ede-b8ad-8f236075021b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666281233 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2666281233
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1215300758
Short name T908
Test name
Test status
Simulation time 521782633 ps
CPU time 1.08 seconds
Started Apr 28 01:19:55 PM PDT 24
Finished Apr 28 01:19:57 PM PDT 24
Peak memory 201124 kb
Host smart-3757c4a5-1366-4850-9f57-dbdc5fc414cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215300758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1215300758
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.401912194
Short name T893
Test name
Test status
Simulation time 517661104 ps
CPU time 1.94 seconds
Started Apr 28 01:19:57 PM PDT 24
Finished Apr 28 01:19:59 PM PDT 24
Peak memory 201200 kb
Host smart-01848c0b-f971-4e3a-971f-570d7dc9f8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401912194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.401912194
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.362202270
Short name T843
Test name
Test status
Simulation time 4874264051 ps
CPU time 8.07 seconds
Started Apr 28 01:19:56 PM PDT 24
Finished Apr 28 01:20:04 PM PDT 24
Peak memory 201516 kb
Host smart-a8560e2e-32bd-4af7-bb1d-2fcde6a36891
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362202270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.362202270
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.623094706
Short name T851
Test name
Test status
Simulation time 461730588 ps
CPU time 2.52 seconds
Started Apr 28 01:19:57 PM PDT 24
Finished Apr 28 01:20:00 PM PDT 24
Peak memory 201368 kb
Host smart-5b34639f-812c-4a81-8cd8-14a35fd13e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623094706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.623094706
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.441115598
Short name T354
Test name
Test status
Simulation time 4316126533 ps
CPU time 11.48 seconds
Started Apr 28 01:19:57 PM PDT 24
Finished Apr 28 01:20:09 PM PDT 24
Peak memory 201376 kb
Host smart-977c983c-fb0b-43ea-a43a-b3aa6e000938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441115598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.441115598
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2757690735
Short name T463
Test name
Test status
Simulation time 246077371232 ps
CPU time 182.05 seconds
Started Apr 28 02:45:29 PM PDT 24
Finished Apr 28 02:48:31 PM PDT 24
Peak memory 202340 kb
Host smart-618fdf2c-f969-4928-a75e-d4090cf6dd49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757690735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2757690735
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3728993286
Short name T330
Test name
Test status
Simulation time 327200123978 ps
CPU time 772.08 seconds
Started Apr 28 02:45:28 PM PDT 24
Finished Apr 28 02:58:21 PM PDT 24
Peak memory 202324 kb
Host smart-7f21496e-2785-4623-872f-bf7a25274398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728993286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3728993286
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4265016631
Short name T764
Test name
Test status
Simulation time 164950551948 ps
CPU time 76.95 seconds
Started Apr 28 02:45:29 PM PDT 24
Finished Apr 28 02:46:47 PM PDT 24
Peak memory 202396 kb
Host smart-898bbfa6-5d7c-42ed-ae3f-2ee5ad4c358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265016631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4265016631
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.740979044
Short name T685
Test name
Test status
Simulation time 165095681346 ps
CPU time 68.05 seconds
Started Apr 28 02:45:28 PM PDT 24
Finished Apr 28 02:46:37 PM PDT 24
Peak memory 202248 kb
Host smart-e159300b-d316-491a-a9b6-bf369f8a85c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=740979044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt
_fixed.740979044
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2960954649
Short name T703
Test name
Test status
Simulation time 333686442554 ps
CPU time 123.49 seconds
Started Apr 28 02:45:27 PM PDT 24
Finished Apr 28 02:47:31 PM PDT 24
Peak memory 202364 kb
Host smart-d725959a-1f3b-4792-a03f-a7a480fc50bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960954649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2960954649
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2658746753
Short name T782
Test name
Test status
Simulation time 167613315476 ps
CPU time 33.67 seconds
Started Apr 28 02:45:28 PM PDT 24
Finished Apr 28 02:46:02 PM PDT 24
Peak memory 202360 kb
Host smart-4c971e10-01db-4daf-8604-353aad8ebffd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658746753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2658746753
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2878272474
Short name T185
Test name
Test status
Simulation time 351205771229 ps
CPU time 128.79 seconds
Started Apr 28 02:45:28 PM PDT 24
Finished Apr 28 02:47:38 PM PDT 24
Peak memory 202328 kb
Host smart-e5b9de68-0ce7-47aa-bff9-53b7385cc544
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878272474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2878272474
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2184101821
Short name T377
Test name
Test status
Simulation time 200659593906 ps
CPU time 78.92 seconds
Started Apr 28 02:45:27 PM PDT 24
Finished Apr 28 02:46:47 PM PDT 24
Peak memory 202300 kb
Host smart-5b3f37d3-0d29-4162-8b85-6306b63a015c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184101821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2184101821
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3926001744
Short name T395
Test name
Test status
Simulation time 103245474243 ps
CPU time 562.21 seconds
Started Apr 28 02:45:28 PM PDT 24
Finished Apr 28 02:54:51 PM PDT 24
Peak memory 202624 kb
Host smart-f8863bb9-48d0-46bd-9b85-6ea82f80b6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926001744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3926001744
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2396226154
Short name T671
Test name
Test status
Simulation time 26600918730 ps
CPU time 15.24 seconds
Started Apr 28 02:45:26 PM PDT 24
Finished Apr 28 02:45:42 PM PDT 24
Peak memory 202140 kb
Host smart-6318399b-80a6-4d41-9dfc-d50d7b72d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396226154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2396226154
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.2183823957
Short name T745
Test name
Test status
Simulation time 4399642826 ps
CPU time 6.11 seconds
Started Apr 28 02:45:26 PM PDT 24
Finished Apr 28 02:45:33 PM PDT 24
Peak memory 202116 kb
Host smart-b82327ef-a2f4-4e0e-9947-85b3d69fb090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183823957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.2183823957
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1666633057
Short name T515
Test name
Test status
Simulation time 6120093031 ps
CPU time 4.79 seconds
Started Apr 28 02:45:29 PM PDT 24
Finished Apr 28 02:45:34 PM PDT 24
Peak memory 202140 kb
Host smart-2c5c1053-2d51-4fde-899f-b6f37c3d1ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666633057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1666633057
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2140328219
Short name T168
Test name
Test status
Simulation time 500146398780 ps
CPU time 606.6 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:55:39 PM PDT 24
Peak memory 202412 kb
Host smart-f7e9fc4d-6dc2-4ee3-9fb5-1f1153813d4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140328219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2140328219
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.23504542
Short name T23
Test name
Test status
Simulation time 278678963820 ps
CPU time 186.03 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:48:38 PM PDT 24
Peak memory 211000 kb
Host smart-42619b74-d878-4ba0-95ed-d00d0557cd54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23504542 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.23504542
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3367543749
Short name T473
Test name
Test status
Simulation time 445336683 ps
CPU time 0.93 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:45:34 PM PDT 24
Peak memory 202000 kb
Host smart-b926cbb3-645c-4c07-a650-adfd69ed0774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367543749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3367543749
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.945053809
Short name T695
Test name
Test status
Simulation time 327140021651 ps
CPU time 783.7 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:58:35 PM PDT 24
Peak memory 202312 kb
Host smart-6034466e-6ecb-4d76-9c2b-b3ef88e1383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945053809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.945053809
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.243872984
Short name T287
Test name
Test status
Simulation time 492690567677 ps
CPU time 321.3 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:50:54 PM PDT 24
Peak memory 202300 kb
Host smart-9a0adbff-f4d3-4863-b0ac-c4a8b75f74bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243872984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.243872984
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3808511544
Short name T429
Test name
Test status
Simulation time 163742256110 ps
CPU time 105.4 seconds
Started Apr 28 02:45:30 PM PDT 24
Finished Apr 28 02:47:16 PM PDT 24
Peak memory 202228 kb
Host smart-ede65f69-81cc-4feb-944b-93e6a0eeb482
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808511544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3808511544
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3138438759
Short name T321
Test name
Test status
Simulation time 158046272476 ps
CPU time 199.75 seconds
Started Apr 28 02:45:30 PM PDT 24
Finished Apr 28 02:48:51 PM PDT 24
Peak memory 202308 kb
Host smart-87e73ce9-b1bf-4e6f-bc22-54abc5ffefeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138438759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3138438759
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1433157917
Short name T616
Test name
Test status
Simulation time 163602422160 ps
CPU time 101.21 seconds
Started Apr 28 02:45:30 PM PDT 24
Finished Apr 28 02:47:12 PM PDT 24
Peak memory 202340 kb
Host smart-4106b02c-b6fd-42b7-a6ad-d4833983d5dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433157917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1433157917
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.212403107
Short name T143
Test name
Test status
Simulation time 517164906898 ps
CPU time 308.81 seconds
Started Apr 28 02:45:35 PM PDT 24
Finished Apr 28 02:50:44 PM PDT 24
Peak memory 202408 kb
Host smart-0bedfa06-ab5b-419e-a51e-e26c6fc81c28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212403107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.212403107
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3158550369
Short name T771
Test name
Test status
Simulation time 391187591325 ps
CPU time 435.11 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:52:48 PM PDT 24
Peak memory 202284 kb
Host smart-93c3292f-1116-4894-96f6-f193d10f5ca7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158550369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3158550369
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.2181212513
Short name T32
Test name
Test status
Simulation time 94629844000 ps
CPU time 309.22 seconds
Started Apr 28 02:45:39 PM PDT 24
Finished Apr 28 02:50:50 PM PDT 24
Peak memory 202164 kb
Host smart-16ba5314-e1c6-4755-96f4-4fc332e9d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181212513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.2181212513
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.245462271
Short name T724
Test name
Test status
Simulation time 22316477355 ps
CPU time 56.32 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:46:29 PM PDT 24
Peak memory 202140 kb
Host smart-e6e52d13-182f-48d5-87f2-350acdaa9191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245462271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.245462271
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2333628360
Short name T573
Test name
Test status
Simulation time 3246765394 ps
CPU time 8.36 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:45:42 PM PDT 24
Peak memory 202096 kb
Host smart-202e5224-2c27-42bc-80d0-96ea40b965d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333628360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2333628360
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.2830668690
Short name T56
Test name
Test status
Simulation time 4606351106 ps
CPU time 11.29 seconds
Started Apr 28 02:45:33 PM PDT 24
Finished Apr 28 02:45:45 PM PDT 24
Peak memory 217932 kb
Host smart-35b8bf5d-0d30-4800-82fe-7f71c3f3f1c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830668690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.2830668690
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.252152244
Short name T409
Test name
Test status
Simulation time 5720208201 ps
CPU time 15.38 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:45:49 PM PDT 24
Peak memory 202124 kb
Host smart-c404648f-647f-4a52-b003-1d80966e938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252152244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.252152244
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1224150088
Short name T35
Test name
Test status
Simulation time 40381604245 ps
CPU time 48.54 seconds
Started Apr 28 02:45:35 PM PDT 24
Finished Apr 28 02:46:25 PM PDT 24
Peak memory 202164 kb
Host smart-ccc555d6-403b-4668-b525-0afb80a234d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224150088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1224150088
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.719259287
Short name T66
Test name
Test status
Simulation time 605967950 ps
CPU time 0.73 seconds
Started Apr 28 02:46:11 PM PDT 24
Finished Apr 28 02:46:13 PM PDT 24
Peak memory 201992 kb
Host smart-97f4420d-4285-48ce-949d-327092b4595c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719259287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.719259287
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3821100034
Short name T314
Test name
Test status
Simulation time 566648625804 ps
CPU time 858.38 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 03:00:32 PM PDT 24
Peak memory 202272 kb
Host smart-0a9d236e-3fbd-4d54-b23c-63373c263b46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821100034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3821100034
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1827898574
Short name T229
Test name
Test status
Simulation time 171260700008 ps
CPU time 98.23 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 02:47:51 PM PDT 24
Peak memory 202388 kb
Host smart-da2ba6d7-5b43-4577-be23-53755c6dbec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827898574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1827898574
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3023529055
Short name T283
Test name
Test status
Simulation time 161083712633 ps
CPU time 366.31 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:52:03 PM PDT 24
Peak memory 202380 kb
Host smart-62efe6e4-1b66-4760-82cd-afcef043b413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023529055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3023529055
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3905097734
Short name T589
Test name
Test status
Simulation time 325052682472 ps
CPU time 88.88 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:47:26 PM PDT 24
Peak memory 202300 kb
Host smart-039f5b77-3cb6-42ac-95a7-90db853adba0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905097734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3905097734
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4064255453
Short name T418
Test name
Test status
Simulation time 169140151787 ps
CPU time 81.18 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 02:47:34 PM PDT 24
Peak memory 202240 kb
Host smart-b162e62f-71a1-4b45-b305-f98dd3add3fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064255453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4064255453
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3499766699
Short name T634
Test name
Test status
Simulation time 603936042843 ps
CPU time 1312.2 seconds
Started Apr 28 02:45:57 PM PDT 24
Finished Apr 28 03:07:50 PM PDT 24
Peak memory 202256 kb
Host smart-dc6b711d-9d7a-4827-8436-a5d4c60a1d80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499766699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3499766699
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3925866895
Short name T10
Test name
Test status
Simulation time 37833613463 ps
CPU time 84 seconds
Started Apr 28 02:46:00 PM PDT 24
Finished Apr 28 02:47:24 PM PDT 24
Peak memory 202172 kb
Host smart-f7a52056-5bbe-4d60-8357-def3392d4096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925866895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3925866895
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2362249420
Short name T548
Test name
Test status
Simulation time 3958149483 ps
CPU time 10.57 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:46:10 PM PDT 24
Peak memory 201516 kb
Host smart-4392281c-4630-4ffe-b949-59cdbbcc7347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362249420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2362249420
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.102676710
Short name T371
Test name
Test status
Simulation time 5994068094 ps
CPU time 14.43 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:46:11 PM PDT 24
Peak memory 202116 kb
Host smart-e915205e-1351-4013-9416-ad4c890c0510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102676710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.102676710
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3853098966
Short name T351
Test name
Test status
Simulation time 333525952318 ps
CPU time 743.22 seconds
Started Apr 28 02:46:00 PM PDT 24
Finished Apr 28 02:58:23 PM PDT 24
Peak memory 202352 kb
Host smart-64cccbe5-549d-4074-84d4-451d25eafc68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853098966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3853098966
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1184818135
Short name T598
Test name
Test status
Simulation time 89106698930 ps
CPU time 42.57 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:46:42 PM PDT 24
Peak memory 202432 kb
Host smart-289e532b-1164-47d6-ac52-5c4fcde846cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184818135 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1184818135
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3870642521
Short name T385
Test name
Test status
Simulation time 384773109 ps
CPU time 0.75 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:46:03 PM PDT 24
Peak memory 201992 kb
Host smart-6b53d3e9-54e3-4a18-ae91-58c22b3fdc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870642521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3870642521
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3505056103
Short name T247
Test name
Test status
Simulation time 178821476217 ps
CPU time 240.75 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:50:04 PM PDT 24
Peak memory 202296 kb
Host smart-82d484eb-0ebe-4a5c-8e74-f226709bebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505056103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3505056103
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.253198295
Short name T494
Test name
Test status
Simulation time 329979203298 ps
CPU time 210.97 seconds
Started Apr 28 02:46:03 PM PDT 24
Finished Apr 28 02:49:35 PM PDT 24
Peak memory 202220 kb
Host smart-e6a1d39a-b21d-4486-b152-c4c3656d6cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253198295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.253198295
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3959204934
Short name T455
Test name
Test status
Simulation time 495600901151 ps
CPU time 299.9 seconds
Started Apr 28 02:46:01 PM PDT 24
Finished Apr 28 02:51:02 PM PDT 24
Peak memory 202304 kb
Host smart-d1c6c9a0-52fb-422c-b6ee-4b21865111ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959204934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3959204934
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.268545568
Short name T206
Test name
Test status
Simulation time 168102125601 ps
CPU time 101.29 seconds
Started Apr 28 02:45:55 PM PDT 24
Finished Apr 28 02:47:37 PM PDT 24
Peak memory 202312 kb
Host smart-9b4da517-33d8-4014-82c2-3bab17075e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268545568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.268545568
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.307002456
Short name T430
Test name
Test status
Simulation time 328864354880 ps
CPU time 369.28 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:52:09 PM PDT 24
Peak memory 202356 kb
Host smart-c24af316-80f3-4661-bf84-1bc3df829ab0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=307002456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.307002456
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.864291517
Short name T597
Test name
Test status
Simulation time 405626200418 ps
CPU time 155.17 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:48:35 PM PDT 24
Peak memory 202412 kb
Host smart-414307bc-1104-4135-a07f-2e217da733a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864291517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.864291517
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3990324267
Short name T670
Test name
Test status
Simulation time 405343305137 ps
CPU time 53.78 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:46:57 PM PDT 24
Peak memory 202268 kb
Host smart-d1c35a2b-cf8f-46df-8545-55c335ec3e00
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990324267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3990324267
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.3092291753
Short name T374
Test name
Test status
Simulation time 29629882132 ps
CPU time 16.09 seconds
Started Apr 28 02:46:00 PM PDT 24
Finished Apr 28 02:46:17 PM PDT 24
Peak memory 202140 kb
Host smart-8916c029-27b0-4d61-9235-2b41e86c2747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092291753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.3092291753
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.300729469
Short name T370
Test name
Test status
Simulation time 3216812404 ps
CPU time 4.85 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:46:07 PM PDT 24
Peak memory 202128 kb
Host smart-b50fe339-9beb-4c75-b6cb-633843aa97eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300729469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.300729469
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2705417532
Short name T570
Test name
Test status
Simulation time 5740846463 ps
CPU time 15.38 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:46:15 PM PDT 24
Peak memory 202108 kb
Host smart-f8dfd8dc-f85e-4923-b99a-94f2207c3a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705417532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2705417532
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2403625759
Short name T464
Test name
Test status
Simulation time 209519283666 ps
CPU time 502.81 seconds
Started Apr 28 02:46:03 PM PDT 24
Finished Apr 28 02:54:26 PM PDT 24
Peak memory 202216 kb
Host smart-248f172e-d1da-4cea-93df-4800066f575e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403625759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2403625759
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2177727170
Short name T349
Test name
Test status
Simulation time 46266459285 ps
CPU time 61.68 seconds
Started Apr 28 02:46:01 PM PDT 24
Finished Apr 28 02:47:04 PM PDT 24
Peak memory 211100 kb
Host smart-e6b2fa74-f9b1-4f30-9570-21bab2be861c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177727170 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2177727170
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2252974669
Short name T372
Test name
Test status
Simulation time 445509525 ps
CPU time 0.87 seconds
Started Apr 28 02:46:04 PM PDT 24
Finished Apr 28 02:46:06 PM PDT 24
Peak memory 202020 kb
Host smart-9dd30b85-42f0-4557-9ae4-ad90a5c1fcae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252974669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2252974669
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3224388858
Short name T588
Test name
Test status
Simulation time 353459608127 ps
CPU time 415.65 seconds
Started Apr 28 02:46:06 PM PDT 24
Finished Apr 28 02:53:02 PM PDT 24
Peak memory 202412 kb
Host smart-7adfba6b-321a-4d6c-91b0-1f2fd7978c13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224388858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3224388858
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3907650524
Short name T323
Test name
Test status
Simulation time 492023031793 ps
CPU time 283.18 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:50:46 PM PDT 24
Peak memory 202292 kb
Host smart-c42c5486-f441-420f-9fc9-6d072db9ac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907650524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3907650524
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2217306889
Short name T537
Test name
Test status
Simulation time 172178936632 ps
CPU time 107.84 seconds
Started Apr 28 02:46:04 PM PDT 24
Finished Apr 28 02:47:52 PM PDT 24
Peak memory 202288 kb
Host smart-f327c067-14eb-4686-ad6e-3a46c374bb43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217306889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2217306889
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.76073015
Short name T81
Test name
Test status
Simulation time 321584073019 ps
CPU time 695.43 seconds
Started Apr 28 02:46:01 PM PDT 24
Finished Apr 28 02:57:37 PM PDT 24
Peak memory 202336 kb
Host smart-92f68fa1-444c-4793-a895-7bff7ee543c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76073015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.76073015
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1333389699
Short name T378
Test name
Test status
Simulation time 493747195060 ps
CPU time 311.46 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:51:14 PM PDT 24
Peak memory 202192 kb
Host smart-735bfd63-ab68-46bb-be76-4d939f50ad5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333389699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1333389699
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.2770708654
Short name T669
Test name
Test status
Simulation time 543158693906 ps
CPU time 615.81 seconds
Started Apr 28 02:46:06 PM PDT 24
Finished Apr 28 02:56:23 PM PDT 24
Peak memory 202340 kb
Host smart-f34d01ef-6fb4-425c-9649-96feade04496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770708654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.2770708654
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.1536877750
Short name T435
Test name
Test status
Simulation time 197446153284 ps
CPU time 44.15 seconds
Started Apr 28 02:46:07 PM PDT 24
Finished Apr 28 02:46:52 PM PDT 24
Peak memory 202308 kb
Host smart-ed9ff8a3-ea5e-429a-ace1-b241e5cd8a2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536877750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.1536877750
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1600623743
Short name T794
Test name
Test status
Simulation time 91376983965 ps
CPU time 472.73 seconds
Started Apr 28 02:46:07 PM PDT 24
Finished Apr 28 02:54:00 PM PDT 24
Peak memory 202664 kb
Host smart-e85e1862-0a47-4ee0-8dcd-1ab7b5cc77d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600623743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1600623743
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2443074055
Short name T106
Test name
Test status
Simulation time 25898916101 ps
CPU time 4.71 seconds
Started Apr 28 02:46:08 PM PDT 24
Finished Apr 28 02:46:13 PM PDT 24
Peak memory 202152 kb
Host smart-5ea8b10e-bd30-4a7b-ac0b-ce4539ff7577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443074055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2443074055
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2362317844
Short name T602
Test name
Test status
Simulation time 3449203346 ps
CPU time 4.26 seconds
Started Apr 28 02:46:05 PM PDT 24
Finished Apr 28 02:46:10 PM PDT 24
Peak memory 202028 kb
Host smart-f02cd3b7-73ca-47cc-98ff-cea6de132265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362317844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2362317844
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2424557330
Short name T387
Test name
Test status
Simulation time 6089698348 ps
CPU time 4.9 seconds
Started Apr 28 02:46:02 PM PDT 24
Finished Apr 28 02:46:07 PM PDT 24
Peak memory 202160 kb
Host smart-2da4efe3-c068-433b-9e96-76659a3f3552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424557330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2424557330
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1586949315
Short name T779
Test name
Test status
Simulation time 44580341263 ps
CPU time 228.82 seconds
Started Apr 28 02:46:07 PM PDT 24
Finished Apr 28 02:49:57 PM PDT 24
Peak memory 211076 kb
Host smart-7af705b1-6e40-4aed-9665-1a009f064617
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586949315 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1586949315
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.749167525
Short name T68
Test name
Test status
Simulation time 512583470 ps
CPU time 1.21 seconds
Started Apr 28 02:46:16 PM PDT 24
Finished Apr 28 02:46:18 PM PDT 24
Peak memory 201968 kb
Host smart-ab3fa88c-ca06-4279-b253-4af06373e1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749167525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.749167525
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.833109626
Short name T221
Test name
Test status
Simulation time 497323094668 ps
CPU time 317.6 seconds
Started Apr 28 02:46:06 PM PDT 24
Finished Apr 28 02:51:24 PM PDT 24
Peak memory 202308 kb
Host smart-6eb1c445-8118-46c9-ad98-8e08ac6467c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833109626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.833109626
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1185908087
Short name T694
Test name
Test status
Simulation time 171556046928 ps
CPU time 103.22 seconds
Started Apr 28 02:46:06 PM PDT 24
Finished Apr 28 02:47:50 PM PDT 24
Peak memory 202216 kb
Host smart-c02489fe-4e7d-44aa-ba7e-3bc171277dca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185908087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1185908087
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1060724826
Short name T211
Test name
Test status
Simulation time 169872098843 ps
CPU time 410.99 seconds
Started Apr 28 02:46:06 PM PDT 24
Finished Apr 28 02:52:58 PM PDT 24
Peak memory 202292 kb
Host smart-0e144ba1-18b5-4422-baf1-380863122e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060724826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1060724826
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3690293024
Short name T162
Test name
Test status
Simulation time 329844488034 ps
CPU time 276.97 seconds
Started Apr 28 02:46:05 PM PDT 24
Finished Apr 28 02:50:43 PM PDT 24
Peak memory 202268 kb
Host smart-2252a494-8d35-4fbd-bf34-9b0ccff4fbd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690293024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3690293024
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1285364534
Short name T657
Test name
Test status
Simulation time 206458944292 ps
CPU time 483.14 seconds
Started Apr 28 02:46:10 PM PDT 24
Finished Apr 28 02:54:14 PM PDT 24
Peak memory 202284 kb
Host smart-1d4a0e21-19dc-461d-a75b-db3703752716
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285364534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1285364534
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.179573055
Short name T571
Test name
Test status
Simulation time 117057991113 ps
CPU time 502.31 seconds
Started Apr 28 02:46:17 PM PDT 24
Finished Apr 28 02:54:40 PM PDT 24
Peak memory 202688 kb
Host smart-9f700ce0-3cb5-4bea-84b9-31e8dd333ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179573055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.179573055
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3177409697
Short name T732
Test name
Test status
Simulation time 32184563428 ps
CPU time 20.04 seconds
Started Apr 28 02:46:17 PM PDT 24
Finished Apr 28 02:46:38 PM PDT 24
Peak memory 202116 kb
Host smart-47f0522b-5cc6-4f6b-a5c5-8db5afe72deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177409697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3177409697
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2641337662
Short name T643
Test name
Test status
Simulation time 3714200788 ps
CPU time 4.67 seconds
Started Apr 28 02:46:17 PM PDT 24
Finished Apr 28 02:46:23 PM PDT 24
Peak memory 202100 kb
Host smart-6f11ae9f-2eb9-4c05-af10-dac949875408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641337662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2641337662
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.437549731
Short name T668
Test name
Test status
Simulation time 5846198338 ps
CPU time 3.74 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 02:46:17 PM PDT 24
Peak memory 202132 kb
Host smart-2fb4174a-7d3d-4665-86c4-689bbc4d4ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437549731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.437549731
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.956095356
Short name T672
Test name
Test status
Simulation time 35851846462 ps
CPU time 22.7 seconds
Started Apr 28 02:46:15 PM PDT 24
Finished Apr 28 02:46:38 PM PDT 24
Peak memory 202148 kb
Host smart-ac077583-8ba0-4994-b272-add086153cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956095356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
956095356
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3164411589
Short name T655
Test name
Test status
Simulation time 169364528166 ps
CPU time 161.56 seconds
Started Apr 28 02:46:17 PM PDT 24
Finished Apr 28 02:48:59 PM PDT 24
Peak memory 203092 kb
Host smart-755a422e-6a53-405f-914d-b02d8b8b3a35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164411589 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3164411589
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.363671601
Short name T499
Test name
Test status
Simulation time 408295363 ps
CPU time 0.67 seconds
Started Apr 28 02:46:27 PM PDT 24
Finished Apr 28 02:46:28 PM PDT 24
Peak memory 201992 kb
Host smart-d4475507-9d13-417f-a73c-f2ba3f1859fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363671601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.363671601
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1220493781
Short name T279
Test name
Test status
Simulation time 187906780203 ps
CPU time 434.61 seconds
Started Apr 28 02:46:22 PM PDT 24
Finished Apr 28 02:53:37 PM PDT 24
Peak memory 202396 kb
Host smart-74640bdd-38d3-4aab-84ff-b0815fa0857b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220493781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1220493781
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2610981436
Short name T488
Test name
Test status
Simulation time 493314558046 ps
CPU time 1184.02 seconds
Started Apr 28 02:46:21 PM PDT 24
Finished Apr 28 03:06:06 PM PDT 24
Peak memory 202292 kb
Host smart-75f8d42f-b765-415d-9c69-f988d75166b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610981436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2610981436
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.204070177
Short name T759
Test name
Test status
Simulation time 481737575671 ps
CPU time 827.22 seconds
Started Apr 28 02:46:15 PM PDT 24
Finished Apr 28 03:00:04 PM PDT 24
Peak memory 202376 kb
Host smart-26156263-38dc-41fa-895d-b373652cf0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204070177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.204070177
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.913912550
Short name T788
Test name
Test status
Simulation time 479751863553 ps
CPU time 1036.5 seconds
Started Apr 28 02:46:21 PM PDT 24
Finished Apr 28 03:03:38 PM PDT 24
Peak memory 202360 kb
Host smart-9967d2b2-11e9-4f1f-8f4f-3909c89562ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=913912550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.913912550
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1226267218
Short name T298
Test name
Test status
Simulation time 338906683993 ps
CPU time 763.81 seconds
Started Apr 28 02:46:21 PM PDT 24
Finished Apr 28 02:59:05 PM PDT 24
Peak memory 202388 kb
Host smart-015b12b8-437a-4955-800d-954552f82e04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226267218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1226267218
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1825458757
Short name T27
Test name
Test status
Simulation time 215430737117 ps
CPU time 485.52 seconds
Started Apr 28 02:46:22 PM PDT 24
Finished Apr 28 02:54:28 PM PDT 24
Peak memory 202288 kb
Host smart-92b4deef-5d16-49b3-b1e1-15d86e1de4e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825458757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1825458757
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.704534994
Short name T781
Test name
Test status
Simulation time 78511130657 ps
CPU time 263.86 seconds
Started Apr 28 02:46:23 PM PDT 24
Finished Apr 28 02:50:47 PM PDT 24
Peak memory 202732 kb
Host smart-b343a3b7-8666-4dba-b564-385e56a7fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704534994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.704534994
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3554346070
Short name T689
Test name
Test status
Simulation time 33268840263 ps
CPU time 78.81 seconds
Started Apr 28 02:46:24 PM PDT 24
Finished Apr 28 02:47:43 PM PDT 24
Peak memory 202120 kb
Host smart-74d0d4e2-9baf-47e8-ba54-29e4f7e65269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554346070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3554346070
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2382553808
Short name T470
Test name
Test status
Simulation time 3096139040 ps
CPU time 4.3 seconds
Started Apr 28 02:46:22 PM PDT 24
Finished Apr 28 02:46:27 PM PDT 24
Peak memory 202096 kb
Host smart-81e95c1a-9434-402d-9e52-84ea3a02b185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382553808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2382553808
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3775529778
Short name T654
Test name
Test status
Simulation time 5745988795 ps
CPU time 14.25 seconds
Started Apr 28 02:46:15 PM PDT 24
Finished Apr 28 02:46:30 PM PDT 24
Peak memory 202116 kb
Host smart-d5e9637f-1c00-47d6-a1d0-bf213dc94cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775529778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3775529778
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1468090054
Short name T609
Test name
Test status
Simulation time 332298361270 ps
CPU time 373.15 seconds
Started Apr 28 02:46:28 PM PDT 24
Finished Apr 28 02:52:41 PM PDT 24
Peak memory 202300 kb
Host smart-432e5dca-9c70-434e-b47b-c4e8f1b0a3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468090054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1468090054
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2766673617
Short name T101
Test name
Test status
Simulation time 45863166577 ps
CPU time 33.74 seconds
Started Apr 28 02:46:20 PM PDT 24
Finished Apr 28 02:46:54 PM PDT 24
Peak memory 211072 kb
Host smart-eea42887-67d4-4996-acc2-9ff5d1732b83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766673617 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2766673617
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2095226930
Short name T67
Test name
Test status
Simulation time 386047289 ps
CPU time 0.86 seconds
Started Apr 28 02:46:38 PM PDT 24
Finished Apr 28 02:46:39 PM PDT 24
Peak memory 201992 kb
Host smart-c5ac07b4-c657-42d0-bebb-619bc50ff3d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095226930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2095226930
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3390210809
Short name T665
Test name
Test status
Simulation time 529323812516 ps
CPU time 1190.18 seconds
Started Apr 28 02:46:34 PM PDT 24
Finished Apr 28 03:06:25 PM PDT 24
Peak memory 202312 kb
Host smart-0842dffa-bbaf-42fc-a13c-ddb801f6330e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390210809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3390210809
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.2943625558
Short name T315
Test name
Test status
Simulation time 158105924844 ps
CPU time 160.9 seconds
Started Apr 28 02:46:35 PM PDT 24
Finished Apr 28 02:49:16 PM PDT 24
Peak memory 202224 kb
Host smart-9eaac934-d4c1-44c2-9f5f-d6de3bef3aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943625558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.2943625558
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1135228918
Short name T444
Test name
Test status
Simulation time 167182562571 ps
CPU time 214.43 seconds
Started Apr 28 02:46:32 PM PDT 24
Finished Apr 28 02:50:07 PM PDT 24
Peak memory 202292 kb
Host smart-48876291-fc93-4812-99f2-9239657195e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135228918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1135228918
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1867010479
Short name T84
Test name
Test status
Simulation time 496585614167 ps
CPU time 1245.18 seconds
Started Apr 28 02:46:30 PM PDT 24
Finished Apr 28 03:07:15 PM PDT 24
Peak memory 202328 kb
Host smart-dc948e25-e097-42fb-895e-819196757019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867010479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1867010479
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2035508482
Short name T578
Test name
Test status
Simulation time 328748052861 ps
CPU time 416.35 seconds
Started Apr 28 02:46:28 PM PDT 24
Finished Apr 28 02:53:24 PM PDT 24
Peak memory 202360 kb
Host smart-e1039f07-f232-4351-876f-b0a6ac570465
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035508482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2035508482
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3958177608
Short name T517
Test name
Test status
Simulation time 192853888269 ps
CPU time 421.38 seconds
Started Apr 28 02:46:32 PM PDT 24
Finished Apr 28 02:53:34 PM PDT 24
Peak memory 202268 kb
Host smart-26a10ae9-9c43-4c1d-8fb1-b57901354e73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958177608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3958177608
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2447770092
Short name T679
Test name
Test status
Simulation time 199203424499 ps
CPU time 117.55 seconds
Started Apr 28 02:46:33 PM PDT 24
Finished Apr 28 02:48:31 PM PDT 24
Peak memory 202296 kb
Host smart-d40f465e-2516-442d-bc99-181aa86ae2a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447770092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2447770092
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3231446294
Short name T564
Test name
Test status
Simulation time 104640366110 ps
CPU time 481.82 seconds
Started Apr 28 02:46:36 PM PDT 24
Finished Apr 28 02:54:39 PM PDT 24
Peak memory 202652 kb
Host smart-602bac08-da56-4c49-853d-d9896552eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231446294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3231446294
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3396694342
Short name T440
Test name
Test status
Simulation time 28767805020 ps
CPU time 20.25 seconds
Started Apr 28 02:46:32 PM PDT 24
Finished Apr 28 02:46:52 PM PDT 24
Peak memory 202104 kb
Host smart-89ad2d2b-4355-4546-84c6-3fa84d54edb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396694342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3396694342
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.596587689
Short name T784
Test name
Test status
Simulation time 3465053263 ps
CPU time 2.42 seconds
Started Apr 28 02:46:32 PM PDT 24
Finished Apr 28 02:46:35 PM PDT 24
Peak memory 202128 kb
Host smart-1abfd4d7-c2c8-4c55-ba8a-38055ae350b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596587689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.596587689
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.1182888498
Short name T379
Test name
Test status
Simulation time 5635431103 ps
CPU time 4.14 seconds
Started Apr 28 02:46:28 PM PDT 24
Finished Apr 28 02:46:32 PM PDT 24
Peak memory 202132 kb
Host smart-53cbe934-04a3-4cc6-90f3-7f8d96b6423c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182888498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.1182888498
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.4153011368
Short name T201
Test name
Test status
Simulation time 403528816992 ps
CPU time 1194.39 seconds
Started Apr 28 02:46:40 PM PDT 24
Finished Apr 28 03:06:35 PM PDT 24
Peak memory 202608 kb
Host smart-50bb45e3-4fe1-4c1d-88f3-917b7f76f039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153011368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.4153011368
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.982880404
Short name T16
Test name
Test status
Simulation time 56453630747 ps
CPU time 55.02 seconds
Started Apr 28 02:46:41 PM PDT 24
Finished Apr 28 02:47:36 PM PDT 24
Peak memory 210560 kb
Host smart-9fdf8395-6ae7-411a-b806-a7ec0c609e6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982880404 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.982880404
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3524765401
Short name T567
Test name
Test status
Simulation time 375696488 ps
CPU time 1.01 seconds
Started Apr 28 02:46:51 PM PDT 24
Finished Apr 28 02:46:52 PM PDT 24
Peak memory 201956 kb
Host smart-7b9f13ef-ef1a-45cc-b9b5-4d5d59e0b4ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524765401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3524765401
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2341924903
Short name T649
Test name
Test status
Simulation time 170319666568 ps
CPU time 91.2 seconds
Started Apr 28 02:46:42 PM PDT 24
Finished Apr 28 02:48:14 PM PDT 24
Peak memory 202376 kb
Host smart-cfbebe19-78f9-4bf2-99ce-682497de87fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341924903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2341924903
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3155997140
Short name T24
Test name
Test status
Simulation time 167749884810 ps
CPU time 376.28 seconds
Started Apr 28 02:46:43 PM PDT 24
Finished Apr 28 02:53:00 PM PDT 24
Peak memory 202364 kb
Host smart-623ae231-92dd-40bb-92b2-e7a91bc3672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155997140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3155997140
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3743566033
Short name T334
Test name
Test status
Simulation time 167156349535 ps
CPU time 107.19 seconds
Started Apr 28 02:46:44 PM PDT 24
Finished Apr 28 02:48:32 PM PDT 24
Peak memory 202284 kb
Host smart-7160c63b-2106-4f43-b502-d87ec9f6591f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743566033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3743566033
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.845287911
Short name T720
Test name
Test status
Simulation time 162077417535 ps
CPU time 187.57 seconds
Started Apr 28 02:46:38 PM PDT 24
Finished Apr 28 02:49:45 PM PDT 24
Peak memory 202400 kb
Host smart-dde37181-4870-4ba8-ad37-91e009f750a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845287911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.845287911
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2979664033
Short name T686
Test name
Test status
Simulation time 169501570413 ps
CPU time 374.36 seconds
Started Apr 28 02:46:40 PM PDT 24
Finished Apr 28 02:52:54 PM PDT 24
Peak memory 202204 kb
Host smart-87c6e2c5-7a3d-4ffb-9191-05b79c034c5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979664033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2979664033
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.274730882
Short name T302
Test name
Test status
Simulation time 191173993221 ps
CPU time 154.79 seconds
Started Apr 28 02:46:42 PM PDT 24
Finished Apr 28 02:49:18 PM PDT 24
Peak memory 202300 kb
Host smart-6905f57f-d326-48ef-919b-32dda101b326
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274730882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.274730882
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.433663600
Short name T727
Test name
Test status
Simulation time 205472399523 ps
CPU time 484.71 seconds
Started Apr 28 02:46:43 PM PDT 24
Finished Apr 28 02:54:48 PM PDT 24
Peak memory 202272 kb
Host smart-d402e68e-977f-4759-9d00-e3135968aafd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433663600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.433663600
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1462072620
Short name T632
Test name
Test status
Simulation time 31300010159 ps
CPU time 38.52 seconds
Started Apr 28 02:46:43 PM PDT 24
Finished Apr 28 02:47:22 PM PDT 24
Peak memory 202152 kb
Host smart-ead7d608-58a5-47cf-905e-b9cb23ba9146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462072620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1462072620
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.699161184
Short name T30
Test name
Test status
Simulation time 5539518768 ps
CPU time 3.23 seconds
Started Apr 28 02:46:42 PM PDT 24
Finished Apr 28 02:46:45 PM PDT 24
Peak memory 202084 kb
Host smart-d6e72c6f-237d-47ee-9b0f-524429fc59d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699161184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.699161184
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.202415538
Short name T452
Test name
Test status
Simulation time 5820526137 ps
CPU time 6.86 seconds
Started Apr 28 02:46:36 PM PDT 24
Finished Apr 28 02:46:43 PM PDT 24
Peak memory 202112 kb
Host smart-f42ef696-bd56-44b7-8e09-42178ef86703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202415538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.202415538
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.976530675
Short name T729
Test name
Test status
Simulation time 334686970934 ps
CPU time 239.37 seconds
Started Apr 28 02:46:48 PM PDT 24
Finished Apr 28 02:50:48 PM PDT 24
Peak memory 202312 kb
Host smart-07b16a5c-4c57-479b-b984-ac5c56721861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976530675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
976530675
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2982811298
Short name T342
Test name
Test status
Simulation time 168756773774 ps
CPU time 181.85 seconds
Started Apr 28 02:46:46 PM PDT 24
Finished Apr 28 02:49:48 PM PDT 24
Peak memory 210672 kb
Host smart-ca757ffa-64db-4271-8cb6-e49e820bb9aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982811298 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2982811298
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1220207411
Short name T697
Test name
Test status
Simulation time 326154594 ps
CPU time 1.36 seconds
Started Apr 28 02:46:57 PM PDT 24
Finished Apr 28 02:46:59 PM PDT 24
Peak memory 201992 kb
Host smart-17790e79-14b0-444b-9534-270c15e8b36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220207411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1220207411
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3235465781
Short name T263
Test name
Test status
Simulation time 337399805226 ps
CPU time 807.93 seconds
Started Apr 28 02:46:53 PM PDT 24
Finished Apr 28 03:00:21 PM PDT 24
Peak memory 202216 kb
Host smart-5b116949-d186-4dca-8922-31a1793964ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235465781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3235465781
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4222299019
Short name T797
Test name
Test status
Simulation time 374685649173 ps
CPU time 896.83 seconds
Started Apr 28 02:46:54 PM PDT 24
Finished Apr 28 03:01:51 PM PDT 24
Peak memory 202352 kb
Host smart-9f33bfa7-ff49-4ba5-86f0-75ffc59f8b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222299019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4222299019
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.346013926
Short name T562
Test name
Test status
Simulation time 169911019465 ps
CPU time 102.08 seconds
Started Apr 28 02:46:48 PM PDT 24
Finished Apr 28 02:48:31 PM PDT 24
Peak memory 202308 kb
Host smart-b6f9a9e0-678d-4cae-ba89-a31bdd0593ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346013926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.346013926
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.891324858
Short name T644
Test name
Test status
Simulation time 495356658036 ps
CPU time 278.19 seconds
Started Apr 28 02:46:50 PM PDT 24
Finished Apr 28 02:51:29 PM PDT 24
Peak memory 202260 kb
Host smart-1fa8965f-753c-41b2-a685-6ca0686b13e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=891324858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.891324858
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.646853150
Short name T93
Test name
Test status
Simulation time 161903620175 ps
CPU time 346.91 seconds
Started Apr 28 02:46:48 PM PDT 24
Finished Apr 28 02:52:35 PM PDT 24
Peak memory 202292 kb
Host smart-4c519168-b6fb-4368-bd6f-36ec8b145637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646853150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.646853150
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2951911413
Short name T8
Test name
Test status
Simulation time 491571118976 ps
CPU time 289.47 seconds
Started Apr 28 02:46:47 PM PDT 24
Finished Apr 28 02:51:37 PM PDT 24
Peak memory 202308 kb
Host smart-3b1655b1-f157-4bf1-b932-ab8567b14d23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951911413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2951911413
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3521580163
Short name T500
Test name
Test status
Simulation time 204850520197 ps
CPU time 122.48 seconds
Started Apr 28 02:46:46 PM PDT 24
Finished Apr 28 02:48:49 PM PDT 24
Peak memory 202268 kb
Host smart-8780a760-d044-4aa0-bda6-f1170947b1eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521580163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3521580163
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2858205360
Short name T503
Test name
Test status
Simulation time 86413270897 ps
CPU time 336.28 seconds
Started Apr 28 02:46:57 PM PDT 24
Finished Apr 28 02:52:34 PM PDT 24
Peak memory 202752 kb
Host smart-43958227-5d76-40e5-8fe1-8afa5c9210fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858205360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2858205360
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.305624461
Short name T375
Test name
Test status
Simulation time 28267030104 ps
CPU time 17.51 seconds
Started Apr 28 02:46:58 PM PDT 24
Finished Apr 28 02:47:16 PM PDT 24
Peak memory 202140 kb
Host smart-bfff2ebd-6a86-4232-9921-8aa14bccebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305624461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.305624461
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.420363779
Short name T368
Test name
Test status
Simulation time 2749783883 ps
CPU time 3.33 seconds
Started Apr 28 02:46:55 PM PDT 24
Finished Apr 28 02:46:59 PM PDT 24
Peak memory 202116 kb
Host smart-badca32d-1e0f-49a3-b8d2-1b5f2c03d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420363779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.420363779
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3109876186
Short name T606
Test name
Test status
Simulation time 5888586818 ps
CPU time 13.99 seconds
Started Apr 28 02:46:50 PM PDT 24
Finished Apr 28 02:47:04 PM PDT 24
Peak memory 202096 kb
Host smart-4e4a99fc-3a79-4aae-9462-6d698745073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109876186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3109876186
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.4086589799
Short name T241
Test name
Test status
Simulation time 367555548066 ps
CPU time 439.82 seconds
Started Apr 28 02:46:59 PM PDT 24
Finished Apr 28 02:54:19 PM PDT 24
Peak memory 202312 kb
Host smart-a47f2f9b-8878-4f25-b2e2-dc0be18e68c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086589799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.4086589799
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2085421247
Short name T86
Test name
Test status
Simulation time 170386925991 ps
CPU time 95.69 seconds
Started Apr 28 02:46:56 PM PDT 24
Finished Apr 28 02:48:33 PM PDT 24
Peak memory 210616 kb
Host smart-d212827b-2f3c-41a9-a714-ed1168b65e21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085421247 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2085421247
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1665552553
Short name T483
Test name
Test status
Simulation time 525505288 ps
CPU time 1.86 seconds
Started Apr 28 02:47:13 PM PDT 24
Finished Apr 28 02:47:15 PM PDT 24
Peak memory 202020 kb
Host smart-0e0660cb-fb78-432e-840f-5d4897d27b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665552553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1665552553
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.4210385989
Short name T410
Test name
Test status
Simulation time 496589402220 ps
CPU time 559.21 seconds
Started Apr 28 02:47:03 PM PDT 24
Finished Apr 28 02:56:23 PM PDT 24
Peak memory 202288 kb
Host smart-59bc8fc9-353a-40e1-8933-61b9b506ff17
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210385989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.4210385989
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.341291291
Short name T426
Test name
Test status
Simulation time 323932589641 ps
CPU time 775.37 seconds
Started Apr 28 02:46:58 PM PDT 24
Finished Apr 28 02:59:54 PM PDT 24
Peak memory 202260 kb
Host smart-728be0c5-366b-45d7-a549-a8f29e1f1192
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=341291291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.341291291
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.808204415
Short name T140
Test name
Test status
Simulation time 527838845096 ps
CPU time 157.72 seconds
Started Apr 28 02:47:04 PM PDT 24
Finished Apr 28 02:49:42 PM PDT 24
Peak memory 202344 kb
Host smart-f65420d9-2cb6-4766-9eb6-720c7c605f60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808204415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.808204415
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4013602872
Short name T513
Test name
Test status
Simulation time 593820674883 ps
CPU time 222.42 seconds
Started Apr 28 02:47:04 PM PDT 24
Finished Apr 28 02:50:47 PM PDT 24
Peak memory 202252 kb
Host smart-5f0cc84e-1ce1-4dc8-a1e7-d6f8834b6b5d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013602872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4013602872
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2702930833
Short name T709
Test name
Test status
Simulation time 107797770414 ps
CPU time 455.63 seconds
Started Apr 28 02:47:08 PM PDT 24
Finished Apr 28 02:54:44 PM PDT 24
Peak memory 202708 kb
Host smart-9864d384-60a5-474f-9670-4d51487f3bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702930833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2702930833
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.3790873582
Short name T534
Test name
Test status
Simulation time 31120513604 ps
CPU time 17.67 seconds
Started Apr 28 02:47:10 PM PDT 24
Finished Apr 28 02:47:28 PM PDT 24
Peak memory 202104 kb
Host smart-7f441e4c-c3c5-499e-addf-b78def7d0cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790873582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.3790873582
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3100098908
Short name T667
Test name
Test status
Simulation time 4483620243 ps
CPU time 6.11 seconds
Started Apr 28 02:47:09 PM PDT 24
Finished Apr 28 02:47:16 PM PDT 24
Peak memory 202100 kb
Host smart-eb3edc5b-a588-416b-937a-2ee89b67ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100098908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3100098908
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3715164498
Short name T622
Test name
Test status
Simulation time 6042285193 ps
CPU time 4.32 seconds
Started Apr 28 02:46:57 PM PDT 24
Finished Apr 28 02:47:02 PM PDT 24
Peak memory 202160 kb
Host smart-353cd754-2ed5-4324-9c8b-67b432e28c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715164498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3715164498
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.342491122
Short name T261
Test name
Test status
Simulation time 326798743380 ps
CPU time 182.46 seconds
Started Apr 28 02:47:17 PM PDT 24
Finished Apr 28 02:50:20 PM PDT 24
Peak memory 202388 kb
Host smart-c42542df-71b0-431b-ac99-f7c058ff4591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342491122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
342491122
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2154069870
Short name T19
Test name
Test status
Simulation time 15954046741 ps
CPU time 23.69 seconds
Started Apr 28 02:47:14 PM PDT 24
Finished Apr 28 02:47:38 PM PDT 24
Peak memory 210644 kb
Host smart-92dd6c9c-954f-4380-a72a-c6378e4cd293
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154069870 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2154069870
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2602048989
Short name T592
Test name
Test status
Simulation time 490700757 ps
CPU time 1.18 seconds
Started Apr 28 02:47:24 PM PDT 24
Finished Apr 28 02:47:26 PM PDT 24
Peak memory 201968 kb
Host smart-f42e9ea7-7966-4c10-aad8-2fb225fa7f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602048989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2602048989
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3247789511
Short name T324
Test name
Test status
Simulation time 348343942711 ps
CPU time 742.14 seconds
Started Apr 28 02:47:18 PM PDT 24
Finished Apr 28 02:59:41 PM PDT 24
Peak memory 202356 kb
Host smart-e6d5b014-d2fc-474b-98ce-25a2eab88127
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247789511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3247789511
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.351254645
Short name T262
Test name
Test status
Simulation time 361255212953 ps
CPU time 409.02 seconds
Started Apr 28 02:47:21 PM PDT 24
Finished Apr 28 02:54:10 PM PDT 24
Peak memory 202304 kb
Host smart-380f467b-9d72-4500-886d-504b7eba240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351254645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.351254645
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.219479336
Short name T309
Test name
Test status
Simulation time 159166005847 ps
CPU time 332.53 seconds
Started Apr 28 02:47:19 PM PDT 24
Finished Apr 28 02:52:52 PM PDT 24
Peak memory 202284 kb
Host smart-ab573f04-3632-4f21-8516-2137c74b8246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219479336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.219479336
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2299377594
Short name T382
Test name
Test status
Simulation time 498321800647 ps
CPU time 1067.75 seconds
Started Apr 28 02:47:18 PM PDT 24
Finished Apr 28 03:05:06 PM PDT 24
Peak memory 202264 kb
Host smart-0045e5c6-5d43-4976-9a62-bd213a4b33c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299377594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2299377594
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2823697621
Short name T540
Test name
Test status
Simulation time 491556750013 ps
CPU time 1141.54 seconds
Started Apr 28 02:47:15 PM PDT 24
Finished Apr 28 03:06:18 PM PDT 24
Peak memory 202312 kb
Host smart-ae0f67b7-8bcf-4606-ab19-9a7a80466b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823697621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2823697621
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3071380496
Short name T518
Test name
Test status
Simulation time 165875155847 ps
CPU time 201.97 seconds
Started Apr 28 02:47:18 PM PDT 24
Finished Apr 28 02:50:40 PM PDT 24
Peak memory 202312 kb
Host smart-35702dc7-58ad-492c-973b-521aab62930e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071380496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3071380496
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.3166800085
Short name T297
Test name
Test status
Simulation time 253175811384 ps
CPU time 596.28 seconds
Started Apr 28 02:47:19 PM PDT 24
Finished Apr 28 02:57:16 PM PDT 24
Peak memory 202256 kb
Host smart-1ff0da29-ea05-47f1-9a09-5b082a8af091
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166800085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.3166800085
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.2684837945
Short name T449
Test name
Test status
Simulation time 607802237765 ps
CPU time 692.91 seconds
Started Apr 28 02:47:21 PM PDT 24
Finished Apr 28 02:58:54 PM PDT 24
Peak memory 202296 kb
Host smart-f6b4371f-8e64-442c-baa8-7b5936e4af9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684837945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.2684837945
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3669133263
Short name T712
Test name
Test status
Simulation time 121450645688 ps
CPU time 374.16 seconds
Started Apr 28 02:47:19 PM PDT 24
Finished Apr 28 02:53:33 PM PDT 24
Peak memory 202732 kb
Host smart-edc04058-cdd0-49e8-b612-bdf96567a8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669133263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3669133263
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3807834181
Short name T594
Test name
Test status
Simulation time 41773400280 ps
CPU time 20.15 seconds
Started Apr 28 02:47:18 PM PDT 24
Finished Apr 28 02:47:39 PM PDT 24
Peak memory 202108 kb
Host smart-692a977b-437c-455f-9d96-a1a6f4de335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807834181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3807834181
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3017088982
Short name T103
Test name
Test status
Simulation time 3511583515 ps
CPU time 2.8 seconds
Started Apr 28 02:47:19 PM PDT 24
Finished Apr 28 02:47:22 PM PDT 24
Peak memory 202136 kb
Host smart-2d9a5831-d2f4-486b-8433-57c29470e781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017088982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3017088982
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2393045891
Short name T386
Test name
Test status
Simulation time 5648343451 ps
CPU time 13.98 seconds
Started Apr 28 02:47:16 PM PDT 24
Finished Apr 28 02:47:30 PM PDT 24
Peak memory 202120 kb
Host smart-feffcaee-2b0c-47d1-ac54-a187b415f617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393045891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2393045891
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1509709144
Short name T311
Test name
Test status
Simulation time 460230587966 ps
CPU time 287.42 seconds
Started Apr 28 02:47:24 PM PDT 24
Finished Apr 28 02:52:12 PM PDT 24
Peak memory 202672 kb
Host smart-b922bef5-0525-4f52-89ad-30447f9bad13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509709144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1509709144
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1740530319
Short name T591
Test name
Test status
Simulation time 117436659742 ps
CPU time 279.44 seconds
Started Apr 28 02:47:25 PM PDT 24
Finished Apr 28 02:52:04 PM PDT 24
Peak memory 202456 kb
Host smart-d06615e1-daca-4dd0-91c8-a81bbe11ff24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740530319 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1740530319
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1646475661
Short name T392
Test name
Test status
Simulation time 384343209 ps
CPU time 0.86 seconds
Started Apr 28 02:45:37 PM PDT 24
Finished Apr 28 02:45:40 PM PDT 24
Peak memory 201988 kb
Host smart-0afd9e71-d768-45dd-bb84-0d0d5e633759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646475661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1646475661
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.580982531
Short name T244
Test name
Test status
Simulation time 341568799269 ps
CPU time 203.78 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:48:56 PM PDT 24
Peak memory 202280 kb
Host smart-4396b0fa-eb07-43a2-a295-d26412fcc111
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580982531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.580982531
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3422074244
Short name T96
Test name
Test status
Simulation time 441442514092 ps
CPU time 269.39 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:50:02 PM PDT 24
Peak memory 202276 kb
Host smart-44a70dec-b816-4e21-b81a-f2d4a2ad1ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422074244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3422074244
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1426561033
Short name T639
Test name
Test status
Simulation time 164266043407 ps
CPU time 412.91 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:52:26 PM PDT 24
Peak memory 202300 kb
Host smart-cfbcdacf-5dd4-48af-b14c-552a94340447
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426561033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1426561033
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2006167581
Short name T170
Test name
Test status
Simulation time 503358384633 ps
CPU time 220.37 seconds
Started Apr 28 02:45:32 PM PDT 24
Finished Apr 28 02:49:14 PM PDT 24
Peak memory 202292 kb
Host smart-7c12c1cc-a144-4e3f-bc34-a1851c982ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006167581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2006167581
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.285465405
Short name T457
Test name
Test status
Simulation time 494533644050 ps
CPU time 1101.44 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 03:04:02 PM PDT 24
Peak memory 202340 kb
Host smart-a64dcebb-b304-4456-b7f6-1a5806243322
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=285465405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.285465405
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2000724682
Short name T230
Test name
Test status
Simulation time 338352775909 ps
CPU time 204.03 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 02:49:04 PM PDT 24
Peak memory 202360 kb
Host smart-3e4efccb-30d9-4212-90cd-8b47b6ef6b5e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000724682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2000724682
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.264418910
Short name T419
Test name
Test status
Simulation time 199516993294 ps
CPU time 122.93 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 02:47:44 PM PDT 24
Peak memory 202280 kb
Host smart-b0ad3d31-b6a0-4b4d-988b-9d01e5911eea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264418910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.264418910
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.4229715562
Short name T415
Test name
Test status
Simulation time 107078502467 ps
CPU time 349.67 seconds
Started Apr 28 02:45:33 PM PDT 24
Finished Apr 28 02:51:23 PM PDT 24
Peak memory 202700 kb
Host smart-52adfb4c-c32e-4a1c-b022-3a14e3b28389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229715562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.4229715562
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1665718004
Short name T373
Test name
Test status
Simulation time 37278282353 ps
CPU time 39.21 seconds
Started Apr 28 02:45:29 PM PDT 24
Finished Apr 28 02:46:09 PM PDT 24
Peak memory 202132 kb
Host smart-d16c4577-a6bf-4969-87fd-1138386bca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665718004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1665718004
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2465328557
Short name T376
Test name
Test status
Simulation time 3269284776 ps
CPU time 4.67 seconds
Started Apr 28 02:45:33 PM PDT 24
Finished Apr 28 02:45:39 PM PDT 24
Peak memory 202124 kb
Host smart-2150bfbc-b2af-48c3-8563-d1ff1402c2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465328557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2465328557
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3260847166
Short name T58
Test name
Test status
Simulation time 8232339866 ps
CPU time 19.23 seconds
Started Apr 28 02:45:36 PM PDT 24
Finished Apr 28 02:45:56 PM PDT 24
Peak memory 218784 kb
Host smart-aac590fe-1af7-45ac-b3f4-6c19dda10b29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260847166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3260847166
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1303187543
Short name T717
Test name
Test status
Simulation time 6078340187 ps
CPU time 4.58 seconds
Started Apr 28 02:45:39 PM PDT 24
Finished Apr 28 02:45:45 PM PDT 24
Peak memory 201628 kb
Host smart-ee983cee-c9ff-42d3-a3b9-7738a2767eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303187543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1303187543
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.818879485
Short name T305
Test name
Test status
Simulation time 373073306857 ps
CPU time 750.29 seconds
Started Apr 28 02:45:30 PM PDT 24
Finished Apr 28 02:58:01 PM PDT 24
Peak memory 202280 kb
Host smart-d228fcd2-10e6-4ef3-95b0-e671f24a0e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818879485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.818879485
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3466461003
Short name T40
Test name
Test status
Simulation time 71749849095 ps
CPU time 361.06 seconds
Started Apr 28 02:45:31 PM PDT 24
Finished Apr 28 02:51:34 PM PDT 24
Peak memory 211004 kb
Host smart-8892f280-6ca7-42d8-a0f4-25e584471577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466461003 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3466461003
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1658006331
Short name T714
Test name
Test status
Simulation time 320529560 ps
CPU time 0.79 seconds
Started Apr 28 02:47:35 PM PDT 24
Finished Apr 28 02:47:36 PM PDT 24
Peak memory 201968 kb
Host smart-15c37956-3e36-43c9-bea4-e43570522a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658006331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1658006331
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2657832498
Short name T501
Test name
Test status
Simulation time 168910713070 ps
CPU time 108.7 seconds
Started Apr 28 02:47:32 PM PDT 24
Finished Apr 28 02:49:21 PM PDT 24
Peak memory 202316 kb
Host smart-0e5f892b-32a7-41c8-853d-af56f5b35966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657832498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2657832498
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1734164657
Short name T346
Test name
Test status
Simulation time 322957506313 ps
CPU time 695.05 seconds
Started Apr 28 02:47:24 PM PDT 24
Finished Apr 28 02:59:00 PM PDT 24
Peak memory 202188 kb
Host smart-2121b45d-5603-428c-8e36-ed15f2e1749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734164657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1734164657
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2778401369
Short name T785
Test name
Test status
Simulation time 332532612819 ps
CPU time 784.35 seconds
Started Apr 28 02:47:33 PM PDT 24
Finished Apr 28 03:00:37 PM PDT 24
Peak memory 202292 kb
Host smart-88c2687b-8788-457d-9f49-66bb81a915da
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778401369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2778401369
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3842555772
Short name T240
Test name
Test status
Simulation time 498357619834 ps
CPU time 556.37 seconds
Started Apr 28 02:47:30 PM PDT 24
Finished Apr 28 02:56:48 PM PDT 24
Peak memory 202356 kb
Host smart-385d2b53-a3a8-4fc5-9b06-93dd3a826f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842555772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3842555772
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2828251523
Short name T545
Test name
Test status
Simulation time 328385150647 ps
CPU time 202.81 seconds
Started Apr 28 02:47:24 PM PDT 24
Finished Apr 28 02:50:47 PM PDT 24
Peak memory 202308 kb
Host smart-06075bfc-2daf-4472-acc2-81490b2a3fa6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828251523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2828251523
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2053984877
Short name T705
Test name
Test status
Simulation time 193517795095 ps
CPU time 451.13 seconds
Started Apr 28 02:47:23 PM PDT 24
Finished Apr 28 02:54:55 PM PDT 24
Peak memory 202396 kb
Host smart-4098dadf-ee30-4f05-9f5a-dc56e3167c1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053984877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2053984877
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.168803084
Short name T611
Test name
Test status
Simulation time 601498929344 ps
CPU time 1456.92 seconds
Started Apr 28 02:47:30 PM PDT 24
Finished Apr 28 03:11:48 PM PDT 24
Peak memory 202256 kb
Host smart-464b9ad3-5913-492c-9fcd-20683ce7c19c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168803084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.168803084
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.896415778
Short name T195
Test name
Test status
Simulation time 110585984238 ps
CPU time 603.86 seconds
Started Apr 28 02:47:33 PM PDT 24
Finished Apr 28 02:57:38 PM PDT 24
Peak memory 202640 kb
Host smart-687cf583-49b9-4c0c-b256-b6b4060f5cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896415778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.896415778
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3043940352
Short name T424
Test name
Test status
Simulation time 27384268824 ps
CPU time 5.56 seconds
Started Apr 28 02:47:30 PM PDT 24
Finished Apr 28 02:47:37 PM PDT 24
Peak memory 202096 kb
Host smart-9efdb562-ee40-4d1e-8041-bcc6ac0a044e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043940352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3043940352
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.246240909
Short name T393
Test name
Test status
Simulation time 4428444078 ps
CPU time 2.42 seconds
Started Apr 28 02:47:30 PM PDT 24
Finished Apr 28 02:47:33 PM PDT 24
Peak memory 202152 kb
Host smart-7e67fc94-aee8-46cb-89ce-e2ce4596c0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246240909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.246240909
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3330818142
Short name T131
Test name
Test status
Simulation time 5876250889 ps
CPU time 2.18 seconds
Started Apr 28 02:47:30 PM PDT 24
Finished Apr 28 02:47:33 PM PDT 24
Peak memory 202172 kb
Host smart-1795a03b-33f0-4588-b49b-ed9b49515dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330818142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3330818142
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3957990643
Short name T80
Test name
Test status
Simulation time 169846284760 ps
CPU time 393.4 seconds
Started Apr 28 02:47:34 PM PDT 24
Finished Apr 28 02:54:08 PM PDT 24
Peak memory 202388 kb
Host smart-6d6b7219-62e5-4d00-a344-34457671dc8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957990643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3957990643
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.1032879287
Short name T620
Test name
Test status
Simulation time 490255054 ps
CPU time 1.65 seconds
Started Apr 28 02:47:51 PM PDT 24
Finished Apr 28 02:47:53 PM PDT 24
Peak memory 202004 kb
Host smart-ef2fd121-ff9a-46bb-af75-8d8519d6be8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032879287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.1032879287
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1563045945
Short name T227
Test name
Test status
Simulation time 261471752025 ps
CPU time 13.92 seconds
Started Apr 28 02:47:40 PM PDT 24
Finished Apr 28 02:47:54 PM PDT 24
Peak memory 202280 kb
Host smart-1521cfa7-2738-4b5e-91ee-cbb32edb86bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563045945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1563045945
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1112451392
Short name T325
Test name
Test status
Simulation time 540630481699 ps
CPU time 1146.17 seconds
Started Apr 28 02:47:43 PM PDT 24
Finished Apr 28 03:06:50 PM PDT 24
Peak memory 202316 kb
Host smart-b307f93a-421e-4b2f-9372-8f074c7d6f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112451392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1112451392
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3392354052
Short name T216
Test name
Test status
Simulation time 333181552468 ps
CPU time 117.85 seconds
Started Apr 28 02:47:35 PM PDT 24
Finished Apr 28 02:49:33 PM PDT 24
Peak memory 202396 kb
Host smart-8932aaa6-0a09-4be3-b083-e433c4eb86d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392354052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3392354052
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1458413203
Short name T646
Test name
Test status
Simulation time 499594234812 ps
CPU time 319.33 seconds
Started Apr 28 02:47:39 PM PDT 24
Finished Apr 28 02:52:59 PM PDT 24
Peak memory 202324 kb
Host smart-b6463f70-2000-4f37-a64e-df168434ed23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458413203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1458413203
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.103530360
Short name T641
Test name
Test status
Simulation time 162058915394 ps
CPU time 301.89 seconds
Started Apr 28 02:47:34 PM PDT 24
Finished Apr 28 02:52:37 PM PDT 24
Peak memory 202292 kb
Host smart-2206c197-04bb-4e57-b6f1-0c71de6b50fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103530360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.103530360
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3028701307
Short name T554
Test name
Test status
Simulation time 166177045038 ps
CPU time 96.34 seconds
Started Apr 28 02:47:35 PM PDT 24
Finished Apr 28 02:49:12 PM PDT 24
Peak memory 202300 kb
Host smart-1ec668d5-2661-42a5-abda-c16f0ab8ae37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028701307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3028701307
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3942355065
Short name T332
Test name
Test status
Simulation time 606110897685 ps
CPU time 1236.56 seconds
Started Apr 28 02:47:39 PM PDT 24
Finished Apr 28 03:08:16 PM PDT 24
Peak memory 202320 kb
Host smart-9303561d-e232-4bb1-aaa7-839c970ee05e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942355065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3942355065
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.247049300
Short name T521
Test name
Test status
Simulation time 608592615784 ps
CPU time 690.15 seconds
Started Apr 28 02:47:40 PM PDT 24
Finished Apr 28 02:59:10 PM PDT 24
Peak memory 202216 kb
Host smart-f5f4c57c-a37f-43b8-93d5-331270f2a5cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247049300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.247049300
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.119801995
Short name T461
Test name
Test status
Simulation time 26164562663 ps
CPU time 56.91 seconds
Started Apr 28 02:47:45 PM PDT 24
Finished Apr 28 02:48:42 PM PDT 24
Peak memory 202132 kb
Host smart-fa1f1720-75ba-49f6-bb47-930ae1ec47d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119801995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.119801995
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.4117593859
Short name T736
Test name
Test status
Simulation time 5398663845 ps
CPU time 8.38 seconds
Started Apr 28 02:47:46 PM PDT 24
Finished Apr 28 02:47:54 PM PDT 24
Peak memory 202120 kb
Host smart-c4b331fb-4245-4f46-aa9b-24fe908b74bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117593859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.4117593859
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1973465468
Short name T468
Test name
Test status
Simulation time 5527205018 ps
CPU time 3.87 seconds
Started Apr 28 02:47:34 PM PDT 24
Finished Apr 28 02:47:38 PM PDT 24
Peak memory 202136 kb
Host smart-3e4390ec-8021-41d9-8d0f-15f730631066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973465468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1973465468
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1897724460
Short name T337
Test name
Test status
Simulation time 172684383021 ps
CPU time 96.72 seconds
Started Apr 28 02:47:49 PM PDT 24
Finished Apr 28 02:49:26 PM PDT 24
Peak memory 202264 kb
Host smart-b84bbfa4-b043-443b-8c87-b44757cccf43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897724460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1897724460
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3446104081
Short name T88
Test name
Test status
Simulation time 92615887427 ps
CPU time 73.8 seconds
Started Apr 28 02:47:50 PM PDT 24
Finished Apr 28 02:49:04 PM PDT 24
Peak memory 210728 kb
Host smart-13b2e199-1424-43aa-9275-6bdb448ef42d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446104081 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3446104081
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2728038185
Short name T404
Test name
Test status
Simulation time 384530854 ps
CPU time 0.8 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 02:48:13 PM PDT 24
Peak memory 201972 kb
Host smart-05d9c7d9-e092-401b-b126-62360d04baf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728038185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2728038185
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1344896278
Short name T175
Test name
Test status
Simulation time 509426996510 ps
CPU time 212.67 seconds
Started Apr 28 02:47:56 PM PDT 24
Finished Apr 28 02:51:30 PM PDT 24
Peak memory 202280 kb
Host smart-ee9bfcb8-8a19-43df-b487-4882d6f7f6a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344896278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1344896278
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.4201926315
Short name T139
Test name
Test status
Simulation time 167817856962 ps
CPU time 376.26 seconds
Started Apr 28 02:48:12 PM PDT 24
Finished Apr 28 02:54:30 PM PDT 24
Peak memory 202280 kb
Host smart-fda322aa-06ad-4199-9448-cef49429584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201926315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.4201926315
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.412690428
Short name T29
Test name
Test status
Simulation time 493158524933 ps
CPU time 348.91 seconds
Started Apr 28 02:47:58 PM PDT 24
Finished Apr 28 02:53:48 PM PDT 24
Peak memory 202256 kb
Host smart-103825d2-7d07-4e35-bbe0-af39d443a3e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412690428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.412690428
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2197002091
Short name T799
Test name
Test status
Simulation time 488839639553 ps
CPU time 590.12 seconds
Started Apr 28 02:47:50 PM PDT 24
Finished Apr 28 02:57:41 PM PDT 24
Peak memory 202352 kb
Host smart-fc4b2d60-b933-468c-9fd9-e87bf88d8335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197002091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2197002091
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1821000425
Short name T454
Test name
Test status
Simulation time 496256590929 ps
CPU time 121.66 seconds
Started Apr 28 02:47:50 PM PDT 24
Finished Apr 28 02:49:53 PM PDT 24
Peak memory 202388 kb
Host smart-37b60ff9-dd38-4dd5-852e-2e6dcccf91a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821000425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1821000425
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3443461705
Short name T318
Test name
Test status
Simulation time 358193494134 ps
CPU time 824.28 seconds
Started Apr 28 02:47:58 PM PDT 24
Finished Apr 28 03:01:43 PM PDT 24
Peak memory 202332 kb
Host smart-12e759f6-4f38-47f2-b95f-0589c8695981
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443461705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3443461705
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3034290331
Short name T406
Test name
Test status
Simulation time 100288406937 ps
CPU time 389.12 seconds
Started Apr 28 02:48:12 PM PDT 24
Finished Apr 28 02:54:43 PM PDT 24
Peak memory 202708 kb
Host smart-3a2f56b7-8f16-41ae-b8a1-80b6cca0132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034290331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3034290331
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1828706861
Short name T446
Test name
Test status
Simulation time 42324884798 ps
CPU time 92.13 seconds
Started Apr 28 02:48:04 PM PDT 24
Finished Apr 28 02:49:36 PM PDT 24
Peak memory 202156 kb
Host smart-b8ba3e86-e719-4781-9b66-55c4d5400254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828706861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1828706861
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3410077900
Short name T730
Test name
Test status
Simulation time 4817982381 ps
CPU time 11.99 seconds
Started Apr 28 02:48:05 PM PDT 24
Finished Apr 28 02:48:18 PM PDT 24
Peak memory 202128 kb
Host smart-d5384935-786e-414a-bfea-cbf494671c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410077900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3410077900
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2637652431
Short name T555
Test name
Test status
Simulation time 5740166548 ps
CPU time 15.18 seconds
Started Apr 28 02:47:51 PM PDT 24
Finished Apr 28 02:48:06 PM PDT 24
Peak memory 202104 kb
Host smart-5385ac46-7047-4386-8287-a86accbbfc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637652431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2637652431
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1414096389
Short name T582
Test name
Test status
Simulation time 234812785457 ps
CPU time 521.63 seconds
Started Apr 28 02:48:05 PM PDT 24
Finished Apr 28 02:56:47 PM PDT 24
Peak memory 202352 kb
Host smart-34a46074-1c86-41fd-ad64-f44c30b6c513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414096389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1414096389
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2933856904
Short name T39
Test name
Test status
Simulation time 187305819731 ps
CPU time 409.22 seconds
Started Apr 28 02:48:05 PM PDT 24
Finished Apr 28 02:54:54 PM PDT 24
Peak memory 211068 kb
Host smart-6a702b11-3d0a-46f9-ac07-6fc9942b9136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933856904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2933856904
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.710803762
Short name T383
Test name
Test status
Simulation time 428037676 ps
CPU time 1.55 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 02:48:14 PM PDT 24
Peak memory 201976 kb
Host smart-36078e8c-068d-413e-bc92-656096d1ecb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710803762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.710803762
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.375001742
Short name T234
Test name
Test status
Simulation time 504283576857 ps
CPU time 1064.68 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 03:05:58 PM PDT 24
Peak memory 202364 kb
Host smart-5214157b-6ebf-415d-b641-e9656fdd84f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375001742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gati
ng.375001742
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.519630305
Short name T252
Test name
Test status
Simulation time 365540008599 ps
CPU time 865.72 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 03:02:38 PM PDT 24
Peak memory 202300 kb
Host smart-40ba0ffb-2647-4509-a168-e3394989099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519630305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.519630305
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.583842761
Short name T242
Test name
Test status
Simulation time 334838598301 ps
CPU time 803.34 seconds
Started Apr 28 02:48:06 PM PDT 24
Finished Apr 28 03:01:30 PM PDT 24
Peak memory 202252 kb
Host smart-9d61e179-1bf4-4689-a52e-27089eb9105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583842761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.583842761
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3858968151
Short name T619
Test name
Test status
Simulation time 328601067990 ps
CPU time 197.98 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 02:51:30 PM PDT 24
Peak memory 202268 kb
Host smart-199b28ad-b779-43e2-806f-86e1c48373e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858968151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3858968151
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1620542589
Short name T134
Test name
Test status
Simulation time 489530277604 ps
CPU time 321.57 seconds
Started Apr 28 02:48:05 PM PDT 24
Finished Apr 28 02:53:27 PM PDT 24
Peak memory 202388 kb
Host smart-e806b5cb-97b7-488b-a016-21c87ea0556e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620542589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1620542589
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1932985315
Short name T471
Test name
Test status
Simulation time 163544168405 ps
CPU time 362.74 seconds
Started Apr 28 02:48:05 PM PDT 24
Finished Apr 28 02:54:09 PM PDT 24
Peak memory 202376 kb
Host smart-98bceccd-3114-4508-8784-cf5c49b8b239
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932985315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1932985315
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3493087389
Short name T465
Test name
Test status
Simulation time 189807665694 ps
CPU time 117.2 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 02:50:09 PM PDT 24
Peak memory 202320 kb
Host smart-57f148d2-89e2-4d4e-a1ed-79bd2b7ae4a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493087389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3493087389
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2179618925
Short name T696
Test name
Test status
Simulation time 613764654330 ps
CPU time 144.63 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 02:50:36 PM PDT 24
Peak memory 202248 kb
Host smart-4896c693-753e-42db-9e50-6bd206ca09ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179618925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2179618925
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.340355322
Short name T355
Test name
Test status
Simulation time 97840644211 ps
CPU time 357.03 seconds
Started Apr 28 02:48:10 PM PDT 24
Finished Apr 28 02:54:08 PM PDT 24
Peak memory 202736 kb
Host smart-69b81d17-2fc3-4612-a49a-62a37e981657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340355322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.340355322
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.4181289587
Short name T492
Test name
Test status
Simulation time 44093862763 ps
CPU time 25.18 seconds
Started Apr 28 02:48:12 PM PDT 24
Finished Apr 28 02:48:38 PM PDT 24
Peak memory 202128 kb
Host smart-6537da61-bd2e-43e5-bb61-e62f7aa60706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181289587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.4181289587
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1010046403
Short name T647
Test name
Test status
Simulation time 4201508448 ps
CPU time 2.59 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 02:48:15 PM PDT 24
Peak memory 202140 kb
Host smart-380b627c-83e3-4b19-9747-bc23695bc277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010046403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1010046403
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1462852851
Short name T476
Test name
Test status
Simulation time 5743254614 ps
CPU time 7.02 seconds
Started Apr 28 02:48:05 PM PDT 24
Finished Apr 28 02:48:13 PM PDT 24
Peak memory 202124 kb
Host smart-f84e33f5-e76b-4adb-8160-bb161062a1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462852851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1462852851
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2625751032
Short name T237
Test name
Test status
Simulation time 314869106123 ps
CPU time 575.62 seconds
Started Apr 28 02:48:14 PM PDT 24
Finished Apr 28 02:57:51 PM PDT 24
Peak memory 219020 kb
Host smart-d0289365-9b2a-4caf-a120-1651fc52cc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625751032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2625751032
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3990020050
Short name T42
Test name
Test status
Simulation time 144146605088 ps
CPU time 149.17 seconds
Started Apr 28 02:48:12 PM PDT 24
Finished Apr 28 02:50:42 PM PDT 24
Peak memory 210916 kb
Host smart-fc4831dc-c66d-4ca5-9f64-59e1fa53d294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990020050 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3990020050
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.304534361
Short name T638
Test name
Test status
Simulation time 501185806 ps
CPU time 1.2 seconds
Started Apr 28 02:48:27 PM PDT 24
Finished Apr 28 02:48:29 PM PDT 24
Peak memory 201960 kb
Host smart-ed18e040-ce4c-44dc-9490-db8d00da7d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304534361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.304534361
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3692419371
Short name T610
Test name
Test status
Simulation time 190798624105 ps
CPU time 217.46 seconds
Started Apr 28 02:48:17 PM PDT 24
Finished Apr 28 02:51:55 PM PDT 24
Peak memory 202316 kb
Host smart-f1e6ad82-c899-453a-a8fb-7cbaa291bd16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692419371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3692419371
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1376226440
Short name T254
Test name
Test status
Simulation time 165081238555 ps
CPU time 52.79 seconds
Started Apr 28 02:48:22 PM PDT 24
Finished Apr 28 02:49:15 PM PDT 24
Peak memory 202288 kb
Host smart-276ebbf4-705d-4c3e-837c-663785486f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376226440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1376226440
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3239141015
Short name T138
Test name
Test status
Simulation time 335656507365 ps
CPU time 831.04 seconds
Started Apr 28 02:48:11 PM PDT 24
Finished Apr 28 03:02:04 PM PDT 24
Peak memory 202352 kb
Host smart-2204f758-196d-4017-8d03-3101118923be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239141015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3239141015
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2815986414
Short name T692
Test name
Test status
Simulation time 494723120053 ps
CPU time 1143.81 seconds
Started Apr 28 02:48:12 PM PDT 24
Finished Apr 28 03:07:18 PM PDT 24
Peak memory 202272 kb
Host smart-3f0680df-8a9d-473f-a434-f543d3cb75ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815986414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2815986414
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1388927029
Short name T778
Test name
Test status
Simulation time 495921918471 ps
CPU time 1210.79 seconds
Started Apr 28 02:48:12 PM PDT 24
Finished Apr 28 03:08:24 PM PDT 24
Peak memory 202296 kb
Host smart-db48c0a5-3924-4284-ba52-b68f6c891d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388927029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1388927029
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2330936148
Short name T787
Test name
Test status
Simulation time 493451247116 ps
CPU time 138.04 seconds
Started Apr 28 02:48:10 PM PDT 24
Finished Apr 28 02:50:29 PM PDT 24
Peak memory 202324 kb
Host smart-6e5906be-a91f-4c71-be79-de5f88a82203
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330936148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2330936148
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.387306808
Short name T569
Test name
Test status
Simulation time 392641281232 ps
CPU time 200.21 seconds
Started Apr 28 02:48:17 PM PDT 24
Finished Apr 28 02:51:38 PM PDT 24
Peak memory 202396 kb
Host smart-8b5c0ace-84f1-4982-81fc-369b2ce18446
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387306808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.387306808
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.507561585
Short name T100
Test name
Test status
Simulation time 625900434084 ps
CPU time 1243.83 seconds
Started Apr 28 02:48:17 PM PDT 24
Finished Apr 28 03:09:01 PM PDT 24
Peak memory 202356 kb
Host smart-21d69c8c-5bcc-4f50-a96f-8dea1d7c1119
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507561585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.507561585
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1973926496
Short name T603
Test name
Test status
Simulation time 98797265756 ps
CPU time 299.43 seconds
Started Apr 28 02:48:21 PM PDT 24
Finished Apr 28 02:53:21 PM PDT 24
Peak memory 202680 kb
Host smart-6758607e-76aa-445b-9cc2-223834268d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973926496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1973926496
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2987763608
Short name T462
Test name
Test status
Simulation time 43311116669 ps
CPU time 5.55 seconds
Started Apr 28 02:48:21 PM PDT 24
Finished Apr 28 02:48:27 PM PDT 24
Peak memory 202136 kb
Host smart-67f8d990-02f9-4a9f-8e89-125a64332725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987763608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2987763608
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2746568139
Short name T581
Test name
Test status
Simulation time 5109249636 ps
CPU time 7 seconds
Started Apr 28 02:48:22 PM PDT 24
Finished Apr 28 02:48:29 PM PDT 24
Peak memory 202108 kb
Host smart-bdb85a92-1707-44f3-9703-1a91840c0113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746568139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2746568139
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1766625338
Short name T780
Test name
Test status
Simulation time 5553910956 ps
CPU time 6.6 seconds
Started Apr 28 02:48:12 PM PDT 24
Finished Apr 28 02:48:20 PM PDT 24
Peak memory 202092 kb
Host smart-a6a9b0fe-9358-4447-ac89-f27a87f559fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766625338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1766625338
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.723542344
Short name T47
Test name
Test status
Simulation time 534389656727 ps
CPU time 936.63 seconds
Started Apr 28 02:48:22 PM PDT 24
Finished Apr 28 03:04:00 PM PDT 24
Peak memory 210948 kb
Host smart-f3353900-9c9e-4d61-82d4-2ce943f0fd3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723542344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
723542344
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1345109868
Short name T551
Test name
Test status
Simulation time 608588781 ps
CPU time 0.69 seconds
Started Apr 28 02:48:43 PM PDT 24
Finished Apr 28 02:48:44 PM PDT 24
Peak memory 202000 kb
Host smart-fd0a25eb-6462-4a03-a40b-392e89a5dbb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345109868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1345109868
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3818496251
Short name T268
Test name
Test status
Simulation time 339127610209 ps
CPU time 183.41 seconds
Started Apr 28 02:48:28 PM PDT 24
Finished Apr 28 02:51:32 PM PDT 24
Peak memory 202376 kb
Host smart-bd5c8299-ee16-4019-aa84-b1fdf79d6d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818496251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3818496251
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.95674769
Short name T684
Test name
Test status
Simulation time 160453545708 ps
CPU time 49.75 seconds
Started Apr 28 02:48:28 PM PDT 24
Finished Apr 28 02:49:18 PM PDT 24
Peak memory 202308 kb
Host smart-37743561-d4a3-4dac-b24d-34b4f4516c7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=95674769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt
_fixed.95674769
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.321734054
Short name T340
Test name
Test status
Simulation time 159707878452 ps
CPU time 385.09 seconds
Started Apr 28 02:48:25 PM PDT 24
Finished Apr 28 02:54:51 PM PDT 24
Peak memory 202396 kb
Host smart-147f2ad3-b503-4449-8bf5-585ae8b2f32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321734054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.321734054
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.238804628
Short name T568
Test name
Test status
Simulation time 158864851339 ps
CPU time 86.74 seconds
Started Apr 28 02:48:26 PM PDT 24
Finished Apr 28 02:49:53 PM PDT 24
Peak memory 202332 kb
Host smart-3d3dee7f-d0c4-45da-9879-0186aecc7179
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=238804628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.238804628
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3256901822
Short name T719
Test name
Test status
Simulation time 666012479904 ps
CPU time 1419.83 seconds
Started Apr 28 02:48:27 PM PDT 24
Finished Apr 28 03:12:07 PM PDT 24
Peak memory 202228 kb
Host smart-390d0708-090a-4f23-aa9c-38d4a541ad30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256901822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3256901822
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2133706781
Short name T738
Test name
Test status
Simulation time 196003443607 ps
CPU time 466.33 seconds
Started Apr 28 02:48:33 PM PDT 24
Finished Apr 28 02:56:20 PM PDT 24
Peak memory 202280 kb
Host smart-4546b4f3-ae41-4597-b1e9-508631570c6b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133706781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2133706781
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1327984051
Short name T687
Test name
Test status
Simulation time 76161533069 ps
CPU time 298.67 seconds
Started Apr 28 02:48:38 PM PDT 24
Finished Apr 28 02:53:38 PM PDT 24
Peak memory 202704 kb
Host smart-60c5a4f5-8c0d-4e1e-9629-86efca703dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327984051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1327984051
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1843977921
Short name T549
Test name
Test status
Simulation time 25936055900 ps
CPU time 51.29 seconds
Started Apr 28 02:48:38 PM PDT 24
Finished Apr 28 02:49:30 PM PDT 24
Peak memory 202116 kb
Host smart-5abe2bd9-1de2-4f59-8d53-2e20ba02640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843977921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1843977921
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.4161517574
Short name T635
Test name
Test status
Simulation time 4743313791 ps
CPU time 8.11 seconds
Started Apr 28 02:48:38 PM PDT 24
Finished Apr 28 02:48:46 PM PDT 24
Peak memory 202132 kb
Host smart-c0b648ed-1249-4cef-91f9-0f54b18bfd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161517574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.4161517574
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.805702875
Short name T572
Test name
Test status
Simulation time 5744066775 ps
CPU time 14.06 seconds
Started Apr 28 02:48:27 PM PDT 24
Finished Apr 28 02:48:42 PM PDT 24
Peak memory 202132 kb
Host smart-54e0ba02-8ce2-41b1-86db-43578a648602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805702875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.805702875
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3787696178
Short name T291
Test name
Test status
Simulation time 161954956612 ps
CPU time 363.59 seconds
Started Apr 28 02:48:43 PM PDT 24
Finished Apr 28 02:54:47 PM PDT 24
Peak memory 202288 kb
Host smart-734587d7-0255-4613-a549-39d5017da62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787696178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3787696178
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2228909868
Short name T765
Test name
Test status
Simulation time 65911581698 ps
CPU time 154.94 seconds
Started Apr 28 02:48:44 PM PDT 24
Finished Apr 28 02:51:19 PM PDT 24
Peak memory 219064 kb
Host smart-d21cfb6d-202e-4b0c-8eeb-1e38ad4d9be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228909868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2228909868
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3936776813
Short name T497
Test name
Test status
Simulation time 403148898 ps
CPU time 1.07 seconds
Started Apr 28 02:48:57 PM PDT 24
Finished Apr 28 02:48:58 PM PDT 24
Peak memory 202008 kb
Host smart-327271f7-4e2f-47da-a946-38a815f5bcc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936776813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3936776813
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2452812064
Short name T91
Test name
Test status
Simulation time 328128329671 ps
CPU time 201.13 seconds
Started Apr 28 02:48:49 PM PDT 24
Finished Apr 28 02:52:11 PM PDT 24
Peak memory 202252 kb
Host smart-d5c3cc8a-108a-4024-809d-dc08486a241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452812064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2452812064
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.516986600
Short name T715
Test name
Test status
Simulation time 162851311784 ps
CPU time 391.34 seconds
Started Apr 28 02:48:49 PM PDT 24
Finished Apr 28 02:55:21 PM PDT 24
Peak memory 202220 kb
Host smart-979fbaea-7012-48b2-a1d7-8bb8dde6d654
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=516986600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.516986600
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2144623879
Short name T205
Test name
Test status
Simulation time 504700015957 ps
CPU time 631.62 seconds
Started Apr 28 02:48:49 PM PDT 24
Finished Apr 28 02:59:21 PM PDT 24
Peak memory 202276 kb
Host smart-75ebf58e-d0cd-4aa8-989b-aed9c6619d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144623879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2144623879
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2363281680
Short name T749
Test name
Test status
Simulation time 320928724038 ps
CPU time 389.51 seconds
Started Apr 28 02:48:47 PM PDT 24
Finished Apr 28 02:55:17 PM PDT 24
Peak memory 202272 kb
Host smart-48153f36-6ea0-46c9-a0d2-ace051c23456
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363281680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2363281680
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2353263005
Short name T207
Test name
Test status
Simulation time 570838762481 ps
CPU time 333.17 seconds
Started Apr 28 02:48:49 PM PDT 24
Finished Apr 28 02:54:22 PM PDT 24
Peak memory 202308 kb
Host smart-20d0428b-4eb5-4440-bae1-c89073afda0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353263005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2353263005
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.428475560
Short name T5
Test name
Test status
Simulation time 595301371683 ps
CPU time 1304.56 seconds
Started Apr 28 02:48:48 PM PDT 24
Finished Apr 28 03:10:33 PM PDT 24
Peak memory 202300 kb
Host smart-b7441efd-11ec-4e7c-b867-bb61868217ca
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428475560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.428475560
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1033359507
Short name T734
Test name
Test status
Simulation time 70866586655 ps
CPU time 220.84 seconds
Started Apr 28 02:48:52 PM PDT 24
Finished Apr 28 02:52:33 PM PDT 24
Peak memory 202716 kb
Host smart-eebcbb39-43a0-437d-bba9-c6b42d175f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033359507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1033359507
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.216527545
Short name T178
Test name
Test status
Simulation time 36628577192 ps
CPU time 40.18 seconds
Started Apr 28 02:48:53 PM PDT 24
Finished Apr 28 02:49:34 PM PDT 24
Peak memory 202124 kb
Host smart-95e961b7-e688-4a7a-8b77-88bf96434edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216527545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.216527545
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3996863181
Short name T9
Test name
Test status
Simulation time 4960730069 ps
CPU time 14.01 seconds
Started Apr 28 02:48:53 PM PDT 24
Finished Apr 28 02:49:07 PM PDT 24
Peak memory 202128 kb
Host smart-21abe57e-c627-4c25-8a37-1b9258a6b172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996863181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3996863181
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.3300080781
Short name T744
Test name
Test status
Simulation time 5863788330 ps
CPU time 4.12 seconds
Started Apr 28 02:48:48 PM PDT 24
Finished Apr 28 02:48:53 PM PDT 24
Peak memory 202124 kb
Host smart-827bcce1-0e00-41e9-869f-ba8499f6664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300080781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.3300080781
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3629478626
Short name T508
Test name
Test status
Simulation time 1039129884769 ps
CPU time 362.31 seconds
Started Apr 28 02:49:00 PM PDT 24
Finished Apr 28 02:55:03 PM PDT 24
Peak memory 211220 kb
Host smart-862b105e-7dc8-4236-8545-a6456009f6d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629478626 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3629478626
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.4092789851
Short name T587
Test name
Test status
Simulation time 519595627 ps
CPU time 0.88 seconds
Started Apr 28 02:49:14 PM PDT 24
Finished Apr 28 02:49:15 PM PDT 24
Peak memory 202020 kb
Host smart-83bc3f1e-cde5-49bf-b73c-f75ca8e966e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092789851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4092789851
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3736562735
Short name T171
Test name
Test status
Simulation time 185473214569 ps
CPU time 219.7 seconds
Started Apr 28 02:49:09 PM PDT 24
Finished Apr 28 02:52:49 PM PDT 24
Peak memory 202372 kb
Host smart-8980088c-39fc-4ea0-b7e6-1e357fcdb507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736562735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3736562735
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2949881034
Short name T176
Test name
Test status
Simulation time 333728874770 ps
CPU time 179.8 seconds
Started Apr 28 02:49:03 PM PDT 24
Finished Apr 28 02:52:03 PM PDT 24
Peak memory 202264 kb
Host smart-de29945d-daa6-4e81-a532-4968d853496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949881034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2949881034
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2509029952
Short name T754
Test name
Test status
Simulation time 488337268659 ps
CPU time 328.98 seconds
Started Apr 28 02:49:05 PM PDT 24
Finished Apr 28 02:54:34 PM PDT 24
Peak memory 202276 kb
Host smart-acdcb3a2-fc0c-4f51-8e01-a5ea4191c58a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509029952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2509029952
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.815600709
Short name T272
Test name
Test status
Simulation time 500771482642 ps
CPU time 293.62 seconds
Started Apr 28 02:49:03 PM PDT 24
Finished Apr 28 02:53:57 PM PDT 24
Peak memory 202384 kb
Host smart-769b4e44-977b-4410-a1b3-22f66f95f043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815600709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.815600709
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.601511963
Short name T541
Test name
Test status
Simulation time 165651959838 ps
CPU time 97.27 seconds
Started Apr 28 02:49:05 PM PDT 24
Finished Apr 28 02:50:42 PM PDT 24
Peak memory 202360 kb
Host smart-58bcf330-614f-4234-8470-34ac897c424d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=601511963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.601511963
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.4213940942
Short name T543
Test name
Test status
Simulation time 595840559752 ps
CPU time 740.82 seconds
Started Apr 28 02:49:04 PM PDT 24
Finished Apr 28 03:01:26 PM PDT 24
Peak memory 202320 kb
Host smart-07daf9b8-9c5f-4a5e-8dc6-4d535e9b2fc9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213940942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.4213940942
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3542162408
Short name T630
Test name
Test status
Simulation time 59788286974 ps
CPU time 273.15 seconds
Started Apr 28 02:49:09 PM PDT 24
Finished Apr 28 02:53:42 PM PDT 24
Peak memory 202540 kb
Host smart-af7ce7cb-cec2-465a-a284-017e13164bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542162408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3542162408
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3581312748
Short name T450
Test name
Test status
Simulation time 41336687920 ps
CPU time 6.92 seconds
Started Apr 28 02:49:09 PM PDT 24
Finished Apr 28 02:49:16 PM PDT 24
Peak memory 202144 kb
Host smart-51951eef-9d60-4829-ac08-55c5695b205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581312748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3581312748
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.24005366
Short name T132
Test name
Test status
Simulation time 4139686704 ps
CPU time 10.48 seconds
Started Apr 28 02:49:08 PM PDT 24
Finished Apr 28 02:49:19 PM PDT 24
Peak memory 202092 kb
Host smart-772e6ebb-35af-4407-b367-fd36df10986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24005366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.24005366
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1263418023
Short name T742
Test name
Test status
Simulation time 6044260382 ps
CPU time 8.04 seconds
Started Apr 28 02:49:05 PM PDT 24
Finished Apr 28 02:49:14 PM PDT 24
Peak memory 202124 kb
Host smart-d0e4359f-a33e-4928-90f3-2ce9f33ef826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263418023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1263418023
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.979851206
Short name T722
Test name
Test status
Simulation time 177769221033 ps
CPU time 202.84 seconds
Started Apr 28 02:49:16 PM PDT 24
Finished Apr 28 02:52:40 PM PDT 24
Peak memory 202392 kb
Host smart-be902717-1d5a-4fba-9ed2-eafe0d97d3bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979851206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
979851206
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3013369727
Short name T339
Test name
Test status
Simulation time 357427668691 ps
CPU time 196.24 seconds
Started Apr 28 02:49:15 PM PDT 24
Finished Apr 28 02:52:32 PM PDT 24
Peak memory 210700 kb
Host smart-944bd9f6-56ac-4053-a68f-1cf6caed3d15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013369727 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3013369727
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.374940615
Short name T417
Test name
Test status
Simulation time 517270125 ps
CPU time 0.97 seconds
Started Apr 28 02:49:35 PM PDT 24
Finished Apr 28 02:49:36 PM PDT 24
Peak memory 201984 kb
Host smart-2c0b9202-2129-45a5-b403-a29d8a31ef6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374940615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.374940615
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3087447294
Short name T701
Test name
Test status
Simulation time 168046766949 ps
CPU time 377.67 seconds
Started Apr 28 02:49:25 PM PDT 24
Finished Apr 28 02:55:43 PM PDT 24
Peak memory 202288 kb
Host smart-0d4d31e9-df30-41b0-b177-de06130a73dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087447294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3087447294
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1373567608
Short name T190
Test name
Test status
Simulation time 327748659560 ps
CPU time 49.4 seconds
Started Apr 28 02:49:25 PM PDT 24
Finished Apr 28 02:50:15 PM PDT 24
Peak memory 202316 kb
Host smart-c4bfa6be-de72-4080-bbd6-c4779a4a018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373567608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1373567608
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3401405801
Short name T169
Test name
Test status
Simulation time 497657025427 ps
CPU time 931.25 seconds
Started Apr 28 02:49:21 PM PDT 24
Finished Apr 28 03:04:53 PM PDT 24
Peak memory 202304 kb
Host smart-530ff713-f51c-4015-a421-c53bc38ee4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401405801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3401405801
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.913847817
Short name T433
Test name
Test status
Simulation time 497913483721 ps
CPU time 418.94 seconds
Started Apr 28 02:49:22 PM PDT 24
Finished Apr 28 02:56:22 PM PDT 24
Peak memory 202296 kb
Host smart-492e7ca6-b18f-47be-9d1d-4a51fe79b6d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=913847817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.913847817
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.910767780
Short name T141
Test name
Test status
Simulation time 497245712166 ps
CPU time 1182.79 seconds
Started Apr 28 02:49:20 PM PDT 24
Finished Apr 28 03:09:04 PM PDT 24
Peak memory 202404 kb
Host smart-4a545d9a-74bd-48c3-905c-1202e0c8363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910767780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.910767780
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1867947526
Short name T651
Test name
Test status
Simulation time 491171342074 ps
CPU time 560.57 seconds
Started Apr 28 02:49:20 PM PDT 24
Finished Apr 28 02:58:41 PM PDT 24
Peak memory 202252 kb
Host smart-ac255a68-7b42-4023-b521-1db26460c36d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867947526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1867947526
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2832155123
Short name T623
Test name
Test status
Simulation time 579629662419 ps
CPU time 1358.15 seconds
Started Apr 28 02:49:25 PM PDT 24
Finished Apr 28 03:12:03 PM PDT 24
Peak memory 202316 kb
Host smart-c7db182e-d33a-43b5-973a-b19beba0d719
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832155123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2832155123
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3887444779
Short name T607
Test name
Test status
Simulation time 399760937683 ps
CPU time 245.13 seconds
Started Apr 28 02:49:26 PM PDT 24
Finished Apr 28 02:53:32 PM PDT 24
Peak memory 202324 kb
Host smart-b17ee214-4911-49e3-a2a0-37d30b13bb9e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887444779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3887444779
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3286373242
Short name T627
Test name
Test status
Simulation time 37957673032 ps
CPU time 79.76 seconds
Started Apr 28 02:49:30 PM PDT 24
Finished Apr 28 02:50:51 PM PDT 24
Peak memory 202112 kb
Host smart-4e401115-b189-44e9-9ac2-ce6e99194bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286373242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3286373242
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.136924258
Short name T739
Test name
Test status
Simulation time 5021630041 ps
CPU time 11.71 seconds
Started Apr 28 02:49:26 PM PDT 24
Finished Apr 28 02:49:38 PM PDT 24
Peak memory 202148 kb
Host smart-4913f59b-794b-4e17-8e92-7ee68f91cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136924258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.136924258
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2953721941
Short name T391
Test name
Test status
Simulation time 5979015285 ps
CPU time 13.41 seconds
Started Apr 28 02:49:15 PM PDT 24
Finished Apr 28 02:49:29 PM PDT 24
Peak memory 202056 kb
Host smart-e3103bde-dcbf-453e-a247-1d93a6772ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953721941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2953721941
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.247573969
Short name T747
Test name
Test status
Simulation time 532391089539 ps
CPU time 334.22 seconds
Started Apr 28 02:49:31 PM PDT 24
Finished Apr 28 02:55:05 PM PDT 24
Peak memory 202256 kb
Host smart-8a2471f2-bf5f-4981-8302-86ab8ebe3de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247573969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.
247573969
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.3063363576
Short name T37
Test name
Test status
Simulation time 26726699817 ps
CPU time 79.54 seconds
Started Apr 28 02:49:31 PM PDT 24
Finished Apr 28 02:50:51 PM PDT 24
Peak memory 210940 kb
Host smart-d7faf289-31fa-4be0-a19e-103519e4441a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063363576 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.3063363576
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4004570378
Short name T723
Test name
Test status
Simulation time 519347872 ps
CPU time 1.74 seconds
Started Apr 28 02:49:46 PM PDT 24
Finished Apr 28 02:49:48 PM PDT 24
Peak memory 201996 kb
Host smart-d0a9067b-cf22-435d-8ed6-f75f1814a320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004570378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4004570378
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3130592729
Short name T793
Test name
Test status
Simulation time 524669721247 ps
CPU time 1233.56 seconds
Started Apr 28 02:49:47 PM PDT 24
Finished Apr 28 03:10:22 PM PDT 24
Peak memory 202340 kb
Host smart-2e8610e4-2a3e-45d1-a653-a96d6f6ea289
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130592729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3130592729
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3530042161
Short name T223
Test name
Test status
Simulation time 161645201754 ps
CPU time 346.54 seconds
Started Apr 28 02:49:46 PM PDT 24
Finished Apr 28 02:55:34 PM PDT 24
Peak memory 202416 kb
Host smart-28b0cc7d-3b83-4d8a-aff7-579d90a49247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530042161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3530042161
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3418566855
Short name T510
Test name
Test status
Simulation time 169652073039 ps
CPU time 207.23 seconds
Started Apr 28 02:49:40 PM PDT 24
Finished Apr 28 02:53:08 PM PDT 24
Peak memory 202288 kb
Host smart-f053f71a-52a3-4827-bcdf-bcea802a9fa5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418566855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3418566855
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.1797727339
Short name T333
Test name
Test status
Simulation time 320747607672 ps
CPU time 376.01 seconds
Started Apr 28 02:49:37 PM PDT 24
Finished Apr 28 02:55:54 PM PDT 24
Peak memory 202380 kb
Host smart-bd0f4a6f-5a8e-44c4-846f-f06f011596ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797727339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.1797727339
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.1638364601
Short name T166
Test name
Test status
Simulation time 170105898738 ps
CPU time 49.15 seconds
Started Apr 28 02:49:36 PM PDT 24
Finished Apr 28 02:50:26 PM PDT 24
Peak memory 202304 kb
Host smart-ad7c9cc5-d1ce-4a01-8766-13ee5855af05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638364601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.1638364601
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.700995816
Short name T413
Test name
Test status
Simulation time 389341657136 ps
CPU time 143.41 seconds
Started Apr 28 02:49:47 PM PDT 24
Finished Apr 28 02:52:11 PM PDT 24
Peak memory 202380 kb
Host smart-d6257d94-2139-4584-9e21-3da89f6e3661
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700995816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.700995816
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1768777445
Short name T194
Test name
Test status
Simulation time 110525274299 ps
CPU time 348.58 seconds
Started Apr 28 02:49:46 PM PDT 24
Finished Apr 28 02:55:36 PM PDT 24
Peak memory 202736 kb
Host smart-6d9e7102-4bad-4964-8610-899d704ad011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768777445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1768777445
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4067262597
Short name T369
Test name
Test status
Simulation time 34438945086 ps
CPU time 71.73 seconds
Started Apr 28 02:49:47 PM PDT 24
Finished Apr 28 02:50:59 PM PDT 24
Peak memory 202144 kb
Host smart-e2dace10-0088-4800-a8cd-ff6ce059d507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067262597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4067262597
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3522454527
Short name T663
Test name
Test status
Simulation time 2824515878 ps
CPU time 1.3 seconds
Started Apr 28 02:49:46 PM PDT 24
Finished Apr 28 02:49:48 PM PDT 24
Peak memory 202140 kb
Host smart-a6ce0109-2882-4d38-8806-7b279eb1ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522454527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3522454527
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3088402120
Short name T472
Test name
Test status
Simulation time 5765552058 ps
CPU time 7.49 seconds
Started Apr 28 02:49:36 PM PDT 24
Finished Apr 28 02:49:45 PM PDT 24
Peak memory 202116 kb
Host smart-f9dc0a02-b89c-469a-a9c5-c3eef6cc66c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088402120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3088402120
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1582338254
Short name T617
Test name
Test status
Simulation time 340053894130 ps
CPU time 433.65 seconds
Started Apr 28 02:49:50 PM PDT 24
Finished Apr 28 02:57:04 PM PDT 24
Peak memory 202380 kb
Host smart-a0760f70-825d-4e18-a24d-8040dac57115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582338254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1582338254
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.677831176
Short name T480
Test name
Test status
Simulation time 410148883 ps
CPU time 1.53 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 02:45:42 PM PDT 24
Peak memory 202028 kb
Host smart-a07ce667-384a-4c9e-bdd9-0a764ea1cb87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677831176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.677831176
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2179777141
Short name T527
Test name
Test status
Simulation time 167072254968 ps
CPU time 98.48 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 02:47:19 PM PDT 24
Peak memory 202328 kb
Host smart-9df9f574-1099-4370-a83f-02c9de1be6ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179777141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2179777141
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1419256467
Short name T253
Test name
Test status
Simulation time 322418943713 ps
CPU time 704.17 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 02:57:24 PM PDT 24
Peak memory 202308 kb
Host smart-a73ad5a5-e3f0-4aa1-be02-7bb7f679df86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419256467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1419256467
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3649100862
Short name T674
Test name
Test status
Simulation time 158480374616 ps
CPU time 376.24 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 02:51:57 PM PDT 24
Peak memory 202328 kb
Host smart-589a040f-59c1-4085-a389-23ba833c17d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649100862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3649100862
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2865492686
Short name T303
Test name
Test status
Simulation time 329702460761 ps
CPU time 391.27 seconds
Started Apr 28 02:45:39 PM PDT 24
Finished Apr 28 02:52:12 PM PDT 24
Peak memory 202428 kb
Host smart-c2d5a96e-2505-4e8d-8109-9acd675e9de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865492686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2865492686
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1458704473
Short name T85
Test name
Test status
Simulation time 324594533901 ps
CPU time 312.63 seconds
Started Apr 28 02:45:37 PM PDT 24
Finished Apr 28 02:50:51 PM PDT 24
Peak memory 202296 kb
Host smart-9858b37f-6a3f-406a-9c67-553cb4de7ebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458704473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1458704473
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3302390300
Short name T189
Test name
Test status
Simulation time 534732927767 ps
CPU time 381.56 seconds
Started Apr 28 02:45:38 PM PDT 24
Finished Apr 28 02:52:02 PM PDT 24
Peak memory 202320 kb
Host smart-3b11e48c-2a5a-47da-9027-e36c76eae52e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302390300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3302390300
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.322196877
Short name T161
Test name
Test status
Simulation time 616262384034 ps
CPU time 1495.3 seconds
Started Apr 28 02:45:37 PM PDT 24
Finished Apr 28 03:10:34 PM PDT 24
Peak memory 202280 kb
Host smart-f0542a61-3d07-4e43-9f8f-5d9aca940ba3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322196877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.322196877
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3100199072
Short name T716
Test name
Test status
Simulation time 130508711722 ps
CPU time 433.44 seconds
Started Apr 28 02:45:36 PM PDT 24
Finished Apr 28 02:52:51 PM PDT 24
Peak memory 202636 kb
Host smart-0362db20-f724-4cdc-9a81-205ff3ead3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100199072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3100199072
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.798057813
Short name T664
Test name
Test status
Simulation time 25503576749 ps
CPU time 58.38 seconds
Started Apr 28 02:45:36 PM PDT 24
Finished Apr 28 02:46:35 PM PDT 24
Peak memory 202140 kb
Host smart-723474f0-4483-4b8b-b910-3f9f7df356a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798057813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.798057813
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1208340462
Short name T151
Test name
Test status
Simulation time 4700442621 ps
CPU time 2.64 seconds
Started Apr 28 02:45:40 PM PDT 24
Finished Apr 28 02:45:44 PM PDT 24
Peak memory 202000 kb
Host smart-2bf67f45-66e6-4d95-a2c6-3c176956e70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208340462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1208340462
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3834973774
Short name T76
Test name
Test status
Simulation time 4479033408 ps
CPU time 10.77 seconds
Started Apr 28 02:45:35 PM PDT 24
Finished Apr 28 02:45:47 PM PDT 24
Peak memory 217800 kb
Host smart-5652d205-307d-44b1-b715-2ed4cd73c7e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834973774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3834973774
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1056256013
Short name T486
Test name
Test status
Simulation time 5871708567 ps
CPU time 2.59 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:45:45 PM PDT 24
Peak memory 202008 kb
Host smart-e191b09b-3c24-4ea2-8efb-88e9df7895b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056256013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1056256013
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2760788154
Short name T214
Test name
Test status
Simulation time 33600088972 ps
CPU time 88.34 seconds
Started Apr 28 02:45:45 PM PDT 24
Finished Apr 28 02:47:14 PM PDT 24
Peak memory 211028 kb
Host smart-4efc080c-1ad3-4832-b9f5-88429eb701b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760788154 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2760788154
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1802608194
Short name T743
Test name
Test status
Simulation time 323187995 ps
CPU time 0.99 seconds
Started Apr 28 02:50:03 PM PDT 24
Finished Apr 28 02:50:04 PM PDT 24
Peak memory 201984 kb
Host smart-0603fc16-e15f-4e6b-b90c-ca6a85bfbadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802608194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1802608194
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.957754615
Short name T317
Test name
Test status
Simulation time 335017246179 ps
CPU time 163.18 seconds
Started Apr 28 02:49:55 PM PDT 24
Finished Apr 28 02:52:39 PM PDT 24
Peak memory 202336 kb
Host smart-f4993417-00dd-46dd-b98e-f37e82cddb31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957754615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gati
ng.957754615
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2584372704
Short name T217
Test name
Test status
Simulation time 187645051149 ps
CPU time 116.48 seconds
Started Apr 28 02:49:55 PM PDT 24
Finished Apr 28 02:51:52 PM PDT 24
Peak memory 202348 kb
Host smart-e1b3269b-64e8-4d23-8464-448da36ce5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584372704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2584372704
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3331984141
Short name T149
Test name
Test status
Simulation time 495294513353 ps
CPU time 321.86 seconds
Started Apr 28 02:49:51 PM PDT 24
Finished Apr 28 02:55:13 PM PDT 24
Peak memory 202292 kb
Host smart-c20aa4bb-1b5e-4bab-bd82-08fb1268d62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331984141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3331984141
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1216105091
Short name T583
Test name
Test status
Simulation time 328201826908 ps
CPU time 726.08 seconds
Started Apr 28 02:49:55 PM PDT 24
Finished Apr 28 03:02:02 PM PDT 24
Peak memory 202248 kb
Host smart-e411ca3f-7e40-4ac7-90c1-6e094625d468
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216105091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1216105091
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3737967218
Short name T547
Test name
Test status
Simulation time 162373045457 ps
CPU time 92.02 seconds
Started Apr 28 02:49:56 PM PDT 24
Finished Apr 28 02:51:29 PM PDT 24
Peak memory 202408 kb
Host smart-87e50ff6-cbfe-4ee0-93b8-afcf230fb627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737967218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3737967218
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2183157527
Short name T777
Test name
Test status
Simulation time 327278889538 ps
CPU time 108.01 seconds
Started Apr 28 02:49:55 PM PDT 24
Finished Apr 28 02:51:43 PM PDT 24
Peak memory 202264 kb
Host smart-ba0a4754-9a98-44d5-a077-863b959130e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183157527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2183157527
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2143084691
Short name T192
Test name
Test status
Simulation time 537810103879 ps
CPU time 274.4 seconds
Started Apr 28 02:49:56 PM PDT 24
Finished Apr 28 02:54:31 PM PDT 24
Peak memory 202296 kb
Host smart-3fc13cbf-bd4b-4b79-9ca5-71a4356487aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143084691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2143084691
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2580920849
Short name T443
Test name
Test status
Simulation time 202057577681 ps
CPU time 421.46 seconds
Started Apr 28 02:49:57 PM PDT 24
Finished Apr 28 02:56:58 PM PDT 24
Peak memory 202288 kb
Host smart-d152a80e-b469-4dd9-8fca-cc23e7864415
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580920849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2580920849
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2141449219
Short name T94
Test name
Test status
Simulation time 75836177847 ps
CPU time 427.03 seconds
Started Apr 28 02:49:57 PM PDT 24
Finished Apr 28 02:57:04 PM PDT 24
Peak memory 202664 kb
Host smart-8f094f86-98b8-4986-80c4-7831843ecc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141449219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2141449219
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3760928094
Short name T713
Test name
Test status
Simulation time 40928944639 ps
CPU time 51.25 seconds
Started Apr 28 02:49:58 PM PDT 24
Finished Apr 28 02:50:49 PM PDT 24
Peak memory 202128 kb
Host smart-c86ffddf-94eb-44cb-bf4a-6a0ab40c87b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760928094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3760928094
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3203718610
Short name T757
Test name
Test status
Simulation time 4703294896 ps
CPU time 11.83 seconds
Started Apr 28 02:49:55 PM PDT 24
Finished Apr 28 02:50:08 PM PDT 24
Peak memory 202116 kb
Host smart-f23a5560-c58e-42d9-8826-e7bed6548e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203718610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3203718610
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.602721660
Short name T388
Test name
Test status
Simulation time 5822817499 ps
CPU time 8.14 seconds
Started Apr 28 02:49:55 PM PDT 24
Finished Apr 28 02:50:04 PM PDT 24
Peak memory 202124 kb
Host smart-d708ff7c-6969-4650-9e21-01ce027b7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602721660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.602721660
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.689801350
Short name T150
Test name
Test status
Simulation time 200290727843 ps
CPU time 422.06 seconds
Started Apr 28 02:50:02 PM PDT 24
Finished Apr 28 02:57:04 PM PDT 24
Peak memory 202300 kb
Host smart-b5cd3bf4-7ea4-4b39-ae09-96d8538c256d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689801350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all.
689801350
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.2335715573
Short name T626
Test name
Test status
Simulation time 387272928 ps
CPU time 1.06 seconds
Started Apr 28 02:50:19 PM PDT 24
Finished Apr 28 02:50:20 PM PDT 24
Peak memory 201924 kb
Host smart-6f7646d1-b65a-4ffd-875f-b584e24fefc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335715573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.2335715573
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3267830104
Short name T752
Test name
Test status
Simulation time 167747956968 ps
CPU time 53.33 seconds
Started Apr 28 02:50:09 PM PDT 24
Finished Apr 28 02:51:03 PM PDT 24
Peak memory 202400 kb
Host smart-8ff63bbf-68de-46b4-8036-b3d62b2315c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267830104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3267830104
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1676300321
Short name T236
Test name
Test status
Simulation time 161478625663 ps
CPU time 60.51 seconds
Started Apr 28 02:50:09 PM PDT 24
Finished Apr 28 02:51:10 PM PDT 24
Peak memory 202284 kb
Host smart-43438cb0-b6a6-450f-92ef-73be701d39ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676300321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1676300321
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2294780315
Short name T135
Test name
Test status
Simulation time 329288762505 ps
CPU time 445.11 seconds
Started Apr 28 02:50:08 PM PDT 24
Finished Apr 28 02:57:34 PM PDT 24
Peak memory 202312 kb
Host smart-55909525-1d0d-43ca-b466-f1a789de76fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294780315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2294780315
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1288104801
Short name T458
Test name
Test status
Simulation time 490278922861 ps
CPU time 1132.16 seconds
Started Apr 28 02:50:11 PM PDT 24
Finished Apr 28 03:09:03 PM PDT 24
Peak memory 202320 kb
Host smart-4b9aacb1-f6c3-4ae8-ab88-8bfbe7c3f3b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288104801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1288104801
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3796713704
Short name T766
Test name
Test status
Simulation time 327465879914 ps
CPU time 804.18 seconds
Started Apr 28 02:50:09 PM PDT 24
Finished Apr 28 03:03:34 PM PDT 24
Peak memory 202336 kb
Host smart-30443197-e27d-439d-a636-593e0a94c82f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796713704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3796713704
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.496664705
Short name T249
Test name
Test status
Simulation time 366809358646 ps
CPU time 211.1 seconds
Started Apr 28 02:50:09 PM PDT 24
Finished Apr 28 02:53:40 PM PDT 24
Peak memory 202348 kb
Host smart-8c2fd8cc-5adb-4ca1-ae22-c1cf47135d3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496664705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.496664705
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1309878587
Short name T524
Test name
Test status
Simulation time 597568714949 ps
CPU time 1355.42 seconds
Started Apr 28 02:50:08 PM PDT 24
Finished Apr 28 03:12:44 PM PDT 24
Peak memory 202284 kb
Host smart-733b5be2-6ff2-499c-8db9-98ae885733d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309878587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1309878587
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3695175941
Short name T196
Test name
Test status
Simulation time 99741052990 ps
CPU time 505.67 seconds
Started Apr 28 02:50:16 PM PDT 24
Finished Apr 28 02:58:42 PM PDT 24
Peak memory 202752 kb
Host smart-8ac6f053-b1dd-40de-bcf7-96b9e249ba4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695175941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3695175941
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1399176712
Short name T691
Test name
Test status
Simulation time 21923204410 ps
CPU time 12.42 seconds
Started Apr 28 02:50:14 PM PDT 24
Finished Apr 28 02:50:27 PM PDT 24
Peak memory 202116 kb
Host smart-e579e5e8-81af-4adf-8be8-8963517874d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399176712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1399176712
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3957475359
Short name T768
Test name
Test status
Simulation time 3224052385 ps
CPU time 9.2 seconds
Started Apr 28 02:50:14 PM PDT 24
Finished Apr 28 02:50:24 PM PDT 24
Peak memory 202144 kb
Host smart-faae23ab-3558-4d5b-b876-179f2553791c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957475359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3957475359
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2423284783
Short name T746
Test name
Test status
Simulation time 5732269793 ps
CPU time 4.1 seconds
Started Apr 28 02:50:02 PM PDT 24
Finished Apr 28 02:50:06 PM PDT 24
Peak memory 202136 kb
Host smart-51fbf27a-9f41-4943-85cf-5bd414e983a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423284783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2423284783
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1203575782
Short name T301
Test name
Test status
Simulation time 197292788018 ps
CPU time 480.61 seconds
Started Apr 28 02:50:20 PM PDT 24
Finished Apr 28 02:58:21 PM PDT 24
Peak memory 202316 kb
Host smart-4a4ca3e4-7c91-49bc-a81d-61e8cad9410f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203575782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1203575782
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1306630330
Short name T456
Test name
Test status
Simulation time 18304744350 ps
CPU time 45.54 seconds
Started Apr 28 02:50:20 PM PDT 24
Finished Apr 28 02:51:06 PM PDT 24
Peak memory 211096 kb
Host smart-4bf7138a-cba6-4adf-af71-4e3e1765f203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306630330 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1306630330
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.2484992624
Short name T511
Test name
Test status
Simulation time 315740877 ps
CPU time 1.36 seconds
Started Apr 28 02:50:32 PM PDT 24
Finished Apr 28 02:50:34 PM PDT 24
Peak memory 202012 kb
Host smart-b4be9d65-d7ae-4b44-9e0a-08a8b9c3dd3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484992624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.2484992624
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.735430702
Short name T484
Test name
Test status
Simulation time 157113864509 ps
CPU time 98.04 seconds
Started Apr 28 02:50:21 PM PDT 24
Finished Apr 28 02:51:59 PM PDT 24
Peak memory 202280 kb
Host smart-79779d79-8019-41a9-bfa6-cc11082ac44b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=735430702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.735430702
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1007280974
Short name T601
Test name
Test status
Simulation time 164262985905 ps
CPU time 91.71 seconds
Started Apr 28 02:50:21 PM PDT 24
Finished Apr 28 02:51:54 PM PDT 24
Peak memory 202284 kb
Host smart-9900e9bb-e69b-4e7b-a906-318da622fb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007280974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1007280974
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.3074075421
Short name T400
Test name
Test status
Simulation time 160790118009 ps
CPU time 179.36 seconds
Started Apr 28 02:50:20 PM PDT 24
Finished Apr 28 02:53:20 PM PDT 24
Peak memory 202288 kb
Host smart-db2a506a-89ca-4636-a3c5-1ad02ff5b82c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074075421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.3074075421
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.180732041
Short name T481
Test name
Test status
Simulation time 172782044756 ps
CPU time 46.81 seconds
Started Apr 28 02:50:20 PM PDT 24
Finished Apr 28 02:51:07 PM PDT 24
Peak memory 202364 kb
Host smart-7c6e6185-d1c3-48ae-8b1f-499c534bd7b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180732041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.180732041
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2793914603
Short name T608
Test name
Test status
Simulation time 607465217142 ps
CPU time 634.12 seconds
Started Apr 28 02:50:26 PM PDT 24
Finished Apr 28 03:01:01 PM PDT 24
Peak memory 202328 kb
Host smart-a35d9201-b59d-4254-af84-54fed0d0b797
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793914603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2793914603
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.817988647
Short name T356
Test name
Test status
Simulation time 121412178634 ps
CPU time 466.38 seconds
Started Apr 28 02:50:32 PM PDT 24
Finished Apr 28 02:58:18 PM PDT 24
Peak memory 202632 kb
Host smart-a57c16f9-8b01-41b0-89bc-9c898a9a2c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817988647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.817988647
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4095619083
Short name T536
Test name
Test status
Simulation time 26235630817 ps
CPU time 44.9 seconds
Started Apr 28 02:50:26 PM PDT 24
Finished Apr 28 02:51:11 PM PDT 24
Peak memory 202100 kb
Host smart-70218b09-efcb-42bc-970b-1573a1aa957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095619083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4095619083
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.399109318
Short name T628
Test name
Test status
Simulation time 4709647021 ps
CPU time 3.87 seconds
Started Apr 28 02:50:27 PM PDT 24
Finished Apr 28 02:50:32 PM PDT 24
Peak memory 202132 kb
Host smart-626732d8-8a9e-4ffe-b60d-bff541f9cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399109318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.399109318
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2786112815
Short name T525
Test name
Test status
Simulation time 5600390710 ps
CPU time 7.37 seconds
Started Apr 28 02:50:20 PM PDT 24
Finished Apr 28 02:50:28 PM PDT 24
Peak memory 202044 kb
Host smart-b8f3a4a1-58c5-45f6-a484-095c93a43c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786112815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2786112815
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.315110369
Short name T33
Test name
Test status
Simulation time 293988965329 ps
CPU time 499.98 seconds
Started Apr 28 02:50:34 PM PDT 24
Finished Apr 28 02:58:54 PM PDT 24
Peak memory 210744 kb
Host smart-7d451c72-5106-4619-878c-72ab6ac4437a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315110369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
315110369
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2325568947
Short name T296
Test name
Test status
Simulation time 207156796810 ps
CPU time 193.1 seconds
Started Apr 28 02:50:33 PM PDT 24
Finished Apr 28 02:53:46 PM PDT 24
Peak memory 211100 kb
Host smart-db2faf3a-54b3-4f97-b3c2-cdae4b706db5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325568947 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2325568947
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2040409926
Short name T796
Test name
Test status
Simulation time 400890587 ps
CPU time 0.77 seconds
Started Apr 28 02:50:44 PM PDT 24
Finished Apr 28 02:50:46 PM PDT 24
Peak memory 202004 kb
Host smart-d8959139-1842-45b9-88fa-5f332bbe13af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040409926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2040409926
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2625512405
Short name T775
Test name
Test status
Simulation time 345949804315 ps
CPU time 198.94 seconds
Started Apr 28 02:50:38 PM PDT 24
Finished Apr 28 02:53:58 PM PDT 24
Peak memory 202292 kb
Host smart-7e4c71db-7ea9-4544-ba8e-1e930381c38e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625512405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2625512405
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1463861123
Short name T245
Test name
Test status
Simulation time 198657069589 ps
CPU time 385.51 seconds
Started Apr 28 02:50:40 PM PDT 24
Finished Apr 28 02:57:06 PM PDT 24
Peak memory 202372 kb
Host smart-222648a8-47dd-4fbe-ae16-014191c3f0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463861123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1463861123
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.4248699928
Short name T422
Test name
Test status
Simulation time 160594825066 ps
CPU time 200.72 seconds
Started Apr 28 02:50:40 PM PDT 24
Finished Apr 28 02:54:02 PM PDT 24
Peak memory 202304 kb
Host smart-9eb0a236-4ccd-40a6-9e0e-01a4e5f320c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248699928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.4248699928
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1188238742
Short name T137
Test name
Test status
Simulation time 163125241223 ps
CPU time 94.16 seconds
Started Apr 28 02:50:41 PM PDT 24
Finished Apr 28 02:52:15 PM PDT 24
Peak memory 202324 kb
Host smart-9cdd5e65-e979-491d-a7bf-601069a42451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188238742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1188238742
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.3976248295
Short name T751
Test name
Test status
Simulation time 339118544019 ps
CPU time 415.16 seconds
Started Apr 28 02:50:41 PM PDT 24
Finished Apr 28 02:57:37 PM PDT 24
Peak memory 202304 kb
Host smart-f7f0f43a-838e-4014-9f93-ecfddec42e39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976248295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.3976248295
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2272915658
Short name T285
Test name
Test status
Simulation time 504050974559 ps
CPU time 1191.05 seconds
Started Apr 28 02:50:40 PM PDT 24
Finished Apr 28 03:10:31 PM PDT 24
Peak memory 202360 kb
Host smart-f6c484b2-c7cd-4bce-b44c-7084ecca01f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272915658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2272915658
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.37901628
Short name T459
Test name
Test status
Simulation time 632800581024 ps
CPU time 378.49 seconds
Started Apr 28 02:50:39 PM PDT 24
Finished Apr 28 02:56:58 PM PDT 24
Peak memory 202308 kb
Host smart-9e6c7350-2e7d-4d9a-9d8e-e71362481637
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37901628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
dc_ctrl_filters_wakeup_fixed.37901628
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3694968442
Short name T650
Test name
Test status
Simulation time 87326737977 ps
CPU time 294.31 seconds
Started Apr 28 02:50:45 PM PDT 24
Finished Apr 28 02:55:40 PM PDT 24
Peak memory 202656 kb
Host smart-bc4ea2b0-636d-4727-84c0-63b1964a67e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694968442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3694968442
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3087780622
Short name T658
Test name
Test status
Simulation time 23740111914 ps
CPU time 51.69 seconds
Started Apr 28 02:50:45 PM PDT 24
Finished Apr 28 02:51:37 PM PDT 24
Peak memory 202128 kb
Host smart-86eaca94-5039-4309-b50f-8e9ec432c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087780622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3087780622
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1520517337
Short name T648
Test name
Test status
Simulation time 4835419723 ps
CPU time 7 seconds
Started Apr 28 02:50:45 PM PDT 24
Finished Apr 28 02:50:52 PM PDT 24
Peak memory 202116 kb
Host smart-5c585565-3015-405c-aa77-2a1fb4bd157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520517337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1520517337
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2324084693
Short name T25
Test name
Test status
Simulation time 6064229127 ps
CPU time 4.28 seconds
Started Apr 28 02:50:31 PM PDT 24
Finished Apr 28 02:50:36 PM PDT 24
Peak memory 202152 kb
Host smart-bf5062cf-b727-4aef-8118-95df7fb4d8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324084693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2324084693
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.153877828
Short name T718
Test name
Test status
Simulation time 358655675247 ps
CPU time 221.63 seconds
Started Apr 28 02:50:45 PM PDT 24
Finished Apr 28 02:54:27 PM PDT 24
Peak memory 202300 kb
Host smart-ae055d02-ba19-49f9-85bd-3f5e764a81a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153877828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
153877828
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3593587129
Short name T795
Test name
Test status
Simulation time 71066506651 ps
CPU time 100.07 seconds
Started Apr 28 02:50:44 PM PDT 24
Finished Apr 28 02:52:24 PM PDT 24
Peak memory 210640 kb
Host smart-25c56029-2424-466d-80e3-bfd20a6b0ef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593587129 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3593587129
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1831597389
Short name T702
Test name
Test status
Simulation time 503527110 ps
CPU time 1.71 seconds
Started Apr 28 02:51:03 PM PDT 24
Finished Apr 28 02:51:05 PM PDT 24
Peak memory 201956 kb
Host smart-a7e37ed9-3cc2-464f-88e6-8708351ac696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831597389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1831597389
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.4068108473
Short name T289
Test name
Test status
Simulation time 337528049852 ps
CPU time 371.32 seconds
Started Apr 28 02:50:57 PM PDT 24
Finished Apr 28 02:57:09 PM PDT 24
Peak memory 202392 kb
Host smart-01fa930c-58ad-41ad-be7b-bb68a82fcc37
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068108473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.4068108473
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2087091026
Short name T273
Test name
Test status
Simulation time 158611497452 ps
CPU time 193.37 seconds
Started Apr 28 02:50:52 PM PDT 24
Finished Apr 28 02:54:05 PM PDT 24
Peak memory 202372 kb
Host smart-8d5cc5ed-6eb6-4ad3-b0a8-1915dc95b9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087091026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2087091026
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3882586909
Short name T475
Test name
Test status
Simulation time 499972787455 ps
CPU time 1220.3 seconds
Started Apr 28 02:50:59 PM PDT 24
Finished Apr 28 03:11:19 PM PDT 24
Peak memory 202276 kb
Host smart-e8b026a6-dc7f-4ee9-98ef-9a6c3921121c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882586909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3882586909
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2562916633
Short name T284
Test name
Test status
Simulation time 162272254576 ps
CPU time 90.2 seconds
Started Apr 28 02:50:53 PM PDT 24
Finished Apr 28 02:52:24 PM PDT 24
Peak memory 202380 kb
Host smart-90e16441-9e87-4dae-8676-f892dcbe5017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562916633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2562916633
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2717252114
Short name T662
Test name
Test status
Simulation time 497139387469 ps
CPU time 331.67 seconds
Started Apr 28 02:50:51 PM PDT 24
Finished Apr 28 02:56:23 PM PDT 24
Peak memory 202296 kb
Host smart-ca62d07d-fbfa-40df-b1d3-a3a3447c778a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717252114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2717252114
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.352041199
Short name T208
Test name
Test status
Simulation time 412959273334 ps
CPU time 230.81 seconds
Started Apr 28 02:50:57 PM PDT 24
Finished Apr 28 02:54:49 PM PDT 24
Peak memory 202296 kb
Host smart-0db598aa-1483-4cbd-a9a6-d23e2da50f96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352041199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.352041199
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2321859238
Short name T776
Test name
Test status
Simulation time 211795117623 ps
CPU time 249.75 seconds
Started Apr 28 02:50:57 PM PDT 24
Finished Apr 28 02:55:07 PM PDT 24
Peak memory 202288 kb
Host smart-8622738e-ca7f-4e71-985e-85f05e6d5a40
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321859238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2321859238
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.716471492
Short name T203
Test name
Test status
Simulation time 117091480273 ps
CPU time 372.72 seconds
Started Apr 28 02:51:09 PM PDT 24
Finished Apr 28 02:57:22 PM PDT 24
Peak memory 202744 kb
Host smart-2b6a6b42-63b0-4f77-b615-49d171219251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716471492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.716471492
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3131253269
Short name T177
Test name
Test status
Simulation time 24337265905 ps
CPU time 30.52 seconds
Started Apr 28 02:50:57 PM PDT 24
Finished Apr 28 02:51:28 PM PDT 24
Peak memory 202140 kb
Host smart-263a7c0b-1e04-4e60-bfd4-97862659ba5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131253269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3131253269
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2383650641
Short name T493
Test name
Test status
Simulation time 4101841750 ps
CPU time 5.18 seconds
Started Apr 28 02:50:57 PM PDT 24
Finished Apr 28 02:51:02 PM PDT 24
Peak memory 202044 kb
Host smart-fc3a841e-0274-4b6d-9602-f5de580d089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383650641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2383650641
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1933525666
Short name T574
Test name
Test status
Simulation time 5773387950 ps
CPU time 1.64 seconds
Started Apr 28 02:50:51 PM PDT 24
Finished Apr 28 02:50:53 PM PDT 24
Peak memory 202128 kb
Host smart-4044f9e1-2f7d-4db3-8127-2ccf99c5f2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933525666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1933525666
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.106660902
Short name T763
Test name
Test status
Simulation time 356241152 ps
CPU time 0.99 seconds
Started Apr 28 02:51:14 PM PDT 24
Finished Apr 28 02:51:16 PM PDT 24
Peak memory 201960 kb
Host smart-8b84f579-2bb5-496f-8fdf-dae1a26c4a1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106660902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.106660902
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.1920358419
Short name T726
Test name
Test status
Simulation time 495250805507 ps
CPU time 151.11 seconds
Started Apr 28 02:51:09 PM PDT 24
Finished Apr 28 02:53:41 PM PDT 24
Peak memory 202324 kb
Host smart-7ca1b286-ca3a-4572-8db7-3639d7463aa8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920358419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.1920358419
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3573336987
Short name T474
Test name
Test status
Simulation time 169843142129 ps
CPU time 368.13 seconds
Started Apr 28 02:51:08 PM PDT 24
Finished Apr 28 02:57:17 PM PDT 24
Peak memory 202352 kb
Host smart-60f1a276-2bad-47a3-8672-8853127dc940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573336987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3573336987
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1521825325
Short name T506
Test name
Test status
Simulation time 169788952955 ps
CPU time 51.47 seconds
Started Apr 28 02:51:09 PM PDT 24
Finished Apr 28 02:52:01 PM PDT 24
Peak memory 202368 kb
Host smart-8b307691-5c17-4e4b-a3cb-97d32fdcf09c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521825325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1521825325
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.640594389
Short name T26
Test name
Test status
Simulation time 164861943678 ps
CPU time 90.11 seconds
Started Apr 28 02:51:03 PM PDT 24
Finished Apr 28 02:52:34 PM PDT 24
Peak memory 202416 kb
Host smart-625ea8d0-907f-4e9b-9fb8-be476f26efbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640594389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.640594389
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1921788925
Short name T700
Test name
Test status
Simulation time 500775444235 ps
CPU time 704.74 seconds
Started Apr 28 02:51:05 PM PDT 24
Finished Apr 28 03:02:50 PM PDT 24
Peak memory 202288 kb
Host smart-0da20325-3d30-49ed-a34e-3a012aae981b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921788925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1921788925
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.445539368
Short name T163
Test name
Test status
Simulation time 259251372765 ps
CPU time 544.34 seconds
Started Apr 28 02:51:09 PM PDT 24
Finished Apr 28 03:00:14 PM PDT 24
Peak memory 202328 kb
Host smart-84914641-8349-43e4-a2d2-91c2f664322d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445539368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.445539368
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1344958823
Short name T561
Test name
Test status
Simulation time 391962056596 ps
CPU time 242.5 seconds
Started Apr 28 02:51:08 PM PDT 24
Finished Apr 28 02:55:11 PM PDT 24
Peak memory 202332 kb
Host smart-77d7ff80-43a3-4792-b43f-20faea3963d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344958823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1344958823
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1966870688
Short name T199
Test name
Test status
Simulation time 74297265007 ps
CPU time 257.48 seconds
Started Apr 28 02:51:15 PM PDT 24
Finished Apr 28 02:55:33 PM PDT 24
Peak memory 202588 kb
Host smart-bc2a8787-36c1-4ea4-bb34-fdd60914ac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966870688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1966870688
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.742169006
Short name T523
Test name
Test status
Simulation time 32427587732 ps
CPU time 78.03 seconds
Started Apr 28 02:51:10 PM PDT 24
Finished Apr 28 02:52:28 PM PDT 24
Peak memory 202136 kb
Host smart-c02f891a-10ed-4bc3-9d41-742204999eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742169006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.742169006
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.79916954
Short name T439
Test name
Test status
Simulation time 3742598141 ps
CPU time 5.53 seconds
Started Apr 28 02:51:09 PM PDT 24
Finished Apr 28 02:51:15 PM PDT 24
Peak memory 202148 kb
Host smart-066a3777-3f33-4b05-9efa-6f979b817c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79916954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.79916954
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.3450138249
Short name T451
Test name
Test status
Simulation time 5677060545 ps
CPU time 4.28 seconds
Started Apr 28 02:51:08 PM PDT 24
Finished Apr 28 02:51:12 PM PDT 24
Peak memory 202116 kb
Host smart-fc630800-9cd6-44cb-9450-6d3eaf6f9d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450138249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.3450138249
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2419445392
Short name T312
Test name
Test status
Simulation time 500424494598 ps
CPU time 1220.09 seconds
Started Apr 28 02:51:16 PM PDT 24
Finished Apr 28 03:11:36 PM PDT 24
Peak memory 202408 kb
Host smart-5ad1de28-7eca-415e-abe0-2a05b5a79043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419445392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2419445392
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.923074640
Short name T396
Test name
Test status
Simulation time 456750137 ps
CPU time 0.83 seconds
Started Apr 28 02:51:28 PM PDT 24
Finished Apr 28 02:51:29 PM PDT 24
Peak memory 201988 kb
Host smart-f523d945-ecae-4c34-942e-4c405bfb23e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923074640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.923074640
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2988595478
Short name T529
Test name
Test status
Simulation time 359119569396 ps
CPU time 147.68 seconds
Started Apr 28 02:51:20 PM PDT 24
Finished Apr 28 02:53:48 PM PDT 24
Peak memory 202340 kb
Host smart-4f1cbc17-be5a-4d39-8868-8525f6d8596a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988595478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2988595478
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4250161672
Short name T538
Test name
Test status
Simulation time 160582604822 ps
CPU time 91.76 seconds
Started Apr 28 02:51:23 PM PDT 24
Finished Apr 28 02:52:55 PM PDT 24
Peak memory 202316 kb
Host smart-2e25f4cb-2f99-4036-a4b7-c7a35bc468c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250161672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4250161672
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.102282221
Short name T706
Test name
Test status
Simulation time 164095081851 ps
CPU time 101.82 seconds
Started Apr 28 02:51:23 PM PDT 24
Finished Apr 28 02:53:05 PM PDT 24
Peak memory 202308 kb
Host smart-a9c05b9b-98d5-41a9-bfdd-7596045a1dcb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=102282221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.102282221
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2350951463
Short name T184
Test name
Test status
Simulation time 323069658966 ps
CPU time 54.84 seconds
Started Apr 28 02:51:15 PM PDT 24
Finished Apr 28 02:52:10 PM PDT 24
Peak memory 202332 kb
Host smart-75eb3e3b-3178-43e9-9678-dbef62342b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350951463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2350951463
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1023481760
Short name T577
Test name
Test status
Simulation time 167829122874 ps
CPU time 101.22 seconds
Started Apr 28 02:51:22 PM PDT 24
Finished Apr 28 02:53:03 PM PDT 24
Peak memory 202276 kb
Host smart-5903eafb-3cc6-4cda-a4e4-1ed37211ec14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023481760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1023481760
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4057582537
Short name T348
Test name
Test status
Simulation time 188793606784 ps
CPU time 406.23 seconds
Started Apr 28 02:51:20 PM PDT 24
Finished Apr 28 02:58:07 PM PDT 24
Peak memory 202380 kb
Host smart-a53ea272-b48c-49f4-a9eb-2afb0e99a904
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057582537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4057582537
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3066498594
Short name T758
Test name
Test status
Simulation time 618070544924 ps
CPU time 1426.64 seconds
Started Apr 28 02:51:23 PM PDT 24
Finished Apr 28 03:15:10 PM PDT 24
Peak memory 202296 kb
Host smart-3f248e2a-034c-407e-8b2e-1380ff6d41f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066498594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3066498594
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2994598922
Short name T560
Test name
Test status
Simulation time 74847072000 ps
CPU time 309.59 seconds
Started Apr 28 02:51:21 PM PDT 24
Finished Apr 28 02:56:31 PM PDT 24
Peak memory 202728 kb
Host smart-2ccf954a-8d1c-4166-8c57-636b816ad504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994598922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2994598922
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2128487473
Short name T612
Test name
Test status
Simulation time 27176907295 ps
CPU time 7.23 seconds
Started Apr 28 02:51:20 PM PDT 24
Finished Apr 28 02:51:28 PM PDT 24
Peak memory 202100 kb
Host smart-597a9124-2708-49c0-b7e3-6099b220a23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128487473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2128487473
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.886207601
Short name T423
Test name
Test status
Simulation time 5370696801 ps
CPU time 6.93 seconds
Started Apr 28 02:51:19 PM PDT 24
Finished Apr 28 02:51:26 PM PDT 24
Peak memory 202160 kb
Host smart-6b5ed0ec-b081-4e7e-968f-37350cdc3807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886207601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.886207601
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.73434361
Short name T509
Test name
Test status
Simulation time 5680833173 ps
CPU time 3.6 seconds
Started Apr 28 02:51:16 PM PDT 24
Finished Apr 28 02:51:20 PM PDT 24
Peak memory 202084 kb
Host smart-ab32a92b-4c2f-4e54-8424-558c6415abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73434361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.73434361
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2786207161
Short name T341
Test name
Test status
Simulation time 713614330274 ps
CPU time 819.76 seconds
Started Apr 28 02:51:26 PM PDT 24
Finished Apr 28 03:05:07 PM PDT 24
Peak memory 202356 kb
Host smart-3a119f9d-822a-4ec5-af74-fe90e31a63be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786207161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2786207161
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1484801762
Short name T108
Test name
Test status
Simulation time 61356093754 ps
CPU time 165.11 seconds
Started Apr 28 02:51:20 PM PDT 24
Finished Apr 28 02:54:06 PM PDT 24
Peak memory 218664 kb
Host smart-1176ea30-87ed-436c-b4ff-d708f5880061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484801762 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1484801762
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.4175581268
Short name T102
Test name
Test status
Simulation time 325356542 ps
CPU time 1.31 seconds
Started Apr 28 02:51:36 PM PDT 24
Finished Apr 28 02:51:38 PM PDT 24
Peak memory 201980 kb
Host smart-1b2709ea-73b2-41e3-9345-884a2b3cb155
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175581268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.4175581268
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3526029083
Short name T222
Test name
Test status
Simulation time 348903189015 ps
CPU time 845.31 seconds
Started Apr 28 02:51:26 PM PDT 24
Finished Apr 28 03:05:32 PM PDT 24
Peak memory 202276 kb
Host smart-ee4048e1-3f6f-499f-9578-aa47f3df8a43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526029083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3526029083
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4134129356
Short name T155
Test name
Test status
Simulation time 164077145060 ps
CPU time 92.37 seconds
Started Apr 28 02:51:32 PM PDT 24
Finished Apr 28 02:53:04 PM PDT 24
Peak memory 202320 kb
Host smart-c4756a70-9d86-4525-b49f-9db4fbf9a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134129356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4134129356
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.294092912
Short name T558
Test name
Test status
Simulation time 158957000997 ps
CPU time 78.84 seconds
Started Apr 28 02:51:25 PM PDT 24
Finished Apr 28 02:52:45 PM PDT 24
Peak memory 202276 kb
Host smart-8abe3a45-aa4f-4a0f-8a15-3d874e3f19e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294092912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.294092912
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2877637024
Short name T733
Test name
Test status
Simulation time 170735014470 ps
CPU time 98.48 seconds
Started Apr 28 02:51:26 PM PDT 24
Finished Apr 28 02:53:06 PM PDT 24
Peak memory 202300 kb
Host smart-e134cfc0-119a-47a5-9018-ee97350a39f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877637024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2877637024
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2771709124
Short name T624
Test name
Test status
Simulation time 326016528313 ps
CPU time 734.14 seconds
Started Apr 28 02:51:27 PM PDT 24
Finished Apr 28 03:03:41 PM PDT 24
Peak memory 202272 kb
Host smart-b30eeb5d-e207-4ff8-acca-41faad463503
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771709124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2771709124
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3406488745
Short name T344
Test name
Test status
Simulation time 437619149400 ps
CPU time 494.77 seconds
Started Apr 28 02:51:26 PM PDT 24
Finished Apr 28 02:59:42 PM PDT 24
Peak memory 202284 kb
Host smart-e4a60209-9fad-4569-bf91-27b7565c9724
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406488745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3406488745
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.824477455
Short name T563
Test name
Test status
Simulation time 396104120141 ps
CPU time 806.2 seconds
Started Apr 28 02:51:27 PM PDT 24
Finished Apr 28 03:04:54 PM PDT 24
Peak memory 202300 kb
Host smart-e488941b-2149-4958-bfb0-d081ff5d95c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824477455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.824477455
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3539727696
Short name T359
Test name
Test status
Simulation time 100544717955 ps
CPU time 392.12 seconds
Started Apr 28 02:51:37 PM PDT 24
Finished Apr 28 02:58:09 PM PDT 24
Peak memory 202660 kb
Host smart-67752c04-edcc-47f5-9de9-795207ad075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539727696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3539727696
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1743792838
Short name T786
Test name
Test status
Simulation time 33565731543 ps
CPU time 5.92 seconds
Started Apr 28 02:51:31 PM PDT 24
Finished Apr 28 02:51:38 PM PDT 24
Peak memory 202132 kb
Host smart-160a9412-b6bd-4fb6-9ae0-7abd0b0cc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743792838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1743792838
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3171110200
Short name T531
Test name
Test status
Simulation time 5001832719 ps
CPU time 11.85 seconds
Started Apr 28 02:51:30 PM PDT 24
Finished Apr 28 02:51:42 PM PDT 24
Peak memory 202120 kb
Host smart-237917d5-68ad-440d-9bcf-c92096c87d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171110200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3171110200
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3928484332
Short name T412
Test name
Test status
Simulation time 5671335127 ps
CPU time 4.23 seconds
Started Apr 28 02:51:26 PM PDT 24
Finished Apr 28 02:51:31 PM PDT 24
Peak memory 202132 kb
Host smart-23cb7180-519d-4dbe-969a-47cbba80b561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928484332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3928484332
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2298578186
Short name T36
Test name
Test status
Simulation time 172703236195 ps
CPU time 404.92 seconds
Started Apr 28 02:51:36 PM PDT 24
Finished Apr 28 02:58:22 PM PDT 24
Peak memory 202312 kb
Host smart-c5a8d1c0-cb30-425a-bf4e-a5de0fcdd17d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298578186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2298578186
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2951957090
Short name T18
Test name
Test status
Simulation time 393672085324 ps
CPU time 96.26 seconds
Started Apr 28 02:51:36 PM PDT 24
Finished Apr 28 02:53:12 PM PDT 24
Peak memory 210976 kb
Host smart-ca85eaa3-b008-423f-bb77-32dad430a9f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951957090 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2951957090
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3656788706
Short name T431
Test name
Test status
Simulation time 524561779 ps
CPU time 0.93 seconds
Started Apr 28 02:51:52 PM PDT 24
Finished Apr 28 02:51:53 PM PDT 24
Peak memory 201992 kb
Host smart-8196e292-18da-4a42-93ee-1836d30dc74f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656788706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3656788706
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.449519671
Short name T212
Test name
Test status
Simulation time 191775859814 ps
CPU time 408.03 seconds
Started Apr 28 02:51:47 PM PDT 24
Finished Apr 28 02:58:36 PM PDT 24
Peak memory 202392 kb
Host smart-1bdcd607-582b-4055-9188-1057ea096d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449519671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.449519671
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1246263556
Short name T271
Test name
Test status
Simulation time 321152994022 ps
CPU time 273.5 seconds
Started Apr 28 02:51:42 PM PDT 24
Finished Apr 28 02:56:16 PM PDT 24
Peak memory 202320 kb
Host smart-55d10292-4507-4aea-8ccb-1445b5a1e5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246263556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1246263556
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.190388600
Short name T565
Test name
Test status
Simulation time 328582116815 ps
CPU time 719.52 seconds
Started Apr 28 02:51:42 PM PDT 24
Finished Apr 28 03:03:42 PM PDT 24
Peak memory 202392 kb
Host smart-c788c8e0-5efb-469c-bd04-6cfa5d03e4b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=190388600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.190388600
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3429153267
Short name T160
Test name
Test status
Simulation time 485767919258 ps
CPU time 138.46 seconds
Started Apr 28 02:51:37 PM PDT 24
Finished Apr 28 02:53:56 PM PDT 24
Peak memory 202396 kb
Host smart-6317dc1d-dba7-4744-b878-1adb063698aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429153267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3429153267
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3216603667
Short name T753
Test name
Test status
Simulation time 487372928495 ps
CPU time 413.71 seconds
Started Apr 28 02:51:41 PM PDT 24
Finished Apr 28 02:58:35 PM PDT 24
Peak memory 202248 kb
Host smart-e79e3292-dc82-4a87-b61e-a6e8bd8c0085
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216603667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3216603667
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3623398966
Short name T11
Test name
Test status
Simulation time 400525015853 ps
CPU time 261.94 seconds
Started Apr 28 02:51:43 PM PDT 24
Finished Apr 28 02:56:06 PM PDT 24
Peak memory 202300 kb
Host smart-4ce7094b-b93c-4570-a804-2193b0377630
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623398966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3623398966
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.172887143
Short name T519
Test name
Test status
Simulation time 208565913570 ps
CPU time 222.61 seconds
Started Apr 28 02:51:42 PM PDT 24
Finished Apr 28 02:55:25 PM PDT 24
Peak memory 202248 kb
Host smart-ae82139c-1283-4b0a-9062-479d5980c781
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172887143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
adc_ctrl_filters_wakeup_fixed.172887143
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.8628941
Short name T13
Test name
Test status
Simulation time 110927056554 ps
CPU time 424.37 seconds
Started Apr 28 02:51:48 PM PDT 24
Finished Apr 28 02:58:53 PM PDT 24
Peak memory 202728 kb
Host smart-e8938a0e-49e8-4c35-93f5-66f7b5582e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8628941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.8628941
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.3750709340
Short name T448
Test name
Test status
Simulation time 24342420507 ps
CPU time 14.34 seconds
Started Apr 28 02:51:48 PM PDT 24
Finished Apr 28 02:52:03 PM PDT 24
Peak memory 202144 kb
Host smart-140805c0-dc03-42c9-909f-463a53f3bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750709340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.3750709340
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1020258308
Short name T699
Test name
Test status
Simulation time 3793350898 ps
CPU time 3.02 seconds
Started Apr 28 02:51:49 PM PDT 24
Finished Apr 28 02:51:53 PM PDT 24
Peak memory 202148 kb
Host smart-c147606d-04cd-4967-9e21-7f51a2372a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020258308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1020258308
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2993938431
Short name T544
Test name
Test status
Simulation time 6056042709 ps
CPU time 3.87 seconds
Started Apr 28 02:51:37 PM PDT 24
Finished Apr 28 02:51:41 PM PDT 24
Peak memory 202140 kb
Host smart-7cacc72c-a39e-42b5-88d9-ade6e9ca2daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993938431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2993938431
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.2702641501
Short name T384
Test name
Test status
Simulation time 48649337040 ps
CPU time 110.49 seconds
Started Apr 28 02:51:47 PM PDT 24
Finished Apr 28 02:53:38 PM PDT 24
Peak memory 202320 kb
Host smart-2145b146-0969-4683-b469-6fcea2346f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702641501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.2702641501
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1614094656
Short name T224
Test name
Test status
Simulation time 103182583520 ps
CPU time 207.15 seconds
Started Apr 28 02:51:48 PM PDT 24
Finished Apr 28 02:55:16 PM PDT 24
Peak memory 217512 kb
Host smart-bd6bb209-5f0a-48a3-9dd5-a0110c0bb9f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614094656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1614094656
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2097820321
Short name T618
Test name
Test status
Simulation time 504807310 ps
CPU time 0.74 seconds
Started Apr 28 02:52:04 PM PDT 24
Finished Apr 28 02:52:06 PM PDT 24
Peak memory 202024 kb
Host smart-310d850b-f8c6-467b-af3b-b6a0d258e9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097820321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2097820321
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2173129538
Short name T767
Test name
Test status
Simulation time 184646399962 ps
CPU time 11.01 seconds
Started Apr 28 02:52:02 PM PDT 24
Finished Apr 28 02:52:13 PM PDT 24
Peak memory 202292 kb
Host smart-b1b9ec66-6763-455f-9966-a03674de5f7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173129538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2173129538
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.177818083
Short name T556
Test name
Test status
Simulation time 167477543121 ps
CPU time 419.7 seconds
Started Apr 28 02:51:57 PM PDT 24
Finished Apr 28 02:58:58 PM PDT 24
Peak memory 202376 kb
Host smart-648d564c-9f77-422a-867a-4890012f13ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177818083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.177818083
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.630813508
Short name T278
Test name
Test status
Simulation time 165428409004 ps
CPU time 71.02 seconds
Started Apr 28 02:51:55 PM PDT 24
Finished Apr 28 02:53:06 PM PDT 24
Peak memory 202320 kb
Host smart-977aece9-ed8a-4305-87df-1d39aed45895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630813508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.630813508
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3401200222
Short name T408
Test name
Test status
Simulation time 490686267688 ps
CPU time 1208.89 seconds
Started Apr 28 02:51:53 PM PDT 24
Finished Apr 28 03:12:02 PM PDT 24
Peak memory 202176 kb
Host smart-24d5e14a-4832-46ec-be75-3aa1782c6c7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401200222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3401200222
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3152314785
Short name T584
Test name
Test status
Simulation time 162681764496 ps
CPU time 93.51 seconds
Started Apr 28 02:51:53 PM PDT 24
Finished Apr 28 02:53:28 PM PDT 24
Peak memory 202304 kb
Host smart-23b2471d-5a6f-4a81-960f-14adc82a1d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152314785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3152314785
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1296403887
Short name T520
Test name
Test status
Simulation time 161532222787 ps
CPU time 97.1 seconds
Started Apr 28 02:51:52 PM PDT 24
Finished Apr 28 02:53:29 PM PDT 24
Peak memory 202252 kb
Host smart-e49a145e-53e2-40df-be61-32b0b47f7bdb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296403887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1296403887
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3871331874
Short name T347
Test name
Test status
Simulation time 190745701478 ps
CPU time 431.13 seconds
Started Apr 28 02:51:54 PM PDT 24
Finished Apr 28 02:59:05 PM PDT 24
Peak memory 202292 kb
Host smart-8bee11e0-956d-46fd-9a0e-9bbf479d15dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871331874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3871331874
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3016928436
Short name T740
Test name
Test status
Simulation time 398551367254 ps
CPU time 967.18 seconds
Started Apr 28 02:51:57 PM PDT 24
Finished Apr 28 03:08:05 PM PDT 24
Peak memory 202276 kb
Host smart-92798c20-35a0-458a-9078-2c34ce4a80e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016928436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3016928436
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.586015663
Short name T526
Test name
Test status
Simulation time 31848955589 ps
CPU time 79.92 seconds
Started Apr 28 02:51:59 PM PDT 24
Finished Apr 28 02:53:19 PM PDT 24
Peak memory 202128 kb
Host smart-e415e775-19e7-4843-b214-d36aae877069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586015663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.586015663
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.906055804
Short name T791
Test name
Test status
Simulation time 4493092848 ps
CPU time 11.96 seconds
Started Apr 28 02:51:58 PM PDT 24
Finished Apr 28 02:52:10 PM PDT 24
Peak memory 202044 kb
Host smart-e2ab1262-8099-412d-91e0-5981225ebb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906055804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.906055804
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.492416020
Short name T533
Test name
Test status
Simulation time 5810613029 ps
CPU time 13.79 seconds
Started Apr 28 02:51:54 PM PDT 24
Finished Apr 28 02:52:08 PM PDT 24
Peak memory 202072 kb
Host smart-20cb6107-bc6c-42d8-b879-04c7e504aa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492416020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.492416020
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3780719244
Short name T322
Test name
Test status
Simulation time 737801158096 ps
CPU time 345.61 seconds
Started Apr 28 02:52:05 PM PDT 24
Finished Apr 28 02:57:51 PM PDT 24
Peak memory 212704 kb
Host smart-08994f7a-a3b4-464c-b5bf-fc70af1ee97f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780719244 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3780719244
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.709360796
Short name T402
Test name
Test status
Simulation time 438194986 ps
CPU time 1.65 seconds
Started Apr 28 02:45:42 PM PDT 24
Finished Apr 28 02:45:45 PM PDT 24
Peak memory 201968 kb
Host smart-b245ec25-645c-4fa0-b19e-533d4f9073da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709360796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.709360796
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.368729824
Short name T246
Test name
Test status
Simulation time 165209687323 ps
CPU time 147.36 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:48:10 PM PDT 24
Peak memory 202228 kb
Host smart-51ad8070-3527-4a87-afe1-ea843a46502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368729824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.368729824
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.1816970943
Short name T504
Test name
Test status
Simulation time 495788964760 ps
CPU time 336.45 seconds
Started Apr 28 02:45:42 PM PDT 24
Finished Apr 28 02:51:20 PM PDT 24
Peak memory 202300 kb
Host smart-d8c96f48-35fa-4444-af9c-240052c76764
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816970943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.1816970943
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3544152208
Short name T269
Test name
Test status
Simulation time 328542443088 ps
CPU time 176.56 seconds
Started Apr 28 02:45:37 PM PDT 24
Finished Apr 28 02:48:35 PM PDT 24
Peak memory 202344 kb
Host smart-f9e0fcd1-a8f6-46fa-aa59-f06f977e17ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544152208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3544152208
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3311229691
Short name T575
Test name
Test status
Simulation time 493025848330 ps
CPU time 1188.78 seconds
Started Apr 28 02:45:36 PM PDT 24
Finished Apr 28 03:05:26 PM PDT 24
Peak memory 202260 kb
Host smart-69611d77-de51-4f4d-aece-fadcaf29f679
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311229691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3311229691
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.909910935
Short name T436
Test name
Test status
Simulation time 401501868976 ps
CPU time 228.11 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:49:48 PM PDT 24
Peak memory 202280 kb
Host smart-896a7a94-5f3c-4c97-b80d-fa061175330e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909910935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.909910935
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.122663176
Short name T362
Test name
Test status
Simulation time 134886095066 ps
CPU time 708.13 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:57:31 PM PDT 24
Peak memory 202620 kb
Host smart-16df8c80-3c56-4e1f-b467-4369789ece4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122663176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.122663176
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1955877460
Short name T399
Test name
Test status
Simulation time 33140074761 ps
CPU time 38.35 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:46:32 PM PDT 24
Peak memory 202112 kb
Host smart-335eccfc-9426-44a1-a706-8e7c6abd33f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955877460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1955877460
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.1849952767
Short name T546
Test name
Test status
Simulation time 5185418437 ps
CPU time 6.57 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:45:59 PM PDT 24
Peak memory 202080 kb
Host smart-00f67c55-eade-4984-ba1f-2c3153de908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849952767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.1849952767
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2191008159
Short name T57
Test name
Test status
Simulation time 7687853796 ps
CPU time 17.28 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:46:10 PM PDT 24
Peak memory 218892 kb
Host smart-5565d24e-e861-43c6-b81a-ea168d570bf4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191008159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2191008159
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.2150432892
Short name T522
Test name
Test status
Simulation time 6087368796 ps
CPU time 4.5 seconds
Started Apr 28 02:45:37 PM PDT 24
Finished Apr 28 02:45:44 PM PDT 24
Peak memory 202136 kb
Host smart-8e660387-909d-4eb9-b614-9502cd07c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150432892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.2150432892
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1696324308
Short name T487
Test name
Test status
Simulation time 337806565447 ps
CPU time 373.69 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:51:57 PM PDT 24
Peak memory 202368 kb
Host smart-65daa6a7-b195-4790-bae0-85e83bbe8dae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696324308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1696324308
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1962532194
Short name T345
Test name
Test status
Simulation time 84141934441 ps
CPU time 126.79 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:47:50 PM PDT 24
Peak memory 212020 kb
Host smart-ea488de5-a408-4f1d-b4d0-02449ba03329
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962532194 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1962532194
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2977825304
Short name T661
Test name
Test status
Simulation time 471564172 ps
CPU time 0.7 seconds
Started Apr 28 02:52:09 PM PDT 24
Finished Apr 28 02:52:11 PM PDT 24
Peak memory 201996 kb
Host smart-05daeccd-29ee-4af3-a9ed-b3dfdb7a2e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977825304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2977825304
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1658255749
Short name T576
Test name
Test status
Simulation time 504393024992 ps
CPU time 775.37 seconds
Started Apr 28 02:52:05 PM PDT 24
Finished Apr 28 03:05:01 PM PDT 24
Peak memory 202328 kb
Host smart-8f324935-f33b-4769-b0c2-9e6427a95311
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658255749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1658255749
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3130386091
Short name T320
Test name
Test status
Simulation time 323448043291 ps
CPU time 485.54 seconds
Started Apr 28 02:52:04 PM PDT 24
Finished Apr 28 03:00:11 PM PDT 24
Peak memory 202308 kb
Host smart-81c2591a-9a0e-42c2-9683-7bce2e646b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130386091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3130386091
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.394925077
Short name T83
Test name
Test status
Simulation time 485140324670 ps
CPU time 1185.52 seconds
Started Apr 28 02:52:04 PM PDT 24
Finished Apr 28 03:11:50 PM PDT 24
Peak memory 202296 kb
Host smart-ce3bbb0f-98db-4666-967c-e05048d2de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394925077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.394925077
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.661401490
Short name T721
Test name
Test status
Simulation time 167011133028 ps
CPU time 210.03 seconds
Started Apr 28 02:52:08 PM PDT 24
Finished Apr 28 02:55:39 PM PDT 24
Peak memory 202280 kb
Host smart-639169c7-e888-4107-94f0-38fce2175573
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=661401490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.661401490
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3804844529
Short name T156
Test name
Test status
Simulation time 328228860320 ps
CPU time 206.08 seconds
Started Apr 28 02:52:04 PM PDT 24
Finished Apr 28 02:55:31 PM PDT 24
Peak memory 202340 kb
Host smart-6ced19de-35ba-43a1-b87e-32df569c1ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804844529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3804844529
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3055810042
Short name T469
Test name
Test status
Simulation time 479254243156 ps
CPU time 325.2 seconds
Started Apr 28 02:52:03 PM PDT 24
Finished Apr 28 02:57:29 PM PDT 24
Peak memory 202204 kb
Host smart-bda5fc67-bc5b-4987-9a84-060a3a0941d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055810042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3055810042
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.230163530
Short name T146
Test name
Test status
Simulation time 344972733741 ps
CPU time 402.7 seconds
Started Apr 28 02:52:08 PM PDT 24
Finished Apr 28 02:58:51 PM PDT 24
Peak memory 202296 kb
Host smart-d062a9d7-3b0c-4076-a4b0-1cb451d669b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230163530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.230163530
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1403064364
Short name T366
Test name
Test status
Simulation time 399035271436 ps
CPU time 467.09 seconds
Started Apr 28 02:52:04 PM PDT 24
Finished Apr 28 02:59:52 PM PDT 24
Peak memory 202312 kb
Host smart-e0c53c68-9b96-4e8a-b139-6fe647766425
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403064364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1403064364
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2366096434
Short name T636
Test name
Test status
Simulation time 77291169082 ps
CPU time 280.56 seconds
Started Apr 28 02:52:08 PM PDT 24
Finished Apr 28 02:56:49 PM PDT 24
Peak memory 202720 kb
Host smart-893f547a-3fa4-48a6-b4fd-c00a6c4f6cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366096434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2366096434
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2952571724
Short name T659
Test name
Test status
Simulation time 25711475384 ps
CPU time 15.97 seconds
Started Apr 28 02:52:08 PM PDT 24
Finished Apr 28 02:52:25 PM PDT 24
Peak memory 202100 kb
Host smart-857dff84-19ed-44be-95b9-b95edfc6c741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952571724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2952571724
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1650599509
Short name T704
Test name
Test status
Simulation time 4801936494 ps
CPU time 11.22 seconds
Started Apr 28 02:52:07 PM PDT 24
Finished Apr 28 02:52:19 PM PDT 24
Peak memory 202160 kb
Host smart-168b4c1b-1e16-4b15-8ca9-3a6ab3804248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650599509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1650599509
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3771436078
Short name T181
Test name
Test status
Simulation time 5830535052 ps
CPU time 4.22 seconds
Started Apr 28 02:52:08 PM PDT 24
Finished Apr 28 02:52:13 PM PDT 24
Peak memory 202108 kb
Host smart-95741749-6143-45bd-b9ba-9fb0b4cd02f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771436078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3771436078
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.193188338
Short name T550
Test name
Test status
Simulation time 37239563785 ps
CPU time 110.61 seconds
Started Apr 28 02:52:08 PM PDT 24
Finished Apr 28 02:53:59 PM PDT 24
Peak memory 218828 kb
Host smart-3a418918-cffb-42b7-af7d-ae45a70967e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193188338 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.193188338
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.1328681976
Short name T95
Test name
Test status
Simulation time 356926727 ps
CPU time 1.03 seconds
Started Apr 28 02:52:23 PM PDT 24
Finished Apr 28 02:52:25 PM PDT 24
Peak memory 201976 kb
Host smart-a22dea00-d2e2-4511-a361-fef0806159d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328681976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.1328681976
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1813592585
Short name T750
Test name
Test status
Simulation time 547798775505 ps
CPU time 134.41 seconds
Started Apr 28 02:52:27 PM PDT 24
Finished Apr 28 02:54:42 PM PDT 24
Peak memory 202292 kb
Host smart-1668aa41-74d2-4c9c-925a-897bbf747568
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813592585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1813592585
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1331563164
Short name T105
Test name
Test status
Simulation time 325909544519 ps
CPU time 185.01 seconds
Started Apr 28 02:52:27 PM PDT 24
Finished Apr 28 02:55:33 PM PDT 24
Peak memory 202284 kb
Host smart-1c110148-2dd5-4b40-9133-9707505aec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331563164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1331563164
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1797254626
Short name T579
Test name
Test status
Simulation time 318498186085 ps
CPU time 191.91 seconds
Started Apr 28 02:52:14 PM PDT 24
Finished Apr 28 02:55:27 PM PDT 24
Peak memory 202304 kb
Host smart-09cd5869-8bfe-4164-a01f-ff98b1f80784
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797254626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1797254626
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3970063640
Short name T276
Test name
Test status
Simulation time 506493963318 ps
CPU time 94.21 seconds
Started Apr 28 02:52:13 PM PDT 24
Finished Apr 28 02:53:48 PM PDT 24
Peak memory 202392 kb
Host smart-09467113-d0ad-4ab8-80f5-d52017479ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970063640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3970063640
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2094451593
Short name T478
Test name
Test status
Simulation time 489720008893 ps
CPU time 1161.51 seconds
Started Apr 28 02:52:14 PM PDT 24
Finished Apr 28 03:11:36 PM PDT 24
Peak memory 202316 kb
Host smart-b27c5fb5-6788-4610-904c-f507be746916
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094451593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2094451593
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2907937287
Short name T798
Test name
Test status
Simulation time 578911149286 ps
CPU time 385.91 seconds
Started Apr 28 02:52:12 PM PDT 24
Finished Apr 28 02:58:39 PM PDT 24
Peak memory 202380 kb
Host smart-b7d333b2-8b58-4574-911c-526aea8f5913
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907937287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2907937287
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.834389981
Short name T7
Test name
Test status
Simulation time 615054159843 ps
CPU time 174.57 seconds
Started Apr 28 02:52:18 PM PDT 24
Finished Apr 28 02:55:13 PM PDT 24
Peak memory 202328 kb
Host smart-486ee350-c393-4305-bf4d-158abeb45545
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834389981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.834389981
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3736268011
Short name T748
Test name
Test status
Simulation time 107660005995 ps
CPU time 546.43 seconds
Started Apr 28 02:52:28 PM PDT 24
Finished Apr 28 03:01:35 PM PDT 24
Peak memory 202636 kb
Host smart-80105b2f-c6eb-4238-a91e-942c5016deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736268011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3736268011
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.2785520064
Short name T542
Test name
Test status
Simulation time 47070943291 ps
CPU time 27.56 seconds
Started Apr 28 02:52:27 PM PDT 24
Finished Apr 28 02:52:55 PM PDT 24
Peak memory 202116 kb
Host smart-637dc037-5fae-490b-af75-0956c952724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785520064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.2785520064
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1707456262
Short name T593
Test name
Test status
Simulation time 4048352578 ps
CPU time 5.8 seconds
Started Apr 28 02:52:17 PM PDT 24
Finished Apr 28 02:52:23 PM PDT 24
Peak memory 202160 kb
Host smart-66d4b24f-c1cf-4777-9d7d-e73705d49162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707456262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1707456262
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1738846993
Short name T496
Test name
Test status
Simulation time 5925100489 ps
CPU time 4.01 seconds
Started Apr 28 02:52:08 PM PDT 24
Finished Apr 28 02:52:13 PM PDT 24
Peak memory 202044 kb
Host smart-587bca48-691e-467e-a7a2-ab22c0c7d5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738846993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1738846993
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2321644668
Short name T789
Test name
Test status
Simulation time 292655608842 ps
CPU time 920.21 seconds
Started Apr 28 02:52:25 PM PDT 24
Finished Apr 28 03:07:46 PM PDT 24
Peak memory 202640 kb
Host smart-1b5c9a38-5e94-404c-883a-b662ba696c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321644668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2321644668
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2192330648
Short name T389
Test name
Test status
Simulation time 418072899 ps
CPU time 1.59 seconds
Started Apr 28 02:52:37 PM PDT 24
Finished Apr 28 02:52:39 PM PDT 24
Peak memory 201992 kb
Host smart-b6100378-150e-4b99-8cb5-f307f5c1d70f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192330648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2192330648
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2017761332
Short name T653
Test name
Test status
Simulation time 158801334365 ps
CPU time 22.1 seconds
Started Apr 28 02:52:27 PM PDT 24
Finished Apr 28 02:52:50 PM PDT 24
Peak memory 202316 kb
Host smart-072cfb4d-1e92-4820-9221-6758e87b0c6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017761332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2017761332
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3207884053
Short name T783
Test name
Test status
Simulation time 487359957531 ps
CPU time 531.89 seconds
Started Apr 28 02:52:29 PM PDT 24
Finished Apr 28 03:01:21 PM PDT 24
Peak memory 202396 kb
Host smart-bfad4900-b704-42f9-82cf-6439d9610f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207884053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3207884053
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2135373595
Short name T414
Test name
Test status
Simulation time 480474749441 ps
CPU time 1057.78 seconds
Started Apr 28 02:52:33 PM PDT 24
Finished Apr 28 03:10:12 PM PDT 24
Peak memory 202280 kb
Host smart-15c85238-6d20-44d6-8282-a0248df5e7eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135373595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2135373595
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.4029595944
Short name T136
Test name
Test status
Simulation time 489381088408 ps
CPU time 946.24 seconds
Started Apr 28 02:52:24 PM PDT 24
Finished Apr 28 03:08:11 PM PDT 24
Peak memory 202384 kb
Host smart-3b5796db-cf5e-417c-b27c-989a7b3f48c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029595944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.4029595944
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.4113831680
Short name T642
Test name
Test status
Simulation time 493503981819 ps
CPU time 156.56 seconds
Started Apr 28 02:52:24 PM PDT 24
Finished Apr 28 02:55:01 PM PDT 24
Peak memory 202368 kb
Host smart-947de8f3-9d79-4c5a-af3d-e1c211d3db12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113831680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.4113831680
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4110725694
Short name T599
Test name
Test status
Simulation time 619095102391 ps
CPU time 197.28 seconds
Started Apr 28 02:52:27 PM PDT 24
Finished Apr 28 02:55:45 PM PDT 24
Peak memory 202300 kb
Host smart-2c0bb593-08d2-47a5-aa86-01841a6b5bf1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110725694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.4110725694
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2630397641
Short name T357
Test name
Test status
Simulation time 95641662030 ps
CPU time 358.45 seconds
Started Apr 28 02:52:34 PM PDT 24
Finished Apr 28 02:58:33 PM PDT 24
Peak memory 202712 kb
Host smart-60e278b9-cc99-43d9-b06b-03c2fc1818a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630397641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2630397641
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3857386357
Short name T477
Test name
Test status
Simulation time 32079048886 ps
CPU time 75.96 seconds
Started Apr 28 02:52:35 PM PDT 24
Finished Apr 28 02:53:51 PM PDT 24
Peak memory 202164 kb
Host smart-433347bc-4e97-4468-bfb2-6f0b7755e91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857386357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3857386357
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2609088985
Short name T447
Test name
Test status
Simulation time 4310733204 ps
CPU time 10.55 seconds
Started Apr 28 02:52:30 PM PDT 24
Finished Apr 28 02:52:41 PM PDT 24
Peak memory 202148 kb
Host smart-c64f743c-9199-4044-881a-9ff8e3380509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609088985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2609088985
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2712762249
Short name T403
Test name
Test status
Simulation time 5703037064 ps
CPU time 13.61 seconds
Started Apr 28 02:52:23 PM PDT 24
Finished Apr 28 02:52:37 PM PDT 24
Peak memory 202104 kb
Host smart-090ab263-af28-4fcf-ac4a-5d07d9450749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712762249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2712762249
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.2301594390
Short name T267
Test name
Test status
Simulation time 214847531423 ps
CPU time 467.07 seconds
Started Apr 28 02:52:35 PM PDT 24
Finished Apr 28 03:00:22 PM PDT 24
Peak memory 202356 kb
Host smart-78efd841-89d1-4e40-952a-0b368f48b44e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301594390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.2301594390
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.61216452
Short name T498
Test name
Test status
Simulation time 109850405495 ps
CPU time 207.51 seconds
Started Apr 28 02:52:33 PM PDT 24
Finished Apr 28 02:56:01 PM PDT 24
Peak memory 211116 kb
Host smart-f68ccde6-9395-4749-b58b-d0a4683af529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61216452 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.61216452
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.149919594
Short name T434
Test name
Test status
Simulation time 492010741 ps
CPU time 1.64 seconds
Started Apr 28 02:52:43 PM PDT 24
Finished Apr 28 02:52:45 PM PDT 24
Peak memory 201992 kb
Host smart-b9a43ad4-4722-49bb-ab9c-cf1175ad386a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149919594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.149919594
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2196967884
Short name T226
Test name
Test status
Simulation time 536278732034 ps
CPU time 783.91 seconds
Started Apr 28 02:52:44 PM PDT 24
Finished Apr 28 03:05:48 PM PDT 24
Peak memory 202356 kb
Host smart-5750fa03-6891-4ff7-af60-80486e0b7c06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196967884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2196967884
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1835831627
Short name T92
Test name
Test status
Simulation time 330820989119 ps
CPU time 133.1 seconds
Started Apr 28 02:52:39 PM PDT 24
Finished Apr 28 02:54:52 PM PDT 24
Peak memory 202280 kb
Host smart-b3ec2f0d-c9af-495e-8680-d45644171a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835831627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1835831627
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.368037562
Short name T629
Test name
Test status
Simulation time 498923410475 ps
CPU time 416.79 seconds
Started Apr 28 02:52:38 PM PDT 24
Finished Apr 28 02:59:36 PM PDT 24
Peak memory 202304 kb
Host smart-321f52ac-029c-459a-8d84-1c82389bd4fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=368037562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrup
t_fixed.368037562
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3524131130
Short name T209
Test name
Test status
Simulation time 498832505377 ps
CPU time 1070.54 seconds
Started Apr 28 02:52:38 PM PDT 24
Finished Apr 28 03:10:29 PM PDT 24
Peak memory 202396 kb
Host smart-6cc3fbc0-05c5-4d1f-a29b-e6788264b6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524131130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3524131130
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3386348384
Short name T756
Test name
Test status
Simulation time 499399970540 ps
CPU time 260.17 seconds
Started Apr 28 02:52:38 PM PDT 24
Finished Apr 28 02:56:59 PM PDT 24
Peak memory 202276 kb
Host smart-97e35d51-31a5-435f-ae31-170fd9dbfdd8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386348384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3386348384
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3051627148
Short name T637
Test name
Test status
Simulation time 413826812282 ps
CPU time 988.79 seconds
Started Apr 28 02:52:42 PM PDT 24
Finished Apr 28 03:09:11 PM PDT 24
Peak memory 202288 kb
Host smart-5e4345c4-a8e3-4be1-a398-b1464b1d027c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051627148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3051627148
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.616071151
Short name T361
Test name
Test status
Simulation time 120361874177 ps
CPU time 583.39 seconds
Started Apr 28 02:52:43 PM PDT 24
Finished Apr 28 03:02:27 PM PDT 24
Peak memory 202616 kb
Host smart-db6045cd-c387-4807-80e9-be564fff46b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616071151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.616071151
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3959771182
Short name T645
Test name
Test status
Simulation time 47966820669 ps
CPU time 71.2 seconds
Started Apr 28 02:52:41 PM PDT 24
Finished Apr 28 02:53:53 PM PDT 24
Peak memory 202144 kb
Host smart-3bdee61a-51c5-43fd-84d7-55586fe4d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959771182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3959771182
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3236129789
Short name T553
Test name
Test status
Simulation time 4732640340 ps
CPU time 11.5 seconds
Started Apr 28 02:52:42 PM PDT 24
Finished Apr 28 02:52:54 PM PDT 24
Peak memory 202088 kb
Host smart-2cfe73a6-a5df-41b8-b168-a79614c5c856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236129789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3236129789
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1179894251
Short name T380
Test name
Test status
Simulation time 6126311388 ps
CPU time 4.6 seconds
Started Apr 28 02:52:40 PM PDT 24
Finished Apr 28 02:52:45 PM PDT 24
Peak memory 202116 kb
Host smart-737f8035-37e8-4339-bfe0-d186d77442d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179894251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1179894251
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.464909190
Short name T331
Test name
Test status
Simulation time 422413165120 ps
CPU time 521.21 seconds
Started Apr 28 02:52:41 PM PDT 24
Finished Apr 28 03:01:23 PM PDT 24
Peak memory 202304 kb
Host smart-22e2ce10-6ea5-476b-a901-a37f84c76377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464909190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
464909190
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.1227749760
Short name T43
Test name
Test status
Simulation time 284297261116 ps
CPU time 103.52 seconds
Started Apr 28 02:52:44 PM PDT 24
Finished Apr 28 02:54:28 PM PDT 24
Peak memory 211112 kb
Host smart-97c31f0c-550f-4e57-8936-75dce2845a36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227749760 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.1227749760
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.4179623314
Short name T557
Test name
Test status
Simulation time 521119802 ps
CPU time 0.96 seconds
Started Apr 28 02:53:00 PM PDT 24
Finished Apr 28 02:53:02 PM PDT 24
Peak memory 201924 kb
Host smart-009f1b14-c225-4971-ba42-7e30039e4093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179623314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.4179623314
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3658197944
Short name T290
Test name
Test status
Simulation time 169703059453 ps
CPU time 99.3 seconds
Started Apr 28 02:52:50 PM PDT 24
Finished Apr 28 02:54:30 PM PDT 24
Peak memory 202296 kb
Host smart-adaa28e6-087e-49a4-b492-a78646f39f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658197944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3658197944
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3840033363
Short name T711
Test name
Test status
Simulation time 158533519851 ps
CPU time 188.59 seconds
Started Apr 28 02:52:50 PM PDT 24
Finished Apr 28 02:55:59 PM PDT 24
Peak memory 202312 kb
Host smart-b1ff3a7d-f6bf-46b1-a245-8f3a392a72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840033363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3840033363
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3637564219
Short name T559
Test name
Test status
Simulation time 165570509396 ps
CPU time 338.2 seconds
Started Apr 28 02:52:48 PM PDT 24
Finished Apr 28 02:58:26 PM PDT 24
Peak memory 202308 kb
Host smart-78530d1c-9367-46bc-a929-4032cea18162
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637564219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3637564219
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1796667893
Short name T631
Test name
Test status
Simulation time 166642055610 ps
CPU time 100.09 seconds
Started Apr 28 02:52:44 PM PDT 24
Finished Apr 28 02:54:25 PM PDT 24
Peak memory 202220 kb
Host smart-69572b9c-03ce-4199-8da7-57dbb1f93234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796667893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1796667893
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2950970088
Short name T600
Test name
Test status
Simulation time 164757014388 ps
CPU time 374.54 seconds
Started Apr 28 02:52:42 PM PDT 24
Finished Apr 28 02:58:57 PM PDT 24
Peak memory 202304 kb
Host smart-cc224d07-e3cf-4a07-8c16-5cf44d132b53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950970088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2950970088
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2649375241
Short name T735
Test name
Test status
Simulation time 302847311669 ps
CPU time 748.6 seconds
Started Apr 28 02:52:48 PM PDT 24
Finished Apr 28 03:05:17 PM PDT 24
Peak memory 202316 kb
Host smart-34f6e071-2ed3-4c00-b2f7-0455aeb9f6c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649375241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2649375241
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3998186383
Short name T479
Test name
Test status
Simulation time 597489559980 ps
CPU time 1451.16 seconds
Started Apr 28 02:52:49 PM PDT 24
Finished Apr 28 03:17:01 PM PDT 24
Peak memory 202388 kb
Host smart-5614aa7d-b286-4d11-a51d-3501c0400506
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998186383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3998186383
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3397079117
Short name T698
Test name
Test status
Simulation time 81075846322 ps
CPU time 435.85 seconds
Started Apr 28 02:52:48 PM PDT 24
Finished Apr 28 03:00:04 PM PDT 24
Peak memory 202656 kb
Host smart-752339f7-bd65-4c0e-b5c9-c789158a807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397079117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3397079117
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1778014933
Short name T728
Test name
Test status
Simulation time 28504340336 ps
CPU time 62.18 seconds
Started Apr 28 02:52:49 PM PDT 24
Finished Apr 28 02:53:52 PM PDT 24
Peak memory 202092 kb
Host smart-ebdf30c2-0bbe-47ec-9764-71e43f6a856e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778014933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1778014933
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2370078607
Short name T460
Test name
Test status
Simulation time 3440841417 ps
CPU time 2.19 seconds
Started Apr 28 02:52:47 PM PDT 24
Finished Apr 28 02:52:50 PM PDT 24
Peak memory 202000 kb
Host smart-4533084d-aed1-4822-88c3-b3e3d4cb5cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370078607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2370078607
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1304614960
Short name T761
Test name
Test status
Simulation time 5832137819 ps
CPU time 8.21 seconds
Started Apr 28 02:52:45 PM PDT 24
Finished Apr 28 02:52:53 PM PDT 24
Peak memory 202068 kb
Host smart-0c477c1e-2578-461c-8cdf-fb36a7a3a354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304614960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1304614960
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3143273490
Short name T294
Test name
Test status
Simulation time 658002784066 ps
CPU time 366.65 seconds
Started Apr 28 02:52:53 PM PDT 24
Finished Apr 28 02:59:01 PM PDT 24
Peak memory 202392 kb
Host smart-48e8f0d5-5775-41f4-86af-5d59fa9d4885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143273490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3143273490
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1715570903
Short name T485
Test name
Test status
Simulation time 14034654286 ps
CPU time 40.58 seconds
Started Apr 28 02:52:49 PM PDT 24
Finished Apr 28 02:53:30 PM PDT 24
Peak memory 211092 kb
Host smart-0b6dbdcd-f9a1-4643-8f05-afd71649bb84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715570903 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1715570903
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2265663600
Short name T596
Test name
Test status
Simulation time 358981756 ps
CPU time 1.02 seconds
Started Apr 28 02:53:14 PM PDT 24
Finished Apr 28 02:53:15 PM PDT 24
Peak memory 202012 kb
Host smart-b73894af-3433-4816-9112-4bce8db6a66b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265663600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2265663600
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2315472099
Short name T552
Test name
Test status
Simulation time 168243626068 ps
CPU time 359.39 seconds
Started Apr 28 02:52:59 PM PDT 24
Finished Apr 28 02:58:59 PM PDT 24
Peak memory 202252 kb
Host smart-2a471cc3-37d0-45f3-9a33-1bd4697b9abe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315472099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2315472099
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1070591781
Short name T445
Test name
Test status
Simulation time 324940001583 ps
CPU time 738.92 seconds
Started Apr 28 02:52:59 PM PDT 24
Finished Apr 28 03:05:18 PM PDT 24
Peak memory 202300 kb
Host smart-b8afbc9b-cfce-4261-9ca1-3f4797cda754
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070591781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1070591781
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1787423672
Short name T535
Test name
Test status
Simulation time 328925868897 ps
CPU time 754.86 seconds
Started Apr 28 02:52:59 PM PDT 24
Finished Apr 28 03:05:35 PM PDT 24
Peak memory 202300 kb
Host smart-932967b8-cbb8-47ca-9c4f-5fd48555a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787423672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1787423672
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1136428439
Short name T681
Test name
Test status
Simulation time 496250689129 ps
CPU time 850.82 seconds
Started Apr 28 02:53:02 PM PDT 24
Finished Apr 28 03:07:13 PM PDT 24
Peak memory 202276 kb
Host smart-8f765590-a7f7-4cae-abcb-a248203e0932
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136428439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1136428439
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1494974664
Short name T173
Test name
Test status
Simulation time 519363585095 ps
CPU time 308.02 seconds
Started Apr 28 02:53:00 PM PDT 24
Finished Apr 28 02:58:09 PM PDT 24
Peak memory 202292 kb
Host smart-faa185a7-0b6c-4e8b-8ac0-9a2834ff6b06
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494974664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1494974664
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1368399796
Short name T416
Test name
Test status
Simulation time 196946004827 ps
CPU time 191.37 seconds
Started Apr 28 02:52:59 PM PDT 24
Finished Apr 28 02:56:11 PM PDT 24
Peak memory 202292 kb
Host smart-bf63da85-3755-499a-947e-20ea524314f1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368399796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1368399796
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.401927183
Short name T360
Test name
Test status
Simulation time 90217345676 ps
CPU time 538.33 seconds
Started Apr 28 02:53:04 PM PDT 24
Finished Apr 28 03:02:03 PM PDT 24
Peak memory 202712 kb
Host smart-44927576-202a-4f9d-9a2e-79a262492330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401927183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.401927183
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3530764424
Short name T99
Test name
Test status
Simulation time 39293513878 ps
CPU time 88.69 seconds
Started Apr 28 02:53:05 PM PDT 24
Finished Apr 28 02:54:35 PM PDT 24
Peak memory 202164 kb
Host smart-7598a10e-641c-4a20-b7fd-376dba452573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530764424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3530764424
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4285622216
Short name T394
Test name
Test status
Simulation time 4983698954 ps
CPU time 4.06 seconds
Started Apr 28 02:53:05 PM PDT 24
Finished Apr 28 02:53:10 PM PDT 24
Peak memory 202120 kb
Host smart-a4ed8011-7829-4e5e-b6a0-9ef47f1eff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285622216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4285622216
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2826761035
Short name T490
Test name
Test status
Simulation time 5680926711 ps
CPU time 5.46 seconds
Started Apr 28 02:53:00 PM PDT 24
Finished Apr 28 02:53:06 PM PDT 24
Peak memory 202100 kb
Host smart-4d792ecc-a975-441a-a708-80b45fb386cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826761035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2826761035
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1570421617
Short name T365
Test name
Test status
Simulation time 421784244724 ps
CPU time 1263.37 seconds
Started Apr 28 02:53:13 PM PDT 24
Finished Apr 28 03:14:17 PM PDT 24
Peak memory 202732 kb
Host smart-0a491a0a-6117-4aef-b547-9f98fbcd9063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570421617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1570421617
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.164799003
Short name T193
Test name
Test status
Simulation time 300515186483 ps
CPU time 190.1 seconds
Started Apr 28 02:53:08 PM PDT 24
Finished Apr 28 02:56:19 PM PDT 24
Peak memory 202788 kb
Host smart-15bb2ee9-f056-4969-8309-c773f51adefb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164799003 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.164799003
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2428632828
Short name T683
Test name
Test status
Simulation time 500142993 ps
CPU time 0.68 seconds
Started Apr 28 02:53:18 PM PDT 24
Finished Apr 28 02:53:19 PM PDT 24
Peak memory 202004 kb
Host smart-118007a0-1c8a-41d1-a1e3-bcf7a9a1e7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428632828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2428632828
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1128775654
Short name T326
Test name
Test status
Simulation time 342726036979 ps
CPU time 423.02 seconds
Started Apr 28 02:53:15 PM PDT 24
Finished Apr 28 03:00:18 PM PDT 24
Peak memory 202300 kb
Host smart-026c9389-25fb-4883-b786-d80bb3c86d49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128775654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1128775654
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3436691743
Short name T89
Test name
Test status
Simulation time 328664685270 ps
CPU time 215.05 seconds
Started Apr 28 02:53:08 PM PDT 24
Finished Apr 28 02:56:44 PM PDT 24
Peak memory 202364 kb
Host smart-2ac76492-f47a-4811-bce3-8df957a27d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436691743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3436691743
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.754336840
Short name T502
Test name
Test status
Simulation time 329657906704 ps
CPU time 777.34 seconds
Started Apr 28 02:53:08 PM PDT 24
Finished Apr 28 03:06:06 PM PDT 24
Peak memory 202284 kb
Host smart-722766fc-9aa0-4086-a4c1-67dba451b24d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=754336840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.754336840
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2429621589
Short name T107
Test name
Test status
Simulation time 326864541327 ps
CPU time 787.94 seconds
Started Apr 28 02:53:10 PM PDT 24
Finished Apr 28 03:06:18 PM PDT 24
Peak memory 202304 kb
Host smart-b19ffac4-4b2f-43b3-bee5-f0d85a346901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429621589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2429621589
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1804509547
Short name T590
Test name
Test status
Simulation time 163328996450 ps
CPU time 100.66 seconds
Started Apr 28 02:53:09 PM PDT 24
Finished Apr 28 02:54:50 PM PDT 24
Peak memory 202276 kb
Host smart-596c0122-288b-4759-84b2-91572efd201d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804509547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1804509547
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.4196350952
Short name T350
Test name
Test status
Simulation time 543068076468 ps
CPU time 1257.04 seconds
Started Apr 28 02:53:13 PM PDT 24
Finished Apr 28 03:14:11 PM PDT 24
Peak memory 202380 kb
Host smart-3f3bfcbf-bd93-4411-9b43-e7d305b273c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196350952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.4196350952
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.964369054
Short name T4
Test name
Test status
Simulation time 402862471381 ps
CPU time 156.25 seconds
Started Apr 28 02:53:13 PM PDT 24
Finished Apr 28 02:55:50 PM PDT 24
Peak memory 202272 kb
Host smart-13cc206d-c86a-44e1-a242-41bcbdcb7f70
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964369054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.964369054
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1941209138
Short name T800
Test name
Test status
Simulation time 136353135405 ps
CPU time 468.61 seconds
Started Apr 28 02:53:14 PM PDT 24
Finished Apr 28 03:01:03 PM PDT 24
Peak memory 202684 kb
Host smart-75c56841-eb8c-415f-adc7-b3819eb4faee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941209138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1941209138
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.415090167
Short name T437
Test name
Test status
Simulation time 27756940437 ps
CPU time 41.7 seconds
Started Apr 28 02:53:14 PM PDT 24
Finished Apr 28 02:53:57 PM PDT 24
Peak memory 202100 kb
Host smart-4a0e4e1c-4bdc-489d-8407-b1f6b17137e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415090167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.415090167
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3751769969
Short name T390
Test name
Test status
Simulation time 4888188819 ps
CPU time 13.37 seconds
Started Apr 28 02:53:24 PM PDT 24
Finished Apr 28 02:53:38 PM PDT 24
Peak memory 202020 kb
Host smart-82aeba01-144a-47b4-9a4c-a5365e73a287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751769969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3751769969
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1765347459
Short name T441
Test name
Test status
Simulation time 5721817231 ps
CPU time 4.33 seconds
Started Apr 28 02:53:08 PM PDT 24
Finished Apr 28 02:53:12 PM PDT 24
Peak memory 202116 kb
Host smart-0b18a84c-68fc-4820-89fe-6bf080ef6b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765347459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1765347459
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2920896953
Short name T159
Test name
Test status
Simulation time 326371096273 ps
CPU time 115.52 seconds
Started Apr 28 02:53:18 PM PDT 24
Finished Apr 28 02:55:14 PM PDT 24
Peak memory 202296 kb
Host smart-6303fb87-4dd1-4445-938d-d97e89f017c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920896953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2920896953
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2860529252
Short name T773
Test name
Test status
Simulation time 485157348 ps
CPU time 1.17 seconds
Started Apr 28 02:53:29 PM PDT 24
Finished Apr 28 02:53:31 PM PDT 24
Peak memory 201992 kb
Host smart-7df9674d-298c-493d-9157-56a762ad9ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860529252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2860529252
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.261709676
Short name T614
Test name
Test status
Simulation time 171581811433 ps
CPU time 199.37 seconds
Started Apr 28 02:53:23 PM PDT 24
Finished Apr 28 02:56:43 PM PDT 24
Peak memory 202372 kb
Host smart-b86945b2-17ce-44b5-9107-c6cc23865c55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261709676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.261709676
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.9292751
Short name T633
Test name
Test status
Simulation time 335763876677 ps
CPU time 204.07 seconds
Started Apr 28 02:53:24 PM PDT 24
Finished Apr 28 02:56:48 PM PDT 24
Peak memory 202388 kb
Host smart-8d7b8f8f-bb5f-495f-974c-2bea4c96bcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9292751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.9292751
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4263983365
Short name T308
Test name
Test status
Simulation time 325033795128 ps
CPU time 730.39 seconds
Started Apr 28 02:53:18 PM PDT 24
Finished Apr 28 03:05:29 PM PDT 24
Peak memory 202356 kb
Host smart-64627baf-71d3-4cc1-85c7-0425dd61b2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263983365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4263983365
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3044903147
Short name T660
Test name
Test status
Simulation time 322715396053 ps
CPU time 336.09 seconds
Started Apr 28 02:53:24 PM PDT 24
Finished Apr 28 02:59:00 PM PDT 24
Peak memory 202308 kb
Host smart-5226eceb-71c5-4946-8592-7b39829d33a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044903147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3044903147
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2470922279
Short name T420
Test name
Test status
Simulation time 164177287755 ps
CPU time 287.28 seconds
Started Apr 28 02:53:18 PM PDT 24
Finished Apr 28 02:58:06 PM PDT 24
Peak memory 202320 kb
Host smart-fdd3f464-4f62-4a43-b9b1-864727334eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470922279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2470922279
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3445136151
Short name T656
Test name
Test status
Simulation time 328424865750 ps
CPU time 47.9 seconds
Started Apr 28 02:53:20 PM PDT 24
Finished Apr 28 02:54:08 PM PDT 24
Peak memory 202312 kb
Host smart-bdf27300-4696-4264-8af0-3db119e68234
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445136151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3445136151
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1237085398
Short name T264
Test name
Test status
Simulation time 405079831581 ps
CPU time 516.7 seconds
Started Apr 28 02:53:24 PM PDT 24
Finished Apr 28 03:02:01 PM PDT 24
Peak memory 202284 kb
Host smart-45949892-8735-4fa4-a84f-eb0bf6f93aac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237085398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1237085398
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2355503280
Short name T774
Test name
Test status
Simulation time 200066056578 ps
CPU time 38.87 seconds
Started Apr 28 02:53:28 PM PDT 24
Finished Apr 28 02:54:07 PM PDT 24
Peak memory 202284 kb
Host smart-601a5c23-9efe-4dd6-8cef-4590ff8cf7a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355503280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2355503280
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.90051230
Short name T197
Test name
Test status
Simulation time 77457943995 ps
CPU time 264.24 seconds
Started Apr 28 02:53:30 PM PDT 24
Finished Apr 28 02:57:55 PM PDT 24
Peak memory 202684 kb
Host smart-b7896197-101a-4d4c-9e74-327c79ec5683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90051230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.90051230
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.267576756
Short name T79
Test name
Test status
Simulation time 43978158182 ps
CPU time 28.94 seconds
Started Apr 28 02:53:31 PM PDT 24
Finished Apr 28 02:54:00 PM PDT 24
Peak memory 202036 kb
Host smart-2bcdccb9-3a36-4d13-b8b7-5597df2ac06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267576756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.267576756
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.928396102
Short name T82
Test name
Test status
Simulation time 4550023670 ps
CPU time 10.65 seconds
Started Apr 28 02:53:24 PM PDT 24
Finished Apr 28 02:53:35 PM PDT 24
Peak memory 202136 kb
Host smart-adbe0214-6854-4fe8-bff7-5ba0c2c92fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928396102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.928396102
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2099397761
Short name T425
Test name
Test status
Simulation time 6014894662 ps
CPU time 4.33 seconds
Started Apr 28 02:53:18 PM PDT 24
Finished Apr 28 02:53:23 PM PDT 24
Peak memory 202152 kb
Host smart-4599971e-e1ba-41a9-aa54-ca581d523ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099397761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2099397761
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3155088316
Short name T682
Test name
Test status
Simulation time 42205779234 ps
CPU time 131.41 seconds
Started Apr 28 02:53:35 PM PDT 24
Finished Apr 28 02:55:47 PM PDT 24
Peak memory 219076 kb
Host smart-89c8c9e4-35c2-42b8-808b-0826f92990c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155088316 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3155088316
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1273264686
Short name T770
Test name
Test status
Simulation time 468792410 ps
CPU time 1.35 seconds
Started Apr 28 02:53:48 PM PDT 24
Finished Apr 28 02:53:50 PM PDT 24
Peak memory 202004 kb
Host smart-62c2bbd0-b685-4893-a30f-957ecd0b28e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273264686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1273264686
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3891742927
Short name T710
Test name
Test status
Simulation time 486338249551 ps
CPU time 302.69 seconds
Started Apr 28 02:53:35 PM PDT 24
Finished Apr 28 02:58:39 PM PDT 24
Peak memory 202324 kb
Host smart-c739ac67-3d4f-4047-a3ec-2946c25a2997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891742927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3891742927
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4279199396
Short name T182
Test name
Test status
Simulation time 167979017626 ps
CPU time 44.44 seconds
Started Apr 28 02:53:35 PM PDT 24
Finished Apr 28 02:54:20 PM PDT 24
Peak memory 202276 kb
Host smart-9c09a5d5-78df-4dae-8615-6ed045a03560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279199396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4279199396
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.303745511
Short name T292
Test name
Test status
Simulation time 168406337263 ps
CPU time 234.5 seconds
Started Apr 28 02:53:34 PM PDT 24
Finished Apr 28 02:57:29 PM PDT 24
Peak memory 202260 kb
Host smart-2e92a0bc-25d9-42af-a23c-b86d7ed3d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303745511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.303745511
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2079217032
Short name T453
Test name
Test status
Simulation time 332771182076 ps
CPU time 727.09 seconds
Started Apr 28 02:53:36 PM PDT 24
Finished Apr 28 03:05:44 PM PDT 24
Peak memory 202296 kb
Host smart-7498ef74-0f11-43f7-9e63-0b59531c9e6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079217032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2079217032
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1305208588
Short name T280
Test name
Test status
Simulation time 195029009139 ps
CPU time 496.95 seconds
Started Apr 28 02:53:36 PM PDT 24
Finished Apr 28 03:01:54 PM PDT 24
Peak memory 202336 kb
Host smart-d8881d70-500a-481a-859f-13ac354bb8e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305208588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1305208588
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1431528092
Short name T405
Test name
Test status
Simulation time 610843355157 ps
CPU time 376.81 seconds
Started Apr 28 02:53:40 PM PDT 24
Finished Apr 28 02:59:58 PM PDT 24
Peak memory 202392 kb
Host smart-ac77352f-f709-49ca-a5f0-32b6c17cf719
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431528092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1431528092
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.614771335
Short name T45
Test name
Test status
Simulation time 128317263472 ps
CPU time 725.7 seconds
Started Apr 28 02:53:42 PM PDT 24
Finished Apr 28 03:05:49 PM PDT 24
Peak memory 202576 kb
Host smart-eb0fbbdb-843d-4990-be8e-efb0225d9974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614771335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.614771335
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3128466844
Short name T407
Test name
Test status
Simulation time 26766087347 ps
CPU time 29.42 seconds
Started Apr 28 02:53:41 PM PDT 24
Finished Apr 28 02:54:11 PM PDT 24
Peak memory 202104 kb
Host smart-9bffc526-ca2d-4f8a-b84d-e360b9dbf94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128466844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3128466844
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.641061949
Short name T615
Test name
Test status
Simulation time 3253041509 ps
CPU time 7.5 seconds
Started Apr 28 02:53:40 PM PDT 24
Finished Apr 28 02:53:48 PM PDT 24
Peak memory 202136 kb
Host smart-c3e8945e-1cdb-43e5-9dff-08a352a710d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641061949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.641061949
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3932207930
Short name T495
Test name
Test status
Simulation time 5899931600 ps
CPU time 5.55 seconds
Started Apr 28 02:53:35 PM PDT 24
Finished Apr 28 02:53:41 PM PDT 24
Peak memory 202112 kb
Host smart-8b4a21d9-9d2d-4f78-a926-9a91af4d3730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932207930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3932207930
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1218946548
Short name T251
Test name
Test status
Simulation time 167769754806 ps
CPU time 199.85 seconds
Started Apr 28 02:53:44 PM PDT 24
Finished Apr 28 02:57:04 PM PDT 24
Peak memory 202296 kb
Host smart-d26bb904-a485-46cb-84f1-ed37096819e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218946548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1218946548
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1448692184
Short name T21
Test name
Test status
Simulation time 3465538177 ps
CPU time 14.66 seconds
Started Apr 28 02:53:41 PM PDT 24
Finished Apr 28 02:53:56 PM PDT 24
Peak memory 210824 kb
Host smart-b1503c6c-5263-4ced-8038-a0378986b0f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448692184 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1448692184
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2507802877
Short name T625
Test name
Test status
Simulation time 287218297 ps
CPU time 1.33 seconds
Started Apr 28 02:54:01 PM PDT 24
Finished Apr 28 02:54:03 PM PDT 24
Peak memory 201992 kb
Host smart-ef647993-ee01-48a5-861a-7c7fa1145db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507802877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2507802877
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2847597219
Short name T186
Test name
Test status
Simulation time 322466457300 ps
CPU time 152.06 seconds
Started Apr 28 02:53:53 PM PDT 24
Finished Apr 28 02:56:25 PM PDT 24
Peak memory 202316 kb
Host smart-37c400b7-b043-4731-9a6b-6c5869a4a5dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847597219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2847597219
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2344022314
Short name T708
Test name
Test status
Simulation time 210479985190 ps
CPU time 139.02 seconds
Started Apr 28 02:53:53 PM PDT 24
Finished Apr 28 02:56:12 PM PDT 24
Peak memory 202312 kb
Host smart-7d3d26c4-32ed-4204-bb75-be1aaccce1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344022314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2344022314
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1383622257
Short name T401
Test name
Test status
Simulation time 157652541454 ps
CPU time 92.59 seconds
Started Apr 28 02:53:48 PM PDT 24
Finished Apr 28 02:55:21 PM PDT 24
Peak memory 202324 kb
Host smart-46c74be3-0633-4374-9ecb-f3cdae92e3c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383622257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1383622257
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1323690680
Short name T755
Test name
Test status
Simulation time 172842136578 ps
CPU time 94.25 seconds
Started Apr 28 02:53:49 PM PDT 24
Finished Apr 28 02:55:23 PM PDT 24
Peak memory 202340 kb
Host smart-b5a5fef4-c738-4a6c-a225-40530d44ea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323690680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1323690680
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3749054462
Short name T530
Test name
Test status
Simulation time 483805331099 ps
CPU time 289.63 seconds
Started Apr 28 02:53:46 PM PDT 24
Finished Apr 28 02:58:36 PM PDT 24
Peak memory 202280 kb
Host smart-1a82bf53-c61f-4acb-b02d-45c9d0a1d4f1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749054462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3749054462
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3010001519
Short name T180
Test name
Test status
Simulation time 390469296362 ps
CPU time 227.38 seconds
Started Apr 28 02:53:51 PM PDT 24
Finished Apr 28 02:57:39 PM PDT 24
Peak memory 202352 kb
Host smart-78e518e0-2543-4051-b968-19fa99a8406c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010001519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3010001519
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3796833090
Short name T676
Test name
Test status
Simulation time 132412866851 ps
CPU time 439.9 seconds
Started Apr 28 02:53:58 PM PDT 24
Finished Apr 28 03:01:18 PM PDT 24
Peak memory 202660 kb
Host smart-099c0db3-e8d5-4408-ad11-566ecea5e041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796833090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3796833090
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1367550171
Short name T179
Test name
Test status
Simulation time 30931532973 ps
CPU time 69.51 seconds
Started Apr 28 02:53:56 PM PDT 24
Finished Apr 28 02:55:06 PM PDT 24
Peak memory 202140 kb
Host smart-bb94a27e-a18e-49b1-9b6b-ceb745db7319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367550171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1367550171
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3753485130
Short name T566
Test name
Test status
Simulation time 3771457745 ps
CPU time 3.05 seconds
Started Apr 28 02:53:56 PM PDT 24
Finished Apr 28 02:53:59 PM PDT 24
Peak memory 202124 kb
Host smart-3cb244c3-90e2-4be4-8809-73442e1dec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753485130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3753485130
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3681063282
Short name T489
Test name
Test status
Simulation time 5912035213 ps
CPU time 8.27 seconds
Started Apr 28 02:53:48 PM PDT 24
Finished Apr 28 02:53:57 PM PDT 24
Peak memory 202116 kb
Host smart-b44771b8-8e43-4486-b354-555a2779961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681063282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3681063282
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1114980459
Short name T680
Test name
Test status
Simulation time 164572575996 ps
CPU time 526.11 seconds
Started Apr 28 02:54:01 PM PDT 24
Finished Apr 28 03:02:48 PM PDT 24
Peak memory 212904 kb
Host smart-0d65bc63-ef72-4210-afed-dce9a166b6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114980459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1114980459
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3770619431
Short name T731
Test name
Test status
Simulation time 89512728715 ps
CPU time 61.07 seconds
Started Apr 28 02:54:07 PM PDT 24
Finished Apr 28 02:55:08 PM PDT 24
Peak memory 211084 kb
Host smart-601eab96-36f7-486f-90b6-739b336ab3ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770619431 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3770619431
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.3338165775
Short name T528
Test name
Test status
Simulation time 309638819 ps
CPU time 1.28 seconds
Started Apr 28 02:45:45 PM PDT 24
Finished Apr 28 02:45:47 PM PDT 24
Peak memory 201984 kb
Host smart-e7b540a0-1345-4c9b-8314-e1f5dd4c1018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338165775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.3338165775
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1423422094
Short name T232
Test name
Test status
Simulation time 582242170976 ps
CPU time 230.42 seconds
Started Apr 28 02:45:47 PM PDT 24
Finished Apr 28 02:49:38 PM PDT 24
Peak memory 202372 kb
Host smart-d2ee44c1-b55f-456a-b120-cf97ca9a0c5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423422094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1423422094
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.645274432
Short name T327
Test name
Test status
Simulation time 489762774027 ps
CPU time 203.16 seconds
Started Apr 28 02:45:42 PM PDT 24
Finished Apr 28 02:49:06 PM PDT 24
Peak memory 202308 kb
Host smart-427e1253-8d31-4fca-bf61-e6b51cb496ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645274432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.645274432
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2535953098
Short name T580
Test name
Test status
Simulation time 158287318358 ps
CPU time 174.9 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:48:47 PM PDT 24
Peak memory 202280 kb
Host smart-99de034b-676e-4b35-bae1-273128421aef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535953098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2535953098
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.570505679
Short name T157
Test name
Test status
Simulation time 486554557626 ps
CPU time 970.19 seconds
Started Apr 28 02:45:42 PM PDT 24
Finished Apr 28 03:01:54 PM PDT 24
Peak memory 202288 kb
Host smart-88deb10e-c72d-4179-82c0-ca21e17b7612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570505679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.570505679
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2997655624
Short name T769
Test name
Test status
Simulation time 164629251748 ps
CPU time 386.26 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:52:09 PM PDT 24
Peak memory 202248 kb
Host smart-43f65216-272d-41ef-a24d-b28d0d72be4d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997655624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2997655624
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3900422795
Short name T164
Test name
Test status
Simulation time 178763967737 ps
CPU time 102.37 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:47:36 PM PDT 24
Peak memory 202292 kb
Host smart-74b63798-7b47-4b20-a7c3-05127124d2fc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900422795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3900422795
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2025612750
Short name T438
Test name
Test status
Simulation time 629395168257 ps
CPU time 364.88 seconds
Started Apr 28 02:45:41 PM PDT 24
Finished Apr 28 02:51:47 PM PDT 24
Peak memory 202296 kb
Host smart-c5f1ca04-1182-4794-ab86-28b3f6d1b448
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025612750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2025612750
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3666396501
Short name T762
Test name
Test status
Simulation time 67367329104 ps
CPU time 260.92 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 02:50:12 PM PDT 24
Peak memory 202660 kb
Host smart-5379edde-9ed4-4b51-aadc-7b8d174f064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666396501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3666396501
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.3192932611
Short name T737
Test name
Test status
Simulation time 42826101690 ps
CPU time 67.11 seconds
Started Apr 28 02:45:47 PM PDT 24
Finished Apr 28 02:46:54 PM PDT 24
Peak memory 202128 kb
Host smart-f4a56e5b-58a2-409b-9035-bf37043d306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192932611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.3192932611
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3070513433
Short name T397
Test name
Test status
Simulation time 2926730408 ps
CPU time 2.7 seconds
Started Apr 28 02:45:46 PM PDT 24
Finished Apr 28 02:45:49 PM PDT 24
Peak memory 202140 kb
Host smart-39ee1df6-c88f-4c32-9ac9-857cafba9c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070513433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3070513433
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3273099339
Short name T428
Test name
Test status
Simulation time 5562824928 ps
CPU time 4.26 seconds
Started Apr 28 02:45:40 PM PDT 24
Finished Apr 28 02:45:46 PM PDT 24
Peak memory 202136 kb
Host smart-fdc2b678-cdff-4ce5-ac44-35e8df12367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273099339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3273099339
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1401977938
Short name T256
Test name
Test status
Simulation time 352099923891 ps
CPU time 814.89 seconds
Started Apr 28 02:45:48 PM PDT 24
Finished Apr 28 02:59:23 PM PDT 24
Peak memory 202380 kb
Host smart-550607b0-1e29-4012-b4b9-fec5da724e0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401977938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1401977938
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3447902832
Short name T677
Test name
Test status
Simulation time 66097613625 ps
CPU time 124.19 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:47:54 PM PDT 24
Peak memory 210540 kb
Host smart-4b4ce2e0-2508-414e-9a38-7ce7b3d7c080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447902832 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3447902832
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.64999010
Short name T693
Test name
Test status
Simulation time 497356553 ps
CPU time 0.95 seconds
Started Apr 28 02:45:47 PM PDT 24
Finished Apr 28 02:45:49 PM PDT 24
Peak memory 202000 kb
Host smart-381b8ada-4f7c-4018-ad34-0f5380cb3df9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64999010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.64999010
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3457811378
Short name T772
Test name
Test status
Simulation time 159886854460 ps
CPU time 85.51 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:47:16 PM PDT 24
Peak memory 202332 kb
Host smart-693ec902-d1b6-4ba6-8e95-238963fd8b8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457811378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3457811378
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1486787337
Short name T255
Test name
Test status
Simulation time 226466846338 ps
CPU time 284.37 seconds
Started Apr 28 02:45:48 PM PDT 24
Finished Apr 28 02:50:33 PM PDT 24
Peak memory 202280 kb
Host smart-7dd3c2b1-21e1-4efa-9f5d-09b558c5f26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486787337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1486787337
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.433896871
Short name T595
Test name
Test status
Simulation time 490529629371 ps
CPU time 309.32 seconds
Started Apr 28 02:45:45 PM PDT 24
Finished Apr 28 02:50:55 PM PDT 24
Peak memory 202328 kb
Host smart-5b077067-843c-48ef-968d-c17bc0d1b1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433896871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.433896871
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3847919796
Short name T421
Test name
Test status
Simulation time 325142010701 ps
CPU time 209.85 seconds
Started Apr 28 02:45:48 PM PDT 24
Finished Apr 28 02:49:19 PM PDT 24
Peak memory 202308 kb
Host smart-ec9e6b08-9602-41a8-bd58-90e169fd98db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847919796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3847919796
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3555179269
Short name T90
Test name
Test status
Simulation time 496036656774 ps
CPU time 278.67 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 02:50:30 PM PDT 24
Peak memory 202324 kb
Host smart-1ebce9bd-a0fe-4c69-a15e-8b0213af85d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555179269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3555179269
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3042739409
Short name T760
Test name
Test status
Simulation time 163591838808 ps
CPU time 28.53 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 02:46:19 PM PDT 24
Peak memory 202196 kb
Host smart-295ee2f3-8cbf-49a8-9953-ec011b58423b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042739409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3042739409
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.4233475493
Short name T231
Test name
Test status
Simulation time 541188819973 ps
CPU time 1238.18 seconds
Started Apr 28 02:45:47 PM PDT 24
Finished Apr 28 03:06:26 PM PDT 24
Peak memory 202364 kb
Host smart-c138ec33-551b-407f-90db-c5a6f1d1e75b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233475493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.4233475493
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1152489435
Short name T613
Test name
Test status
Simulation time 590731230211 ps
CPU time 1424.17 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 03:09:34 PM PDT 24
Peak memory 202272 kb
Host smart-b12abcda-cace-47c0-8016-927f64be7e4e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152489435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1152489435
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1790875493
Short name T363
Test name
Test status
Simulation time 105240538207 ps
CPU time 523.03 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:54:33 PM PDT 24
Peak memory 202736 kb
Host smart-a92ecb1a-3b99-4dad-80c4-68bb1e7f8566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790875493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1790875493
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2607366798
Short name T1
Test name
Test status
Simulation time 46524993963 ps
CPU time 108.62 seconds
Started Apr 28 02:45:48 PM PDT 24
Finished Apr 28 02:47:37 PM PDT 24
Peak memory 202116 kb
Host smart-e153f655-fa5d-454f-ac84-1e134b0252b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607366798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2607366798
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2507795784
Short name T427
Test name
Test status
Simulation time 4614949360 ps
CPU time 3.4 seconds
Started Apr 28 02:45:48 PM PDT 24
Finished Apr 28 02:45:52 PM PDT 24
Peak memory 202124 kb
Host smart-2780afc5-a3eb-42b2-99aa-6b35e3e26791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507795784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2507795784
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.4137321881
Short name T790
Test name
Test status
Simulation time 5620866932 ps
CPU time 14.58 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:46:04 PM PDT 24
Peak memory 202128 kb
Host smart-82d4dc83-091b-4ee8-b580-b2c25b8cce6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137321881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.4137321881
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2768780923
Short name T14
Test name
Test status
Simulation time 53489018211 ps
CPU time 126.63 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:47:56 PM PDT 24
Peak memory 210648 kb
Host smart-da80571a-88de-4cbc-8374-12b1d3f9122c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768780923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2768780923
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3936946637
Short name T411
Test name
Test status
Simulation time 363926344 ps
CPU time 1.45 seconds
Started Apr 28 02:45:53 PM PDT 24
Finished Apr 28 02:45:55 PM PDT 24
Peak memory 201888 kb
Host smart-a17a93ef-ad02-43d5-893f-a0f2d7cbdf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936946637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3936946637
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2100991663
Short name T187
Test name
Test status
Simulation time 364223197158 ps
CPU time 477.21 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:53:50 PM PDT 24
Peak memory 202364 kb
Host smart-6fcda0ee-dd02-496c-81b1-3625706bb5c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100991663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2100991663
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2703020478
Short name T652
Test name
Test status
Simulation time 509130748379 ps
CPU time 1156.42 seconds
Started Apr 28 02:45:54 PM PDT 24
Finished Apr 28 03:05:11 PM PDT 24
Peak memory 202320 kb
Host smart-e3cac22f-4ef8-4154-a0b4-21ce68534bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703020478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2703020478
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.132698954
Short name T398
Test name
Test status
Simulation time 167820172484 ps
CPU time 414.8 seconds
Started Apr 28 02:45:47 PM PDT 24
Finished Apr 28 02:52:42 PM PDT 24
Peak memory 202280 kb
Host smart-d3bd09b4-120d-46ca-a308-a0ee56e0d2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132698954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.132698954
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2381744296
Short name T539
Test name
Test status
Simulation time 494320864750 ps
CPU time 1172.56 seconds
Started Apr 28 02:45:46 PM PDT 24
Finished Apr 28 03:05:19 PM PDT 24
Peak memory 202332 kb
Host smart-3ee7e9b2-cd09-4bae-818b-1e6ff0691f80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381744296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2381744296
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1457263586
Short name T621
Test name
Test status
Simulation time 173537463879 ps
CPU time 109.29 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 02:47:40 PM PDT 24
Peak memory 202328 kb
Host smart-6ffb3c2a-777a-4044-96a8-788080f300d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457263586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1457263586
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.617136308
Short name T678
Test name
Test status
Simulation time 317604610312 ps
CPU time 374.71 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:52:05 PM PDT 24
Peak memory 202160 kb
Host smart-d5fb21e5-da23-4ef2-8e97-54118f8fdca2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=617136308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.617136308
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1366975176
Short name T329
Test name
Test status
Simulation time 387628320268 ps
CPU time 476.8 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:53:47 PM PDT 24
Peak memory 202052 kb
Host smart-87d9d901-fdf6-4672-bf8d-af705b4ee798
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366975176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1366975176
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1892022131
Short name T516
Test name
Test status
Simulation time 209458680643 ps
CPU time 71.86 seconds
Started Apr 28 02:45:49 PM PDT 24
Finished Apr 28 02:47:01 PM PDT 24
Peak memory 202272 kb
Host smart-43763dbc-e730-4cef-830d-59d003e88a24
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892022131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1892022131
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3219844447
Short name T666
Test name
Test status
Simulation time 123933534463 ps
CPU time 512.76 seconds
Started Apr 28 02:45:55 PM PDT 24
Finished Apr 28 02:54:28 PM PDT 24
Peak memory 202136 kb
Host smart-4a294bad-81c1-4e94-8679-eaa560095779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219844447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3219844447
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.484159441
Short name T673
Test name
Test status
Simulation time 31052994550 ps
CPU time 75.49 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:47:08 PM PDT 24
Peak memory 202120 kb
Host smart-0a1677cd-6646-44f5-a086-260b3693d324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484159441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.484159441
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3874524892
Short name T432
Test name
Test status
Simulation time 3621980990 ps
CPU time 9.23 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:46:02 PM PDT 24
Peak memory 202144 kb
Host smart-29ad3431-af05-4ecd-b0a8-d7fbeaabaa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874524892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3874524892
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2837733263
Short name T381
Test name
Test status
Simulation time 5721550738 ps
CPU time 13.87 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 02:46:05 PM PDT 24
Peak memory 202108 kb
Host smart-4bf2d478-adb3-46cc-ace2-60170a768bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837733263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2837733263
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1341528589
Short name T507
Test name
Test status
Simulation time 30809784549 ps
CPU time 65.4 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:46:58 PM PDT 24
Peak memory 202144 kb
Host smart-9c3cd82c-8f43-4da2-abe3-95d19120fbcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341528589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1341528589
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.225023281
Short name T586
Test name
Test status
Simulation time 149222509456 ps
CPU time 242.32 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:49:55 PM PDT 24
Peak memory 210540 kb
Host smart-93aefbab-12eb-4f4f-8a2f-70fe893f3623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225023281 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.225023281
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2075007697
Short name T505
Test name
Test status
Simulation time 538749026 ps
CPU time 1.31 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:45:54 PM PDT 24
Peak memory 202008 kb
Host smart-d94bf16e-e1f3-4063-8d57-c457cad243b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075007697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2075007697
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3864404160
Short name T741
Test name
Test status
Simulation time 158016164893 ps
CPU time 381.05 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:52:13 PM PDT 24
Peak memory 202188 kb
Host smart-94e077f2-d395-478c-8bab-f1fcbca24bc0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864404160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3864404160
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2454306028
Short name T172
Test name
Test status
Simulation time 335151596088 ps
CPU time 220.55 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 02:49:32 PM PDT 24
Peak memory 202392 kb
Host smart-24a54508-e52c-41d7-a099-5dc44085d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454306028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2454306028
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1177494040
Short name T467
Test name
Test status
Simulation time 166806606139 ps
CPU time 355.45 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:51:48 PM PDT 24
Peak memory 202328 kb
Host smart-a3b8d4ce-9cbd-44b3-a6fa-b94fdeab1f6c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177494040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1177494040
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3934335779
Short name T725
Test name
Test status
Simulation time 324074189461 ps
CPU time 751.68 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:58:24 PM PDT 24
Peak memory 202336 kb
Host smart-5ee58229-b502-4454-b5a7-8e5202553305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934335779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3934335779
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.961787604
Short name T604
Test name
Test status
Simulation time 327637131717 ps
CPU time 116.98 seconds
Started Apr 28 02:45:53 PM PDT 24
Finished Apr 28 02:47:51 PM PDT 24
Peak memory 202352 kb
Host smart-9d28c163-c7d4-4923-9b85-9a23b3de52af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=961787604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.961787604
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.25195144
Short name T688
Test name
Test status
Simulation time 403489790259 ps
CPU time 1013.44 seconds
Started Apr 28 02:45:50 PM PDT 24
Finished Apr 28 03:02:45 PM PDT 24
Peak memory 202328 kb
Host smart-8aba114f-5205-4834-9289-bbb91029f630
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25195144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.ad
c_ctrl_filters_wakeup_fixed.25195144
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1157885757
Short name T46
Test name
Test status
Simulation time 65746117457 ps
CPU time 245.33 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:49:58 PM PDT 24
Peak memory 202676 kb
Host smart-3753e944-1440-4495-8f2b-07306a687f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157885757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1157885757
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3018050353
Short name T367
Test name
Test status
Simulation time 26724170762 ps
CPU time 32.95 seconds
Started Apr 28 02:45:53 PM PDT 24
Finished Apr 28 02:46:27 PM PDT 24
Peak memory 202128 kb
Host smart-023c1e8f-c670-4d5d-b115-1da94c62ea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018050353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3018050353
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2979796190
Short name T154
Test name
Test status
Simulation time 5433767121 ps
CPU time 4.12 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:45:57 PM PDT 24
Peak memory 202124 kb
Host smart-988a7d61-9ed6-4956-b886-bda937f7ca75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979796190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2979796190
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3688169362
Short name T585
Test name
Test status
Simulation time 6149022867 ps
CPU time 8.54 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:46:01 PM PDT 24
Peak memory 202084 kb
Host smart-dc44c9ae-0679-4ecf-933e-98ea1a98aa48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688169362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3688169362
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.137428144
Short name T512
Test name
Test status
Simulation time 212970904305 ps
CPU time 479.69 seconds
Started Apr 28 02:45:51 PM PDT 24
Finished Apr 28 02:53:51 PM PDT 24
Peak memory 202276 kb
Host smart-d53acb17-87d4-47a8-98ec-cdba75280cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137428144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.137428144
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.4146596524
Short name T20
Test name
Test status
Simulation time 33405892539 ps
CPU time 66.09 seconds
Started Apr 28 02:45:52 PM PDT 24
Finished Apr 28 02:46:59 PM PDT 24
Peak memory 212476 kb
Host smart-96511b03-08a6-4cd4-ba7a-400c9af8b055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146596524 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.4146596524
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3127763404
Short name T532
Test name
Test status
Simulation time 303308301 ps
CPU time 1.05 seconds
Started Apr 28 02:45:57 PM PDT 24
Finished Apr 28 02:45:59 PM PDT 24
Peak memory 201976 kb
Host smart-40163306-b719-4064-9320-9eeedec3d29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127763404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3127763404
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3406105654
Short name T51
Test name
Test status
Simulation time 545923376721 ps
CPU time 291.78 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 02:51:05 PM PDT 24
Peak memory 202320 kb
Host smart-3fb0c3ba-4f6e-4916-9072-d7037e9c04ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406105654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3406105654
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.195838175
Short name T792
Test name
Test status
Simulation time 513097914295 ps
CPU time 342.47 seconds
Started Apr 28 02:45:55 PM PDT 24
Finished Apr 28 02:51:38 PM PDT 24
Peak memory 202292 kb
Host smart-5e7606be-3be7-413e-a378-ed13cc8edf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195838175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.195838175
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3156329002
Short name T295
Test name
Test status
Simulation time 487745062154 ps
CPU time 342.91 seconds
Started Apr 28 02:46:00 PM PDT 24
Finished Apr 28 02:51:43 PM PDT 24
Peak memory 202352 kb
Host smart-2c4ed9d1-9b8b-4b21-baf5-dca32bc64a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156329002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3156329002
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2714722497
Short name T466
Test name
Test status
Simulation time 168539140627 ps
CPU time 101.93 seconds
Started Apr 28 02:45:57 PM PDT 24
Finished Apr 28 02:47:39 PM PDT 24
Peak memory 202292 kb
Host smart-31640766-9dad-4756-bf58-a08ab0a6810f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714722497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2714722497
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3618172725
Short name T174
Test name
Test status
Simulation time 490379760283 ps
CPU time 252.28 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:50:09 PM PDT 24
Peak memory 202288 kb
Host smart-26f2e593-b7f2-4a1e-b417-e1228a1237f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618172725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3618172725
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4016084802
Short name T491
Test name
Test status
Simulation time 488883425612 ps
CPU time 284.31 seconds
Started Apr 28 02:45:58 PM PDT 24
Finished Apr 28 02:50:43 PM PDT 24
Peak memory 201680 kb
Host smart-b58f69bf-cfee-4528-9ea8-e96cae9cd0e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016084802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4016084802
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3320219169
Short name T690
Test name
Test status
Simulation time 468388892625 ps
CPU time 579.79 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 02:55:53 PM PDT 24
Peak memory 202316 kb
Host smart-2ea33ba3-32ea-48e0-b0a5-ac5b18ebbcbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320219169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3320219169
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1746300299
Short name T514
Test name
Test status
Simulation time 608345527907 ps
CPU time 387.75 seconds
Started Apr 28 02:45:59 PM PDT 24
Finished Apr 28 02:52:27 PM PDT 24
Peak memory 202280 kb
Host smart-459d1ac0-d49c-4169-8654-47700301461f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746300299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1746300299
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3917407206
Short name T482
Test name
Test status
Simulation time 123021307359 ps
CPU time 391.58 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:52:28 PM PDT 24
Peak memory 202680 kb
Host smart-ff93d0e0-13bc-4f74-b34c-43113e5e44eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917407206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3917407206
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.901452453
Short name T707
Test name
Test status
Simulation time 44738895544 ps
CPU time 24.85 seconds
Started Apr 28 02:45:56 PM PDT 24
Finished Apr 28 02:46:22 PM PDT 24
Peak memory 202148 kb
Host smart-5fcec963-c8e4-42f7-a3d9-4b09c052f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901452453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.901452453
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3313816408
Short name T442
Test name
Test status
Simulation time 5231880784 ps
CPU time 13.13 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 02:46:26 PM PDT 24
Peak memory 202136 kb
Host smart-b5ef6a72-c577-4aff-b54f-7f79b8bd5bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313816408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3313816408
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.544233414
Short name T640
Test name
Test status
Simulation time 6160425463 ps
CPU time 4.23 seconds
Started Apr 28 02:45:58 PM PDT 24
Finished Apr 28 02:46:03 PM PDT 24
Peak memory 201520 kb
Host smart-7a0dc4d8-bb96-4538-816c-a51472044b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544233414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.544233414
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.398247988
Short name T87
Test name
Test status
Simulation time 17833379162 ps
CPU time 38.1 seconds
Started Apr 28 02:46:12 PM PDT 24
Finished Apr 28 02:46:51 PM PDT 24
Peak memory 210708 kb
Host smart-6bf90720-c169-4ceb-9b34-5c0ea8ed20df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398247988 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.398247988
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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