Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6686	1			T3	7		T4	20		T5	40
testmodes[AdcCtrlTestmodeNormal]	5406	1			T1	1		T2	3		T3	6
testmodes[AdcCtrlTestmodeLowpower]	5728	1			T1	14		T5	41		T6	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3521	1			T3	3		T4	19		T5	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1736	1			T3	3		T5	16		T7	17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1313	1			T5	13		T6	1		T7	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1720	1			T3	4		T5	16		T7	16
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1967	1			T2	2		T3	2		T5	9
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1378	1			T5	13		T6	3		T7	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1338	1			T5	14		T6	2		T7	21
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1357	1			T1	1		T5	13		T6	2
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2793	1			T1	13		T5	14		T6	1