Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22115

1

T1

15

T3

13

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3417

1

T1

5

T2

24

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19677

1

T1

20

T2

9

T3

13

auto[1]

5855

1

T2

15

T5

23

T7

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	96	1			T144	13		T220	5		T165	1
values[1]	639	1			T2	5		T5	23		T7	17
values[2]	578	1			T2	9		T12	11		T24	1
values[3]	524	1			T12	8		T13	24		T31	1
values[4]	2918	1			T7	11		T11	2		T29	16
values[5]	545	1			T6	3		T142	1		T38	20
values[6]	980	1			T28	14		T31	21		T15	1
values[7]	570	1			T12	14		T15	4		T150	15
values[8]	600	1			T1	5		T11	16		T14	4
values[9]	1171	1			T2	10		T9	11		T31	22
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	897	1			T2	5		T5	23		T7	17
values[1]	561	1			T2	9		T24	1		T28	9
values[2]	452	1			T11	2		T12	8		T13	24
values[3]	2901	1			T7	11		T29	16		T30	17
values[4]	792	1			T6	3		T31	21		T148	15
values[5]	777	1			T28	14		T15	1		T16	6
values[6]	564	1			T12	14		T28	9		T15	4
values[7]	703	1			T1	5		T2	10		T11	16
values[8]	710	1			T9	11		T31	22		T137	16
values[9]	234	1			T221	25		T18	7		T187	14
minimum	16941	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	12		T12	1		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	1		T7	9		T148	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T28	9		T31	1		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T2	1		T24	1		T39	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	1		T12	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	17		T222	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T29	2		T30	17		T31	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	6		T150	11		T141	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T31	11		T223	7		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	2		T148	15		T156	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T16	4		T150	9		T40	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T28	14		T15	1		T147	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	3		T222	1		T224	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	1		T28	9		T41	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T14	3		T32	4		T148	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T1	3		T2	1		T11	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T31	11		T137	8		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	11		T225	2		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T18	5		T187	14		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T221	15		T163	1		T228	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16800	1			T1	14		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	11		T12	10		T144	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	4		T7	8		T224	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T143	14		T206	3		T162	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T2	8		T39	8		T184	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T11	1		T12	7		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T13	7		T144	8		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T29	14		T31	17		T160	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	5		T150	15		T134	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T31	10		T223	6		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T17	3		T82	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T16	2		T150	6		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T147	20		T230	5		T80	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T15	1		T224	14		T231	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T12	13		T41	3		T143	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	1		T32	13		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	2		T2	9		T11	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T31	11		T137	8		T232	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T233	11		T234	2		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T18	2		T227	2		T235	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T221	10		T163	3		T228	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	1		T27	15		T15	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T144	5		T220	5		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T174	1		T236	15		T106	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T5	12		T27	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	1		T7	9		T224	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T27	1		T28	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T2	1		T24	1		T148	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T31	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	17		T39	16		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T11	1		T29	2		T30	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	6		T150	11		T141	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T142	1		T38	11		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	2		T156	14		T134	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T31	11		T16	4		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T28	14		T15	1		T148	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	3		T150	9		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T12	1		T41	4		T237	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	3		T148	3		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T1	3		T11	8		T28	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T31	11		T32	4		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T2	1		T9	11		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T144	8		T238	10		T105	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T174	1		T236	13		T106	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	11		T27	15		T144	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T2	4		T7	8		T224	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T12	10		T143	14		T162	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T2	8		T239	2		T45	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T12	7		T150	6		T206	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	7		T39	8		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T11	1		T29	14		T31	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	5		T150	15		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T38	9		T240	4		T159	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T6	1		T134	11		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T31	10		T16	2		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T17	3		T143	15		T147	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	1		T150	6		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T12	13		T41	3		T237	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T14	1		T39	1		T242	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	2		T11	8		T132	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T31	11		T32	13		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	9		T132	8		T196	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	12		T12	11		T27	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T2	5		T7	9		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T28	1		T31	1		T204	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T2	9		T24	1		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	2		T12	8		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	9		T222	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T29	16		T30	2		T31	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	6		T150	16		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T31	11		T223	7		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T6	2		T148	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T16	4		T150	7		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T28	1		T15	1		T147	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	3		T222	1		T224	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T12	14		T28	1		T41	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T14	3		T32	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	3		T2	10		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T31	12		T137	9		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T225	2		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T18	6		T187	1		T227	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T221	11		T163	4		T228	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16937	1			T1	15		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	11		T243	7		T144	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	8		T148	6		T244	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T28	8		T245	11		T161	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T39	11		T246	7		T247	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T150	6		T141	9		T248	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T13	15		T144	13		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T30	15		T31	11		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	5		T150	10		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T31	10		T223	6		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T148	14		T156	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	2		T150	8		T40	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T28	13		T147	22		T249	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T15	1		T224	14		T231	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T28	8		T41	2		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	1		T32	3		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T1	2		T11	7		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T31	10		T137	7		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	10		T81	1		T19	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T18	1		T187	13		T250	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T221	14		T228	13		T251	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T144	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T144	9		T220	1		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T174	2		T236	14		T106	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	12		T27	16		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	5		T7	9		T224	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T12	11		T27	1		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	9		T24	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T12	8		T31	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T13	9		T39	13		T184	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T11	2		T29	16		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T7	6		T150	16		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T142	1		T38	14		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	2		T156	1		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T31	11		T16	4		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	1		T15	1		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T15	3		T150	7		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	14		T41	5		T237	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T14	3		T148	1		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	3		T11	9		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T31	12		T32	14		T137	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T2	10		T9	1		T132	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T144	4		T220	4		T238	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T236	14		T106	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	11		T144	9		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	8		T224	14		T253	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T28	8		T245	11		T243	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T148	6		T244	1		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T150	6		T161	15		T182	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	15		T39	11		T229	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1164	1			T30	15		T31	11		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	5		T150	10		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	6		T201	13		T255	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T6	1		T156	13		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T31	10		T16	2		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T28	13		T148	14		T243	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	1		T150	8		T231	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T41	2		T237	2		T256	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T14	1		T148	2		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	2		T11	7		T28	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T31	10		T32	3		T137	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	10		T221	14		T257	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22519

1

T1

15

T2

15

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3013

1

T1

5

T2

9

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19928

1

T1

15

T2

10

T3

13

auto[1]

5604

1

T1

5

T2

14

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42	1			T226	1		T258	10		T259	8
values[1]	574	1			T2	10		T11	2		T13	17
values[2]	760	1			T149	1		T204	1		T142	1
values[3]	627	1			T12	14		T156	14		T245	15
values[4]	495	1			T2	14		T7	17		T24	1
values[5]	2773	1			T5	23		T6	3		T27	1
values[6]	677	1			T12	11		T14	4		T27	16
values[7]	678	1			T9	11		T11	16		T149	1
values[8]	809	1			T28	14		T150	15		T141	15
values[9]	1186	1			T1	5		T7	11		T12	8
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	773	1			T2	10		T11	2		T13	17
values[1]	730	1			T149	1		T204	1		T142	1
values[2]	580	1			T2	5		T12	14		T24	1
values[3]	2695	1			T2	9		T5	23		T7	17
values[4]	560	1			T6	3		T27	16		T31	1
values[5]	770	1			T12	11		T14	4		T31	22
values[6]	759	1			T9	11		T11	16		T28	23
values[7]	711	1			T1	5		T12	8		T13	7
values[8]	829	1			T31	50		T148	15		T142	1
values[9]	176	1			T7	11		T41	7		T229	14
minimum	16949	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T2	1		T13	10		T38	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	1		T40	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T204	1		T142	1		T245	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T149	1		T223	7		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T2	1		T12	1		T260	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T24	1		T150	7		T156	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T5	12		T7	9		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T2	1		T27	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T148	10		T40	8		T261	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	2		T27	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T32	4		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	3		T31	11		T137	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	8		T134	10		T262	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T9	11		T28	23		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T15	1		T141	15		T39	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	3		T12	1		T13	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T141	10		T39	4		T17	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T31	23		T148	15		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T7	6		T263	1		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T41	4		T229	3		T265	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T135	1		T266	11		T259	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	9		T13	7		T38	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	1		T186	11		T267	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T241	2		T268	9		T269	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T223	6		T132	4		T184	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	4		T12	13		T260	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T150	6		T144	16		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T5	11		T7	8		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T2	8		T16	2		T227	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T40	2		T147	1		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	1		T27	15		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T12	10		T32	13		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T14	1		T31	11		T137	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	8		T134	8		T257	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T150	15		T196	13		T134	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T39	8		T144	19		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	2		T12	7		T150	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T39	1		T17	3		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T31	27		T132	8		T143	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T7	5		T263	11		T270	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T41	3		T229	11		T265	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T266	10		T259	15		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T213	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T226	1		T258	8		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T2	1		T13	10		T38	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	1		T135	1		T186	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T204	1		T142	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T149	1		T223	7		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	1		T245	3		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T156	14		T245	12		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	1		T7	9		T28	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T2	1		T24	1		T37	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T5	12		T29	2		T30	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	2		T27	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T32	4		T148	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T14	3		T27	1		T28	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	8		T149	1		T134	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	11		T132	1		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T141	15		T39	16		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T28	14		T150	9		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T7	6		T15	1		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T1	3		T12	1		T13	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T258	2		T259	7		T271	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	9		T13	7		T38	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T186	11		T266	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	16		T241	2		T269	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T223	6		T132	4		T184	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	13		T260	15		T272	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T273	2		T162	10		T19	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T2	4		T7	8		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T2	8		T150	6		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1025	1			T5	11		T29	14		T160	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	1		T16	2		T232	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	10		T32	13		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T14	1		T27	15		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	8		T134	8		T257	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T150	15		T253	7		T206	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	8		T144	19		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T150	6		T196	13		T134	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T7	5		T39	1		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	2		T12	7		T31	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2