Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22079

1

T1

15

T3

13

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3453

1

T1

5

T2

24

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19658

1

T1

20

T2

9

T3

13

auto[1]

5874

1

T2

15

T5

23

T7

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	262	1			T225	1		T186	13		T162	12
values[0]	24	1			T330	24		-	-		-	-
values[1]	670	1			T2	5		T5	23		T7	17
values[2]	659	1			T2	9		T24	1		T28	9
values[3]	509	1			T12	8		T13	24		T31	1
values[4]	2863	1			T7	11		T11	2		T29	16
values[5]	616	1			T6	3		T142	1		T38	20
values[6]	884	1			T28	14		T31	21		T15	1
values[7]	638	1			T12	14		T15	4		T150	15
values[8]	566	1			T1	5		T11	16		T14	4
values[9]	930	1			T2	10		T9	11		T31	22
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	684	1			T5	23		T7	17		T27	17
values[1]	656	1			T2	9		T12	11		T24	1
values[2]	430	1			T11	2		T12	8		T13	24
values[3]	2887	1			T7	11		T29	16		T30	17
values[4]	844	1			T6	3		T31	21		T148	15
values[5]	697	1			T28	14		T15	1		T16	6
values[6]	598	1			T12	14		T28	9		T15	4
values[7]	686	1			T1	5		T2	10		T11	16
values[8]	828	1			T9	11		T31	22		T137	16
values[9]	134	1			T221	25		T187	14		T227	3
minimum	17088	1			T1	15		T2	5		T3	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	12		T27	2		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	9		T148	7		T244	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	1		T28	9		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T2	1		T24	1		T39	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T12	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	17		T222	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T29	2		T30	17		T31	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	6		T150	11		T141	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T223	7		T38	11		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T6	2		T31	11		T148	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T16	4		T150	9		T40	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T28	14		T15	1		T147	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	3		T222	1		T224	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T12	1		T28	9		T41	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	3		T32	4		T148	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	3		T2	1		T11	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T31	11		T137	8		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	11		T225	2		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T187	14		T227	1		T235	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T221	15		T251	12		T277	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16815	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T2	1		T224	15		T331	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	11		T27	15		T144	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	8		T253	17		T308	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T12	10		T143	14		T206	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	8		T39	8		T184	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T11	1		T12	7		T150	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T13	7		T144	8		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T29	14		T31	17		T160	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	5		T150	15		T134	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T223	6		T38	9		T221	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T6	1		T31	10		T17	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	2		T150	6		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T147	20		T80	11		T289	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T224	14		T231	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T12	13		T41	3		T143	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	1		T32	13		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	2		T2	9		T11	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T31	11		T137	8		T232	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T186	3		T233	11		T234	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T227	2		T235	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T221	10		T251	16		T277	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T2	4		T224	12		T18	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T162	7		T80	1		T322	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T225	1		T186	10		T81	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T330	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	12		T12	1		T27	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T2	1		T7	9		T224	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	9		T132	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	1		T24	1		T148	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T31	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	17		T39	16		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1499	1			T11	1		T29	2		T30	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T7	6		T150	11		T141	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T142	1		T38	11		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	2		T156	14		T134	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T16	4		T223	7		T40	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T28	14		T31	11		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T15	3		T150	9		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T12	1		T41	4		T143	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	3		T148	3		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	3		T11	8		T28	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T31	11		T32	4		T137	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T2	1		T9	11		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T162	5		T322	11		T266	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T186	3		T332	13		T251	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T330	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	11		T12	10		T27	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	4		T7	8		T224	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T143	14		T162	10		T291	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	8		T247	10		T239	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T12	7		T150	6		T206	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T13	7		T39	8		T184	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T11	1		T29	14		T31	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	5		T150	15		T224	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T38	9		T221	2		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T134	11		T241	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T16	2		T223	6		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T31	10		T17	3		T147	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	1		T150	6		T224	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T12	13		T41	3		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T14	1		T39	1		T34	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T1	2		T11	8		T132	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T31	11		T32	13		T137	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	9		T132	8		T196	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	12		T27	17		T40	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	9		T148	1		T244	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T12	11		T28	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T2	9		T24	1		T39	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	2		T12	8		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T13	9		T222	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T29	16		T30	2		T31	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	6		T150	16		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T223	7		T38	14		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T6	2		T31	11		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T16	4		T150	7		T40	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T28	1		T15	1		T147	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	3		T222	1		T224	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	14		T28	1		T41	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T14	3		T32	14		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T1	3		T2	10		T11	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T31	12		T137	9		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	1		T225	2		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T187	1		T227	3		T235	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T221	11		T251	17		T277	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16936	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T2	5		T224	13		T331	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T5	11		T243	7		T144	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	8		T148	6		T244	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T28	8		T245	11		T161	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T39	11		T246	7		T247	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T150	6		T141	9		T191	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T13	15		T144	13		T229	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1169	1			T30	15		T31	11		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T7	5		T150	10		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T223	6		T38	6		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	1		T31	10		T148	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T16	2		T150	8		T40	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T28	13		T147	22		T249	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	1		T224	14		T231	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T28	8		T41	2		T143	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T14	1		T32	3		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	2		T11	7		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T31	10		T137	7		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	10		T186	9		T81	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T187	13		T333	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T221	14		T251	11		T277	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T144	9		T220	4		T281	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T224	14		T146	11		T174	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T162	6		T80	1		T322	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T225	1		T186	4		T81	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T330	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	12		T12	11		T27	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	5		T7	9		T224	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T28	1		T132	1		T225	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	9		T24	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T12	8		T31	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	9		T39	13		T184	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T11	2		T29	16		T30	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	6		T150	16		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T142	1		T38	14		T136	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	2		T156	1		T134	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T16	4		T223	7		T40	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T28	1		T31	11		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	3		T150	7		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	14		T41	5		T143	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	3		T148	1		T142	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	3		T11	9		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T31	12		T32	14		T137	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T2	10		T9	1		T132	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T162	6		T322	11		T266	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T186	9		T81	1		T220	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T330	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	11		T144	13		T252	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	8		T224	14		T253	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T28	8		T245	11		T243	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T148	6		T244	1		T247	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T150	6		T161	15		T248	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	15		T39	11		T144	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T30	15		T31	11		T151	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	5		T150	10		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T38	6		T221	4		T201	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	1		T156	13		T134	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T16	2		T223	6		T40	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T28	13		T31	10		T148	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T15	1		T150	8		T224	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T41	2		T143	11		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T14	1		T148	2		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	2		T11	7		T28	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T31	10		T32	3		T137	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	10		T221	14		T257	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1