Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22081

1

T1

20

T2

15

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3451

1

T2

9

T6

3

T7

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19842

1

T1

15

T2

9

T3

13

auto[1]

5690

1

T1

5

T2

15

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	297	1			T148	15		T37	3		T134	18
values[0]	26	1			T132	5		T334	1		T335	13
values[1]	571	1			T11	2		T27	1		T15	4
values[2]	610	1			T13	17		T14	4		T37	2
values[3]	872	1			T2	9		T5	23		T11	16
values[4]	655	1			T2	5		T9	11		T31	44
values[5]	529	1			T2	10		T6	3		T7	11
values[6]	741	1			T12	8		T24	1		T27	16
values[7]	566	1			T13	7		T28	14		T149	2
values[8]	2828	1			T7	17		T12	11		T29	16
values[9]	926	1			T1	5		T28	18		T245	3
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	414	1			T15	4		T148	3		T16	6
values[1]	630	1			T13	17		T14	4		T37	2
values[2]	965	1			T2	9		T5	23		T9	11
values[3]	645	1			T2	5		T31	73		T204	1
values[4]	601	1			T2	10		T6	3		T7	11
values[5]	654	1			T13	7		T24	1		T27	16
values[6]	2721	1			T28	14		T29	16		T30	17
values[7]	741	1			T7	17		T12	11		T148	7
values[8]	862	1			T1	5		T28	18		T148	15
values[9]	137	1			T37	3		T222	1		T143	1
minimum	17162	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	4		T223	7		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T15	3		T148	3		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	10		T37	2		T39	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T14	3		T196	1		T221	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T5	12		T9	11		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	1		T11	8		T32	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	1		T134	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T31	35		T204	1		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T2	1		T12	1		T34	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	2		T7	6		T12	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T13	7		T144	5		T145	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T24	1		T27	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T28	14		T29	2		T30	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T149	1		T142	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	9		T12	1		T148	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T141	10		T40	1		T243	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	3		T28	9		T134	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	9		T148	15		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T37	3		T231	7		T268	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T222	1		T143	1		T311	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16874	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T132	1		T269	10		T289	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	2		T223	6		T41	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T15	1		T274	9		T45	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	7		T39	9		T224	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T14	1		T196	13		T221	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	11		T137	8		T144	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T2	8		T11	8		T32	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T2	4		T134	11		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	38		T144	19		T273	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	9		T12	13		T34	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	1		T7	5		T12	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T144	8		T145	2		T308	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T27	15		T18	2		T162	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T29	14		T160	4		T189	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T150	6		T17	3		T136	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	8		T12	10		T132	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T253	17		T163	4		T159	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	2		T134	8		T146	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T224	14		T253	7		T272	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T231	5		T268	9		T80	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T35	2		T241	10		T267	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T1	1		T11	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T132	4		T269	6		T289	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T37	3		T134	10		T146	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T148	15		T225	1		T161	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T334	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T132	1		T335	1		T329	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	1		T27	1		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	3		T148	3		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	10		T37	2		T223	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T14	3		T142	1		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	12		T142	1		T161	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T2	1		T11	8		T133	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T2	1		T9	11		T137	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T31	23		T32	4		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T2	1		T12	1		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T6	2		T7	6		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T144	5		T34	11		T308	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T12	1		T24	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	7		T28	14		T38	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	2		T142	1		T150	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T7	9		T12	1		T29	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	10		T40	1		T243	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T1	3		T28	9		T231	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T28	9		T245	3		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T134	8		T146	8		T147	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T267	5		T277	7		T88	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T132	4		T335	12		T329	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	1		T16	2		T150	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T15	1		T274	9		T45	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T13	7		T223	6		T39	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T14	1		T196	13		T221	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	11		T144	8		T292	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T2	8		T11	8		T133	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T2	4		T137	8		T232	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T31	21		T32	13		T257	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T2	9		T12	13		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	1		T7	5		T31	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T144	8		T34	12		T308	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	7		T27	15		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T38	9		T253	11		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T150	6		T17	3		T136	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T7	8		T12	10		T29	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T163	4		T235	7		T22	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	2		T231	5		T294	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T224	14		T253	24		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T16	4		T223	7		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T15	3		T148	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	8		T37	2		T39	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	3		T196	14		T221	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	12		T9	1		T137	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T2	9		T11	9		T32	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	5		T134	12		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T31	42		T204	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T2	10		T12	14		T34	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	2		T7	6		T12	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	1		T144	9		T145	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T24	1		T27	16		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T28	1		T29	16		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T149	1		T142	1		T150	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	9		T12	11		T148	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T141	1		T40	1		T243	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	3		T28	1		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T28	1		T148	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T37	2		T231	6		T268	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T222	1		T143	1		T311	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16978	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T132	5		T269	11		T289	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T16	2		T223	6		T41	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	1		T148	2		T274	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	9		T39	12		T245	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T14	1		T221	16		T246	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	11		T9	10		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	7		T32	3		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T134	10		T40	6		T232	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	31		T141	14		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T34	10		T145	17		T84	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	1		T7	5		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T13	6		T144	4		T145	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T156	13		T18	1		T162	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T28	13		T30	15		T151	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T150	8		T17	3		T237	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	8		T148	6		T252	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T141	9		T243	7		T244	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	2		T28	8		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T28	8		T148	14		T245	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T37	1		T231	6		T310	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T241	8		T326	14		T255	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T150	10		T224	2		T186	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T269	5		T289	14		T322	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T37	2		T134	9		T146	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T148	1		T225	1		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T334	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T132	5		T335	13		T329	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	2		T27	1		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	3		T148	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T13	8		T37	2		T223	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	3		T142	1		T196	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	12		T142	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	9		T11	9		T133	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	5		T9	1		T137	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T31	24		T32	14		T204	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	10		T12	14		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	2		T7	6		T31	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T144	9		T34	13		T308	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	8		T24	1		T27	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	1		T28	1		T38	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T149	2		T142	1		T150	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T7	9		T12	11		T29	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	1		T40	1		T243	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	3		T28	1		T231	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T28	1		T245	1		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T37	1		T134	9		T146	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T148	14		T161	15		T187	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T16	2		T150	10		T41	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T15	1		T148	2		T274	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	9		T223	6		T39	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T221	16		T246	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	11		T161	17		T144	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	7		T133	8		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T9	10		T137	7		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T31	20		T32	3		T141	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T134	10		T40	6		T145	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T6	1		T7	5		T31	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T144	4		T34	10		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T156	13		T143	11		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	6		T28	13		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T150	8		T17	3		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T7	8		T30	15		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T141	9		T243	7		T244	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	2		T28	8		T231	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T28	8		T245	2		T224	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1