Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19647

1

T1

20

T2

5

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

5885

1

T2

19

T9

11

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19594

1

T1

15

T2

14

T3

13

auto[1]

5938

1

T1

5

T2

10

T9

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T322	7		T329	7		T275	23
values[0]	77	1			T34	23		T145	32		T334	1
values[1]	638	1			T28	14		T142	1		T141	10
values[2]	733	1			T7	11		T13	7		T222	1
values[3]	617	1			T37	3		T132	9		T150	13
values[4]	561	1			T1	5		T148	22		T142	1
values[5]	444	1			T12	8		T14	4		T27	16
values[6]	832	1			T2	15		T5	23		T7	17
values[7]	566	1			T37	2		T149	1		T132	1
values[8]	636	1			T2	9		T6	3		T12	11
values[9]	3480	1			T11	18		T12	14		T13	17
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	798	1			T28	14		T142	1		T141	10
values[1]	2963	1			T13	7		T29	16		T30	17
values[2]	682	1			T7	11		T148	15		T142	1
values[3]	436	1			T1	5		T12	8		T148	7
values[4]	683	1			T2	5		T5	23		T14	4
values[5]	651	1			T2	10		T7	17		T9	11
values[6]	537	1			T2	9		T6	3		T31	29
values[7]	616	1			T12	11		T28	18		T137	16
values[8]	955	1			T11	18		T12	14		T27	1
values[9]	278	1			T13	17		T31	1		T132	5
minimum	16933	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	14		T141	10		T156	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T142	1		T222	1		T17	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T150	7		T225	1		T244	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1659	1			T13	7		T29	2		T30	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	6		T148	15		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T142	1		T184	1		T35	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T1	3		T12	1		T148	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T204	1		T150	11		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T5	12		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	3		T31	11		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	9		T24	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T2	1		T9	11		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	2		T31	12		T246	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T2	1		T15	3		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T28	9		T137	8		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T28	9		T148	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	8		T135	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T11	1		T12	1		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T31	1		T132	1		T247	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	10		T39	16		T256	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T238	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T144	16		T34	12		T145	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T17	3		T144	19		T145	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T150	6		T273	2		T231	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1088	1			T29	14		T160	4		T189	32
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T7	5		T132	8		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T184	8		T35	2		T272	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T1	2		T12	7		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T150	15		T39	1		T41	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	4		T5	11		T27	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T14	1		T31	11		T133	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	8		T40	2		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	9		T257	9		T260	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	1		T31	17		T18	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T2	8		T15	1		T134	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T137	8		T146	14		T290	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	10		T253	17		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	8		T229	11		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	1		T12	13		T31	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T132	4		T247	10		T80	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T13	7		T39	8		T322	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T238	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T329	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T322	5		T275	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T34	11		T336	3		T306	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T145	18		T334	1		T337	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T28	14		T141	10		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T142	1		T17	5		T144	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T7	6		T244	2		T145	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T13	7		T222	1		T253	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T132	1		T150	7		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T37	3		T35	1		T272	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	3		T148	22		T223	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T142	1		T150	11		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T12	1		T27	1		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	3		T204	1		T253	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T2	1		T5	12		T7	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T2	1		T9	11		T31	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	2		T224	15		T246	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T149	1		T132	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	2		T137	8		T161	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	1		T12	1		T28	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	8		T28	9		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1767	1			T11	1		T12	1		T13	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T329	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T322	2		T275	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T34	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T145	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T144	16		T308	12		T240	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T17	3		T144	19		T231	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T7	5		T145	2		T227	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T253	11		T242	1		T162	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T132	8		T150	6		T136	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	2		T272	5		T285	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T1	2		T223	6		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T150	15		T39	1		T184	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	7		T27	15		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T14	1		T253	7		T164	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T2	4		T5	11		T7	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T2	9		T31	11		T133	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T224	12		T18	1		T267	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T134	11		T143	15		T186	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T6	1		T137	8		T146	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T2	8		T12	10		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T11	8		T132	4		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1172	1			T11	1		T12	13		T13	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T28	1		T141	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T142	1		T222	1		T17	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T150	7		T225	1		T244	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1453	1			T13	1		T29	16		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	6		T148	1		T132	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T142	1		T184	9		T35	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T1	3		T12	8		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T204	1		T150	16		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	5		T5	12		T27	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	3		T31	12		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	9		T24	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T2	10		T9	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	2		T31	18		T246	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T2	9		T15	3		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	1		T137	9		T15	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	11		T28	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	9		T135	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T11	2		T12	14		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T31	1		T132	5		T247	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T13	8		T39	13		T256	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T238	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T28	13		T141	9		T156	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T17	3		T144	9		T157	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T150	6		T244	1		T273	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1294	1			T13	6		T30	15		T151	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	5		T148	14		T161	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T272	2		T285	10		T82	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	2		T148	6		T223	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T150	10		T39	1		T41	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	11		T16	2		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T14	1		T31	10		T133	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	8		T40	6		T232	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	10		T243	7		T257	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T6	1		T31	11		T246	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T15	1		T141	9		T134	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T28	8		T137	7		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T28	8		T148	2		T245	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	7		T229	2		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T31	10		T32	3		T150	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T247	13		T188	12		T338	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	9		T39	11		T256	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T238	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T329	7		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T322	3		T275	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T34	13		T336	1		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T145	15		T334	1		T337	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T28	1		T141	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T142	1		T17	5		T144	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	6		T244	1		T145	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T13	1		T222	1		T253	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T132	9		T150	7		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T37	2		T35	3		T272	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	3		T148	2		T223	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	1		T150	16		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	8		T27	16		T16	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T14	3		T204	1		T253	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T2	5		T5	12		T7	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T2	10		T9	1		T31	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T37	2		T224	13		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T149	1		T132	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	2		T137	9		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T2	9		T12	11		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T11	9		T28	1		T31	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1542	1			T11	2		T12	14		T13	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T322	4		T275	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T34	10		T336	2		T306	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T145	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T28	13		T141	9		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	3		T144	9		T157	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T7	5		T244	1		T145	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	6		T253	13		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T150	6		T161	15		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T37	1		T272	2		T285	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	2		T148	20		T223	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T150	10		T39	1		T41	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T16	2		T252	6		T186	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T14	1		T253	9		T339	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	11		T7	8		T31	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	10		T31	10		T133	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T224	14		T246	7		T220	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T141	9		T134	10		T143	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	1		T137	7		T161	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	8		T15	1		T148	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	7		T28	8		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1397	1			T13	9		T30	15		T31	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1