Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22368

1

T1

15

T2

15

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3164

1

T1

5

T2

9

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19785

1

T1

15

T2

10

T3

13

auto[1]

5747

1

T1

5

T2

14

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	368	1			T142	1		T41	7		T143	53
values[0]	84	1			T285	21		T266	21		T258	10
values[1]	512	1			T2	10		T11	2		T13	17
values[2]	722	1			T149	1		T204	1		T142	1
values[3]	704	1			T12	14		T24	1		T150	13
values[4]	462	1			T2	14		T7	17		T28	9
values[5]	2780	1			T5	23		T6	3		T27	17
values[6]	707	1			T12	11		T14	4		T31	22
values[7]	565	1			T9	11		T11	16		T28	9
values[8]	943	1			T28	14		T132	1		T150	15
values[9]	774	1			T1	5		T7	11		T12	8
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	485	1			T2	10		T11	2		T13	17
values[1]	713	1			T149	1		T204	1		T142	1
values[2]	601	1			T12	14		T24	1		T150	13
values[3]	2688	1			T2	14		T5	23		T7	17
values[4]	632	1			T6	3		T27	16		T31	1
values[5]	731	1			T12	11		T14	4		T31	22
values[6]	826	1			T9	11		T11	16		T28	23
values[7]	654	1			T1	5		T12	8		T13	7
values[8]	871	1			T7	11		T31	29		T15	1
values[9]	123	1			T41	7		T265	5		T301	1
minimum	17208	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T2	1		T13	10		T38	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T11	1		T40	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T204	1		T142	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T149	1		T223	7		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T307	1		T260	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T24	1		T150	7		T156	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1523	1			T2	1		T5	12		T7	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	1		T27	1		T37	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T148	10		T40	8		T254	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	2		T27	1		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T32	4		T261	1		T253	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T12	1		T14	3		T31	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	8		T134	10		T221	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	11		T28	23		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T141	15		T39	16		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	3		T12	1		T13	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T7	6		T148	15		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T31	12		T15	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T340	1		T341	1		T342	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T41	4		T265	3		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16853	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T135	1		T186	6		T266	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T2	9		T13	7		T38	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T11	1		T343	9		T235	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T136	16		T241	2		T268	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T223	6		T132	4		T184	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	13		T260	15		T272	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T150	6		T144	16		T146	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	971	1			T2	4		T5	11		T7	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T2	8		T16	2		T227	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T40	2		T162	10		T147	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	1		T27	15		T232	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T32	13		T253	11		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	10		T14	1		T31	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	8		T134	8		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T150	15		T196	13		T134	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	8		T144	19		T224	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	2		T12	7		T31	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	5		T39	1		T143	29
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T31	17		T132	8		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T340	3		T342	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T41	3		T265	2		T344	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T186	11		T266	10		T165	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T143	24		T253	15		T220	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T142	1		T41	4		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T285	16		T101	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T266	11		T258	8		T259	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T2	1		T13	10		T38	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	1		T135	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T204	1		T142	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T149	1		T223	7		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T12	1		T222	1		T307	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T24	1		T150	7		T156	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	1		T7	9		T28	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	1		T37	3		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1471	1			T5	12		T29	2		T30	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T6	2		T27	2		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T32	4		T261	1		T253	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	1		T14	3		T31	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	8		T134	10		T257	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	11		T28	9		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T141	15		T39	16		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T28	14		T132	1		T150	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	6		T148	15		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	3		T12	1		T13	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T143	29		T253	17		T304	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T41	3		T18	2		T265	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T285	5		T101	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T266	10		T258	2		T259	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T2	9		T13	7		T38	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	1		T186	11		T343	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	16		T241	2		T268	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T223	6		T132	4		T184	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T12	13		T260	15		T272	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T150	6		T144	8		T273	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T2	4		T7	8		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T2	8		T144	8		T193	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T5	11		T29	14		T160	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	1		T27	15		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T32	13		T253	11		T162	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	10		T14	1		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	8		T134	8		T257	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T150	15		T206	3		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T39	8		T144	19		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T150	6		T196	13		T134	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	5		T39	1		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	2		T12	7		T31	27
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	10		T13	8		T38	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	2		T40	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T204	1		T142	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T149	1		T223	7		T132	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	14		T307	1		T260	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T24	1		T150	7		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T2	5		T5	12		T7	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	9		T27	1		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T148	2		T40	4		T254	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	2		T27	16		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T32	14		T261	1		T253	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	11		T14	3		T31	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	9		T134	9		T221	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	1		T28	2		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T141	1		T39	13		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	3		T12	8		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	6		T148	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T31	18		T15	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T340	4		T341	1		T342	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T41	5		T265	5		T301	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T135	1		T186	12		T266	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	9		T38	6		T161	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T249	11		T220	12		T343	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T191	12		T241	4		T230	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T223	6		T245	2		T244	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T272	2		T274	4		T187	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T150	6		T156	13		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1193	1			T5	11		T7	8		T28	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T37	1		T16	2		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T148	8		T40	6		T254	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	1		T232	10		T246	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	3		T253	13		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T14	1		T31	10		T137	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	7		T134	9		T221	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	10		T28	21		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T141	14		T39	11		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T1	2		T13	6		T31	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T7	5		T148	14		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T31	11		T243	7		T17	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T342	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T41	2		T275	11		T345	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T292	2		T285	10		T187	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T186	5		T266	10		T346	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T143	31		T253	18		T220	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T142	1		T41	5		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T285	11		T101	2		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T266	11		T258	3		T259	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	10		T13	8		T38	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	2		T135	1		T226	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T204	1		T142	1		T136	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T149	1		T223	7		T132	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	14		T222	1		T307	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T24	1		T150	7		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	5		T7	9		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T2	9		T37	2		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T5	12		T29	16		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	2		T27	17		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T32	14		T261	1		T253	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	11		T14	3		T31	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	9		T134	9		T257	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	1		T28	1		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T141	1		T39	13		T144	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T28	1		T132	1		T150	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T7	6		T148	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	3		T12	8		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T143	22		T253	14		T220	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T41	2		T18	1		T241	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T285	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T266	10		T258	7		T271	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	9		T38	6		T161	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T186	5		T249	11		T343	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T191	12		T241	4		T249	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T223	6		T224	14		T221	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T272	2		T274	4		T187	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T150	6		T156	13		T245	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	8		T28	8		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T37	1		T141	9		T144	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1146	1			T5	11		T30	15		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	1		T16	2		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T32	3		T253	13		T254	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T14	1		T31	10		T137	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	7		T134	9		T257	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	10		T28	8		T150	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T141	14		T39	11		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	13		T150	8		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	5		T148	14		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T1	2		T13	6		T31	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1