Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22444

1

T1

15

T2

9

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3088

1

T1

5

T2

15

T7

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19718

1

T1

20

T2

5

T3

13

auto[1]

5814

1

T2

19

T5

23

T7

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	205	1			T9	11		T14	4		T222	1
values[0]	59	1			T143	27		T285	21		T281	6
values[1]	529	1			T2	9		T31	1		T15	1
values[2]	878	1			T7	17		T24	1		T27	1
values[3]	489	1			T6	3		T32	17		T204	1
values[4]	606	1			T12	11		T137	16		T132	9
values[5]	2846	1			T7	11		T11	2		T29	16
values[6]	685	1			T2	5		T13	17		T28	9
values[7]	594	1			T27	16		T31	21		T132	5
values[8]	542	1			T2	10		T5	23		T12	22
values[9]	1188	1			T1	5		T11	16		T28	23
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	660	1			T2	9		T24	1		T31	1
values[1]	729	1			T7	17		T27	1		T31	29
values[2]	500	1			T6	3		T32	17		T204	1
values[3]	2793	1			T11	2		T12	11		T29	16
values[4]	693	1			T7	11		T15	4		T148	18
values[5]	663	1			T2	5		T13	17		T28	9
values[6]	592	1			T2	10		T27	16		T132	5
values[7]	663	1			T5	23		T11	16		T12	22
values[8]	982	1			T1	5		T9	11		T28	14
values[9]	154	1			T14	4		T196	14		T135	1
minimum	17103	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T2	1		T24	1		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	1		T148	7		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T31	12		T37	2		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	9		T27	1		T144	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T6	2		T204	1		T133	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T32	4		T136	1		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1529	1			T12	1		T29	2		T30	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	1		T37	3		T38	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T225	1		T17	5		T244	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	6		T15	3		T148	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T28	9		T150	9		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T2	1		T13	10		T31	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T27	1		T252	7		T221	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T2	1		T132	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	12		T11	8		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	1		T13	7		T28	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T28	14		T142	1		T39	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	3		T9	11		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T261	1		T18	1		T147	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T14	3		T196	1		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16845	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T141	10		T300	1		T80	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	8		T136	16		T143	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T144	8		T221	14		T285	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T31	17		T241	10		T182	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	8		T144	19		T253	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T6	1		T133	7		T272	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T32	13		T147	10		T289	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T12	10		T29	14		T160	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T11	1		T38	9		T290	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	3		T186	11		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	5		T15	1		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T150	6		T39	1		T41	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T2	4		T13	7		T31	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T27	15		T221	2		T34	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T2	9		T132	4		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	11		T11	8		T12	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	7		T16	2		T223	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T39	8		T40	2		T143	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	2		T229	11		T253	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T18	1		T147	10		T280	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T14	1		T196	13		T292	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T80	11		T322	2		T305	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T224	3		T18	1		T273	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T9	11		T14	3		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T143	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T285	16		T281	6		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T31	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T15	1		T148	7		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T24	1		T31	12		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T7	9		T27	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	2		T204	1		T245	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T32	4		T136	1		T286	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	1		T137	8		T132	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T38	11		T222	1		T331	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T29	2		T30	17		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	6		T11	1		T15	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T28	9		T150	9		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T2	1		T13	10		T31	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T27	1		T252	7		T34	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T31	11		T132	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	12		T12	1		T150	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T2	1		T12	1		T13	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T11	8		T28	14		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T1	3		T28	9		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T224	2		T18	1		T273	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T14	1		T296	3		T193	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T143	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T285	5		T305	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T2	8		T253	11		T145	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T144	8		T80	11		T280	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T31	17		T136	16		T241	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	8		T144	19		T253	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T6	1		T272	5		T294	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T32	13		T147	10		T233	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	10		T137	8		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T38	9		T290	4		T164	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T29	14		T160	4		T189	32
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	5		T11	1		T15	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T150	6		T39	1		T41	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T2	4		T13	7		T31	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T27	15		T34	12		T162	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T31	10		T132	4		T224	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	11		T12	13		T150	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T2	9		T12	7		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T11	8		T39	8		T40	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	2		T223	6		T196	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T2	9		T24	1		T31	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	1		T148	1		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T31	18		T37	2		T149	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	9		T27	1		T144	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T6	2		T204	1		T133	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	14		T136	1		T286	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T12	11		T29	16		T30	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	2		T37	2		T38	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T225	1		T17	5		T244	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	6		T15	3		T148	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	1		T150	7		T39	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T2	5		T13	8		T31	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T27	16		T252	1		T221	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T2	10		T132	5		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	12		T11	9		T12	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	8		T13	1		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T28	1		T142	1		T39	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	3		T9	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T261	1		T18	2		T147	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T14	3		T196	14		T135	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16950	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T141	1		T300	1		T80	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T143	11		T157	17		T145	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T148	6		T156	13		T144	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T31	11		T245	2		T161	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	8		T144	9		T253	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T133	8		T272	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T32	3		T147	9		T289	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T30	15		T137	7		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T37	1		T38	6		T290	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T17	3		T244	1		T186	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	5		T15	1		T148	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T28	8		T150	8		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	9		T31	20		T243	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T252	6		T221	4		T34	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T161	15		T224	14		T146	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	11		T11	7		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T13	6		T28	8		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T28	13		T39	11		T40	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	2		T9	10		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T147	13		T280	12		T347	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T14	1		T292	2		T296	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T253	13		T348	16		T349	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T141	9		T322	4		T87	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T224	3		T18	2		T273	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T9	1		T14	3		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T143	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T285	11		T281	1		T305	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T2	9		T31	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T15	1		T148	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T24	1		T31	18		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T7	9		T27	1		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T6	2		T204	1		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T32	14		T136	1		T286	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T12	11		T137	9		T132	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T38	14		T222	1		T331	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T29	16		T30	2		T160	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	6		T11	2		T15	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T28	1		T150	7		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T2	5		T13	8		T31	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T27	16		T252	1		T34	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T31	11		T132	5		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T5	12		T12	14		T150	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T2	10		T12	8		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T11	9		T28	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T1	3		T28	1		T142	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T224	2		T273	4		T274	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T9	10		T14	1		T262	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T143	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T285	10		T281	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T253	13		T157	17		T145	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T148	6		T141	9		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T31	11		T161	17		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	8		T144	9		T253	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	1		T245	2		T272	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T32	3		T147	9		T266	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T137	7		T133	8		T134	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T38	6		T290	2		T164	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T30	15		T151	7		T203	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	5		T15	1		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T28	8		T150	8		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	9		T31	10		T148	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T252	6		T34	10		T162	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T31	10		T224	14		T146	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	11		T150	10		T134	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T13	6		T16	2		T161	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T11	7		T28	13		T39	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T1	2		T28	8		T223	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1