Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22134

1

T1

20

T2

24

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3398

1

T7

28

T9

11

T11

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19715

1

T1

15

T2

14

T3

13

auto[1]

5817

1

T1

5

T2

10

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	181	1			T134	22		T225	1		T206	4
values[0]	43	1			T297	21		T100	12		T284	10
values[1]	581	1			T7	17		T11	16		T24	1
values[2]	2937	1			T1	5		T14	4		T28	9
values[3]	464	1			T11	2		T31	1		T150	15
values[4]	632	1			T13	7		T27	16		T28	14
values[5]	680	1			T12	25		T28	9		T15	1
values[6]	577	1			T9	11		T12	8		T27	1
values[7]	636	1			T2	10		T6	3		T7	11
values[8]	760	1			T13	17		T148	3		T37	2
values[9]	1130	1			T2	14		T5	23		T32	17
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	707	1			T7	17		T11	16		T14	4
values[1]	2767	1			T1	5		T29	16		T30	17
values[2]	656	1			T11	2		T27	16		T142	1
values[3]	529	1			T13	7		T28	14		T142	1
values[4]	796	1			T9	11		T12	33		T27	1
values[5]	424	1			T2	10		T6	3		T150	13
values[6]	652	1			T7	11		T142	1		T223	13
values[7]	786	1			T13	17		T148	3		T37	2
values[8]	931	1			T2	14		T5	23		T32	17
values[9]	154	1			T15	4		T134	22		T262	14
minimum	17130	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	3		T24	1		T31	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	9		T11	8		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1465	1			T1	3		T29	2		T30	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T148	15		T225	1		T292	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	1		T142	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T27	1		T150	9		T245	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T28	14		T142	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	7		T132	1		T144	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	2		T27	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	11		T12	1		T28	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	1		T6	2		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T300	1		T230	3		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T142	1		T223	7		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	6		T225	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	10		T148	3		T221	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T37	2		T39	16		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T2	2		T5	12		T32	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T137	8		T225	1		T161	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T134	11		T301	1		T304	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T15	3		T262	14		T233	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16822	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T31	11		T38	11		T156	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	1		T31	27		T16	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	8		T11	8		T224	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T1	2		T29	14		T160	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T292	2		T242	1		T237	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T39	1		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	15		T150	6		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T265	2		T309	11		T54	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T132	4		T144	8		T257	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T12	17		T40	2		T143	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	13		T144	19		T253	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T2	9		T6	1		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T303	15		T288	1		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T223	6		T133	7		T196	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	5		T143	14		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	7		T221	10		T260	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	8		T144	8		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T2	12		T5	11		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T137	8		T224	12		T206	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T134	11		T304	5		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T15	1		T233	11		T305	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T31	11		T38	9		T350	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T134	11		T301	1		T164	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T225	1		T206	1		T18	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T297	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T100	1		T284	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T24	1		T31	11		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	9		T11	8		T31	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1534	1			T1	3		T14	3		T29	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T28	9		T148	15		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	1		T31	1		T244	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T150	9		T243	8		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T28	14		T142	1		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	7		T27	1		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	1		T15	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T12	1		T28	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	1		T27	1		T150	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T9	11		T144	10		T300	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T2	1		T6	2		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	6		T225	1		T307	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	10		T148	3		T196	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T37	2		T222	1		T143	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T2	2		T5	12		T32	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T137	8		T15	3		T39	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T134	11		T164	10		T175	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T206	3		T18	2		T305	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T297	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T100	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T31	10		T16	2		T41	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	8		T11	8		T31	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T1	2		T14	1		T29	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T292	2		T242	1		T237	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	1		T136	16		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T150	6		T17	3		T308	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T39	1		T221	2		T265	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T27	15		T132	4		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	10		T40	2		T221	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	13		T253	17		T145	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	7		T150	6		T143	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T144	19		T272	5		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	9		T6	1		T223	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T7	5		T231	11		T248	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	7		T196	13		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T143	14		T144	8		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T2	12		T5	11		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T137	8		T15	1		T39	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	3		T24	1		T31	29
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	9		T11	9		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T1	3		T29	16		T30	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T148	1		T225	1		T292	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	2		T142	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T27	16		T150	7		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T28	1		T142	1		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T132	5		T144	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T12	19		T27	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	1		T12	14		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T2	10		T6	2		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T300	1		T230	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T142	1		T223	7		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	6		T225	1		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	8		T148	1		T221	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T37	2		T39	13		T222	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	14		T5	12		T32	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T137	9		T225	1		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T134	12		T301	1		T304	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T15	3		T262	1		T233	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16948	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T31	12		T38	14		T156	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T31	21		T148	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	8		T11	7		T28	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T1	2		T30	15		T151	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T148	14		T292	2		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	1		T244	1		T221	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T150	8		T245	11		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T28	13		T309	12		T283	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	6		T144	4		T257	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T40	6		T143	11		T221	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	10		T28	8		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T150	6		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T230	2		T220	4		T310	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T223	6		T133	8		T224	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	5		T143	11		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	9		T148	2		T221	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T39	11		T144	13		T157	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	11		T32	3		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T137	7		T161	15		T224	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T134	10		T304	11		T201	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T15	1		T262	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T297	7		T351	11		T352	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T31	10		T38	6		T156	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T134	12		T301	1		T164	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T225	1		T206	4		T18	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T297	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T100	12		T284	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T24	1		T31	11		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	9		T11	9		T31	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T1	3		T14	3		T29	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	1		T148	1		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	2		T31	1		T244	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	7		T243	1		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	1		T142	1		T39	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	1		T27	16		T132	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T12	11		T15	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T12	14		T28	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	8		T27	1		T150	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	1		T144	20		T300	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T2	10		T6	2		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T7	6		T225	1		T307	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	8		T148	1		T196	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T37	2		T222	1		T143	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T2	14		T5	12		T32	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T137	9		T15	3		T39	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T134	10		T164	14		T201	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T18	1		T346	11		T353	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T297	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T284	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T31	10		T16	2		T141	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	8		T11	7		T31	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T1	2		T14	1		T30	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	8		T148	14		T292	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T244	1		T157	2		T19	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T150	8		T243	7		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T28	13		T39	1		T221	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	6		T245	11		T144	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T40	6		T221	16		T256	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	8		T253	14		T145	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T150	6		T161	17		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T9	10		T144	9		T272	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	1		T223	6		T133	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	5		T231	12		T230	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	9		T148	2		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T143	11		T144	13		T157	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T5	11		T32	3		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T137	7		T15	1		T39	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1