Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T2	10		T13	8		T38	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	2		T40	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T204	1		T142	1		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T149	1		T223	7		T132	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T2	5		T12	14		T260	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T24	1		T150	7		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T5	12		T7	9		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T2	9		T27	1		T37	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T148	2		T40	4		T261	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	2		T27	16		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T12	11		T32	14		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T14	3		T31	12		T137	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	9		T134	9		T262	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T9	1		T28	2		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	1		T141	1		T39	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	3		T12	8		T13	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T141	1		T39	4		T17	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T31	29		T148	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T7	6		T263	12		T264	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T41	5		T229	12		T265	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T135	1		T266	11		T259	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	9		T38	6		T161	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T186	5		T249	11		T81	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T245	2		T241	4		T230	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T223	6		T244	1		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T272	2		T274	4		T187	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T150	6		T156	13		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1206	1			T5	11		T7	8		T28	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T37	1		T16	2		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T148	8		T40	6		T248	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	1		T232	10		T246	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T32	3		T253	13		T231	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T31	10		T137	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	7		T134	9		T262	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	10		T28	21		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T141	14		T39	11		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	2		T13	6		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T141	9		T39	1		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T31	21		T148	14		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T7	5		T270	2		T275	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T41	2		T229	2		T167	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T266	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T213	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T226	1		T258	3		T259	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T2	10		T13	8		T38	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	2		T135	1		T186	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T204	1		T142	1		T136	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T149	1		T223	7		T132	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	14		T245	1		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T156	1		T245	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T2	5		T7	9		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T2	9		T24	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T5	12		T29	16		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	2		T27	1		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	11		T32	14		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T14	3		T27	16		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	9		T149	1		T134	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	1		T132	1		T150	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T141	1		T39	13		T144	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T28	1		T150	7		T196	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	353	1			T7	6		T15	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T1	3		T12	8		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T258	7		T271	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	9		T38	6		T161	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T186	5		T249	11		T266	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T241	4		T249	10		T269	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T223	6		T144	13		T224	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T245	2		T272	2		T274	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T156	13		T245	11		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	8		T28	8		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T37	1		T150	6		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T5	11		T30	15		T151	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T6	1		T16	2		T232	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T32	3		T148	6		T40	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	1		T28	8		T31	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	7		T134	9		T257	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	10		T150	10		T253	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T141	14		T39	11		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	13		T150	8		T134	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T7	5		T141	9		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T1	2		T13	6		T31	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1