Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22313

1

T1

15

T2

9

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3219

1

T1

5

T2

15

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19786

1

T1

15

T2

15

T3

13

auto[1]

5746

1

T1

5

T2

9

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	495	1			T5	1		T6	3		T7	1
values[0]	3	1			T82	2		T104	1		-	-
values[1]	727	1			T2	9		T31	29		T141	10
values[2]	2766	1			T2	10		T12	8		T13	17
values[3]	601	1			T7	17		T31	23		T137	16
values[4]	775	1			T6	3		T12	14		T14	4
values[5]	541	1			T1	5		T13	7		T15	1
values[6]	719	1			T11	2		T24	1		T27	1
values[7]	716	1			T5	23		T9	11		T12	11
values[8]	608	1			T11	16		T32	17		T142	1
values[9]	1151	1			T2	5		T7	11		T27	16
minimum	16430	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	904	1			T2	9		T31	29		T141	10
values[1]	2715	1			T2	10		T12	8		T13	17
values[2]	608	1			T6	3		T7	17		T31	23
values[3]	825	1			T1	5		T12	14		T14	4
values[4]	616	1			T11	2		T13	7		T27	1
values[5]	681	1			T12	11		T24	1		T142	2
values[6]	603	1			T5	23		T9	11		T150	15
values[7]	572	1			T11	16		T28	9		T32	17
values[8]	897	1			T2	5		T7	11		T16	6
values[9]	200	1			T27	16		T132	9		T136	17
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T2	1		T141	10		T156	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T31	12		T39	16		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T12	1		T13	10		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T2	1		T148	3		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T148	7		T37	2		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	2		T7	9		T31	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T15	1		T132	1		T245	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	3		T12	1		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	1		T27	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	7		T37	3		T141	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	1		T24	1		T243	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T142	2		T150	11		T141	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	12		T150	9		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	11		T239	1		T274	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	8		T28	9		T32	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T222	1		T157	18		T145	34
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T245	3		T40	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T7	6		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T136	1		T221	15		T18	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T27	1		T132	1		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	8		T206	3		T231	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T31	17		T39	8		T237	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T12	7		T13	7		T29	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T2	9		T39	1		T242	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T133	7		T241	10		T82	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T6	1		T7	8		T31	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T143	15		T221	2		T240	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	2		T12	13		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	1		T265	2		T162	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T196	13		T186	11		T147	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	10		T273	2		T164	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T150	15		T134	8		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	11		T150	6		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T239	11		T274	9		T21	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	8		T32	13		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T145	16		T267	5		T276	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T253	11		T257	9		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T2	4		T7	5		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T136	16		T221	10		T277	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T27	15		T132	8		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	481	1			T5	1		T6	3		T7	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T187	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T82	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T104	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T2	1		T141	10		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T31	12		T225	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T12	1		T13	10		T28	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	1		T148	3		T39	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T148	7		T149	1		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	9		T31	12		T137	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	2		T132	1		T133	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T6	2		T12	1		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T15	1		T245	12		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	3		T13	7		T37	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T24	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T142	1		T150	11		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	12		T12	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	11		T142	1		T141	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	8		T32	4		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T222	1		T157	18		T145	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T28	9		T245	3		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T2	1		T7	6		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16312	1			T1	14		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T82	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T2	8		T206	3		T231	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T31	17		T272	5		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1005	1			T12	7		T13	7		T29	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T2	9		T39	9		T237	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T241	10		T82	4		T279	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	8		T31	11		T137	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T133	7		T143	15		T240	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	1		T12	13		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T221	2		T273	2		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T1	2		T184	8		T147	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T265	2		T164	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T150	15		T134	8		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	11		T12	10		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T40	2		T145	2		T239	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	8		T32	13		T150	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T145	14		T248	12		T276	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	3		T136	16		T253	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T2	4		T7	5		T27	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T2	9		T141	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T31	18		T39	13		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T12	8		T13	8		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T2	10		T148	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T148	1		T37	2		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T6	2		T7	9		T31	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	1		T132	1		T245	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T1	3		T12	14		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	2		T27	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T37	2		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	11		T24	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T142	2		T150	16		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	12		T150	7		T225	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	1		T239	12		T274	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	9		T28	1		T32	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T222	1		T157	1		T145	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T245	1		T40	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T2	5		T7	6		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T136	17		T221	11		T18	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T27	16		T132	9		T35	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T141	9		T156	13		T244	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T31	11		T39	11		T161	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T13	9		T28	8		T30	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T148	2		T39	1		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T148	6		T133	8		T254	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	1		T7	8		T31	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T245	11		T143	11		T221	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	2		T14	1		T28	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T262	13		T280	14		T266	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	6		T37	1		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T243	7		T273	4		T81	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T150	10		T141	14		T134	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	11		T150	8		T143	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T9	10		T274	4		T201	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	7		T28	8		T32	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T157	17		T145	32		T281	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T245	2		T253	13		T246	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	5		T16	2		T223	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T221	14		T277	4		T282	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T283	12		T96	10		T284	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	481	1			T5	1		T6	3		T7	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T187	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T82	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T104	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	9		T141	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T31	18		T225	1		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T12	8		T13	8		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T2	10		T148	1		T39	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T148	1		T149	1		T278	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	9		T31	13		T137	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	2		T132	1		T133	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	2		T12	14		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T15	1		T245	1		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T1	3		T13	1		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	2		T24	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T142	1		T150	16		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T5	12		T12	11		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	1		T142	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	9		T32	14		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T222	1		T157	1		T145	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T28	1		T245	1		T40	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	428	1			T2	5		T7	6		T27	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16430	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T187	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T141	9		T156	13		T244	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T31	11		T157	2		T272	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T13	9		T28	8		T30	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T148	2		T39	12		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T148	6		T254	10		T241	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	8		T31	10		T137	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T133	8		T143	11		T249	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	1		T14	1		T28	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T245	11		T221	4		T262	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	2		T13	6		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T243	7		T164	4		T280	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T150	10		T141	9		T134	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	11		T143	11		T182	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	10		T141	14		T40	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	7		T32	3		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T157	17		T145	17		T248	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T28	8		T245	2		T41	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	5		T16	2		T223	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1