Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22176

1

T1

20

T2

24

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3356

1

T7

28

T9

11

T11

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19791

1

T1

15

T2

14

T3

13

auto[1]

5741

1

T1

5

T2

10

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T109	16		-	-		-	-
values[0]	85	1			T297	21		T298	24		T299	15
values[1]	529	1			T7	17		T11	16		T24	1
values[2]	2949	1			T1	5		T14	4		T28	9
values[3]	479	1			T11	2		T27	16		T28	14
values[4]	608	1			T13	7		T142	1		T132	5
values[5]	635	1			T12	25		T27	1		T28	9
values[6]	658	1			T9	11		T12	8		T150	13
values[7]	611	1			T2	10		T6	3		T7	11
values[8]	715	1			T13	17		T148	3		T37	2
values[9]	1336	1			T2	14		T5	23		T32	17
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	885	1			T7	17		T11	16		T14	4
values[1]	2796	1			T1	5		T29	16		T30	17
values[2]	655	1			T11	2		T142	1		T150	15
values[3]	529	1			T13	7		T27	16		T28	14
values[4]	803	1			T9	11		T12	33		T27	1
values[5]	431	1			T2	10		T6	3		T150	13
values[6]	647	1			T7	11		T142	1		T223	13
values[7]	767	1			T148	3		T37	2		T39	24
values[8]	893	1			T2	14		T5	23		T13	17
values[9]	214	1			T15	4		T134	22		T225	1
minimum	16912	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T14	3		T24	1		T31	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T7	9		T11	8		T28	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1501	1			T1	3		T29	2		T30	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T148	15		T225	1		T292	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	1		T142	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T150	9		T245	12		T243	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T27	1		T28	14		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	7		T132	1		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T12	2		T27	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	11		T12	1		T28	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T2	1		T6	2		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T300	1		T230	3		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T142	1		T223	7		T133	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	6		T225	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T148	3		T221	15		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T37	2		T39	16		T144	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T2	2		T5	12		T13	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T137	8		T161	16		T224	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T134	11		T252	7		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T15	3		T225	1		T262	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T14	1		T31	10		T16	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T7	8		T11	8		T31	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T1	2		T29	14		T31	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T292	2		T242	1		T237	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	1		T39	1		T136	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	6		T17	3		T253	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T27	15		T265	2		T158	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T132	4		T144	8		T257	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T12	17		T40	2		T143	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	13		T144	19		T253	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T2	9		T6	1		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T303	15		T96	10		T288	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T223	6		T133	7		T196	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	5		T143	14		T231	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T221	10		T260	15		T45	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T39	8		T144	8		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T2	12		T5	11		T13	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T137	8		T224	12		T206	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T134	11		T304	5		T175	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T15	1		T233	11		T305	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T109	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T297	8		T298	12		T306	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T299	1		T100	1		T284	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T24	1		T31	11		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	9		T11	8		T31	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1536	1			T1	3		T14	3		T29	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T28	9		T148	15		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T27	1		T28	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T150	9		T243	8		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T142	1		T39	4		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	7		T132	1		T245	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T27	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T28	9		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T150	7		T40	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	11		T144	10		T300	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T2	1		T6	2		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	6		T225	1		T307	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T13	10		T148	3		T224	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T37	2		T222	1		T143	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T2	2		T5	12		T32	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	417	1			T137	8		T15	3		T39	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T109	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T297	13		T298	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T299	14		T100	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T31	10		T16	2		T268	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	8		T11	8		T31	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T1	2		T14	1		T29	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T292	2		T242	1		T237	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	1		T27	15		T136	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T150	6		T17	3		T308	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	1		T221	2		T265	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T132	4		T144	8		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	10		T221	14		T239	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	13		T253	17		T145	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	7		T150	6		T40	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	19		T272	5		T182	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T2	9		T6	1		T223	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T7	5		T231	11		T248	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	7		T224	2		T260	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T143	14		T144	8		T18	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T2	12		T5	11		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T137	8		T15	1		T39	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	3		T24	1		T31	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	9		T11	9		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T1	3		T29	16		T30	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T148	1		T225	1		T292	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	2		T142	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T150	7		T245	1		T243	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T27	16		T28	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T132	5		T226	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T12	19		T27	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	1		T12	14		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T2	10		T6	2		T150	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T300	1		T230	1		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T142	1		T223	7		T133	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	6		T225	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T148	1		T221	11		T260	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	2		T39	13		T144	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T2	14		T5	12		T13	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T137	9		T161	1		T224	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T134	12		T252	1		T301	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T15	3		T225	1		T262	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T302	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T14	1		T31	10		T148	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T7	8		T11	7		T28	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T1	2		T30	15		T31	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T148	14		T292	2		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T39	1		T244	1		T221	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T150	8		T245	11		T243	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T28	13		T309	12		T283	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	6		T144	4		T257	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T40	6		T143	11		T221	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	10		T28	8		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	1		T150	6		T245	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T230	2		T220	4		T310	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T223	6		T133	8		T224	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	5		T143	11		T231	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T148	2		T221	14		T45	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	11		T144	13		T157	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	11		T13	9		T32	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T137	7		T161	15		T224	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T134	10		T252	6		T304	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T15	1		T262	13		T102	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T109	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T297	14		T298	13		T306	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T299	15		T100	12		T284	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T24	1		T31	11		T16	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	9		T11	9		T31	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	3		T14	3		T29	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T28	1		T148	1		T204	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	2		T27	16		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T150	7		T243	1		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T142	1		T39	4		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	1		T132	5		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	11		T27	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	14		T28	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	8		T150	7		T40	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	1		T144	20		T300	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	10		T6	2		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T7	6		T225	1		T307	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	8		T148	1		T224	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T37	2		T222	1		T143	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T2	14		T5	12		T32	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T137	9		T15	3		T39	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T109	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T297	7		T298	11		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T284	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T31	10		T16	2		T141	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	8		T11	7		T31	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T1	2		T14	1		T30	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	8		T148	14		T292	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T28	13		T141	14		T244	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T150	8		T243	7		T17	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	1		T221	4		T147	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T13	6		T245	11		T144	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T221	16		T256	10		T241	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	8		T253	14		T145	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T150	6		T40	6		T161	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	10		T144	9		T272	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	1		T223	6		T133	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	5		T231	12		T230	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	9		T148	2		T224	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T143	11		T144	13		T157	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T5	11		T32	3		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T137	7		T15	1		T39	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1