Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22208

1

T1

20

T3

13

T4

20

auto[ADC_CTRL_FILTER_COND_OUT]

3324

1

T2

24

T6

3

T7

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19530

1

T1

15

T2

24

T3

13

auto[1]

6002

1

T1

5

T5

24

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	761	1			T5	1		T6	3		T7	12
values[0]	2	1			T82	2		-	-		-	-
values[1]	716	1			T2	9		T31	29		T141	10
values[2]	2774	1			T2	10		T12	8		T13	17
values[3]	596	1			T7	17		T31	23		T137	16
values[4]	805	1			T6	3		T12	14		T14	4
values[5]	566	1			T1	5		T13	7		T15	1
values[6]	698	1			T11	2		T24	1		T27	1
values[7]	682	1			T5	23		T9	11		T12	11
values[8]	576	1			T11	16		T32	17		T142	1
values[9]	926	1			T2	5		T28	9		T16	6
minimum	16430	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	747	1			T2	9		T31	29		T148	3
values[1]	2728	1			T2	10		T12	8		T13	17
values[2]	696	1			T6	3		T7	17		T31	23
values[3]	701	1			T1	5		T12	14		T14	4
values[4]	579	1			T11	2		T13	7		T15	1
values[5]	728	1			T12	11		T24	1		T27	1
values[6]	647	1			T5	23		T9	11		T150	15
values[7]	595	1			T11	16		T28	9		T32	17
values[8]	842	1			T2	5		T7	11		T16	6
values[9]	209	1			T27	16		T132	9		T136	17
minimum	17060	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T31	12		T141	10		T156	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T2	1		T148	3		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T13	10		T28	9		T29	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T2	1		T12	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T137	8		T148	7		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	2		T7	9		T31	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	3		T12	1		T14	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T28	14		T31	11		T148	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	1		T13	7		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T37	3		T141	10		T311	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T12	1		T24	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T142	2		T150	11		T40	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	12		T9	11		T141	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T150	9		T225	1		T261	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	9		T142	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	8		T32	4		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T223	7		T245	3		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T2	1		T7	6		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T136	1		T35	1		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T27	1		T132	1		T221	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16828	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T225	1		T244	2		T313	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T31	17		T39	8		T206	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T2	8		T237	15		T272	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T13	7		T29	14		T160	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T2	9		T12	7		T242	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T137	8		T143	15		T292	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	1		T7	8		T31	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	2		T12	13		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T31	10		T150	6		T38	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	1		T221	2		T186	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T147	1		T80	11		T266	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	10		T134	8		T144	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T150	15		T40	2		T186	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	11		T143	14		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T150	6		T145	2		T239	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T247	10		T227	2		T80	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T11	8		T32	13		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T223	6		T144	19		T253	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T2	4		T7	5		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T136	16		T35	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T27	15		T132	8		T221	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T313	4		T251	16		T314	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	510	1			T5	1		T6	3		T7	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T7	6		T27	1		T132	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T82	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T31	12		T141	10		T156	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T2	1		T225	2		T244	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1571	1			T13	10		T28	9		T29	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T2	1		T12	1		T148	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	8		T148	7		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	9		T31	12		T134	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	1		T14	3		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	2		T28	14		T31	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	3		T13	7		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T37	3		T141	10		T184	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T24	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T142	1		T150	11		T243	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	12		T9	11		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T142	1		T40	8		T261	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T142	1		T222	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	8		T32	4		T150	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T28	9		T223	7		T245	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T2	1		T16	4		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16312	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T136	16		T159	15		T315	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	5		T27	15		T132	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T82	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T31	17		T206	3		T231	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T2	8		T272	5		T294	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T13	7		T29	14		T160	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T2	9		T12	7		T237	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T137	8		T241	10		T234	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	8		T31	11		T134	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T12	13		T14	1		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	1		T31	10		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	2		T221	2		T186	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T184	8		T273	2		T147	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	1		T134	8		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T150	15		T186	3		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T5	11		T12	10		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T40	2		T145	2		T239	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T144	8		T247	10		T227	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T11	8		T32	13		T150	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T223	6		T144	19		T253	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T2	4		T16	2		T132	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T31	18		T141	1		T156	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T2	9		T148	1		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T13	8		T28	1		T29	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T2	10		T12	8		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T137	9		T148	1		T37	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	2		T7	9		T31	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	3		T12	14		T14	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	1		T31	11		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T13	1		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T37	2		T141	1		T311	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	11		T24	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T142	2		T150	16		T40	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	12		T9	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T150	7		T225	1		T261	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	1		T142	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	9		T32	14		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T223	7		T245	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T2	5		T7	6		T16	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T136	17		T35	3		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T27	16		T132	9		T221	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16956	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T225	1		T244	1		T313	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T31	11		T141	9		T156	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T148	2		T161	15		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T13	9		T28	8		T30	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T242	8		T231	13		T168	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T137	7		T148	6		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	1		T7	8		T31	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	2		T14	1		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	13		T31	10		T148	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	6		T243	7		T221	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T37	1		T141	9		T254	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T134	9		T144	13		T164	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T150	10		T40	6		T243	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	11		T9	10		T141	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T150	8		T157	17		T145	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T28	8		T161	17		T247	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	7		T32	3		T41	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T223	6		T245	2		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	5		T16	2		T232	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T221	14		T146	13		T283	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T231	12		T146	2		T248	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T244	1		T313	4		T188	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	540	1			T5	1		T6	3		T7	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	6		T27	16		T132	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T82	2		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T31	18		T141	1		T156	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T2	9		T225	2		T244	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T13	8		T28	1		T29	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T2	10		T12	8		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T137	9		T148	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	9		T31	13		T134	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	14		T14	3		T15	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	2		T28	1		T31	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T1	3		T13	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T37	2		T141	1		T184	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	2		T24	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T142	1		T150	16		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	12		T9	1		T12	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T142	1		T40	4		T261	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T142	1		T222	1		T226	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	9		T32	14		T150	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T28	1		T223	7		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T2	5		T16	4		T132	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16430	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T187	13		T315	2		T277	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T7	5		T232	10		T17	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T31	11		T141	9		T156	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T244	1		T157	2		T272	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T13	9		T28	8		T30	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T148	2		T161	15		T237	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T137	7		T148	6		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	8		T31	10		T134	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	1		T15	1		T143	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	1		T28	13		T31	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	2		T13	6		T245	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T37	1		T141	9		T273	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T134	9		T144	13		T164	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T150	10		T243	7		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	11		T9	10		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T40	6		T145	15		T274	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T161	17		T144	4		T247	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	7		T32	3		T150	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T28	8		T223	6		T245	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T16	2		T41	2		T229	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1