Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22103

1

T1

20

T2

5

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3429

1

T2

19

T7

11

T11

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20044

1

T1

20

T3

13

T4

20

auto[1]

5488

1

T2

24

T5

23

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	233	1			T225	1		T224	5		T239	3
values[0]	12	1			T255	12		-	-		-	-
values[1]	492	1			T2	10		T6	3		T9	11
values[2]	597	1			T2	9		T12	14		T15	1
values[3]	727	1			T2	5		T11	16		T12	11
values[4]	897	1			T7	11		T148	7		T37	2
values[5]	700	1			T148	3		T149	1		T204	1
values[6]	553	1			T11	2		T14	4		T24	1
values[7]	699	1			T12	8		T13	7		T16	6
values[8]	672	1			T1	5		T7	17		T27	1
values[9]	3039	1			T5	23		T29	16		T30	17
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	520	1			T2	19		T6	3		T9	11
values[1]	578	1			T2	5		T12	25		T15	1
values[2]	710	1			T11	16		T13	17		T27	16
values[3]	961	1			T7	11		T148	7		T141	10
values[4]	610	1			T14	4		T148	3		T149	1
values[5]	573	1			T11	2		T24	1		T31	1
values[6]	2944	1			T1	5		T12	8		T13	7
values[7]	567	1			T7	17		T27	1		T32	17
values[8]	867	1			T5	23		T31	29		T132	6
values[9]	101	1			T186	13		T307	1		T301	1
minimum	17101	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	2		T9	11		T31	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T2	2		T148	15		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T2	1		T15	1		T245	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	2		T142	2		T307	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T31	11		T137	8		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	8		T13	10		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T229	3		T224	15		T253	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	6		T148	7		T141	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T14	3		T204	1		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T148	3		T149	1		T156	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	1		T24	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T31	1		T37	3		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1508	1			T1	3		T12	1		T28	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	7		T28	9		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	9		T32	4		T141	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T27	1		T223	7		T150	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	12		T132	1		T141	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T31	12		T132	1		T196	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T186	10		T220	12		T302	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T307	1		T301	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16867	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T323	1		T163	1		T279	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T6	1		T31	11		T297	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	17		T186	11		T280	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T2	4		T260	15		T273	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	23		T242	1		T80	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T31	10		T137	8		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	8		T13	7		T27	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T229	11		T224	12		T253	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	5		T143	14		T292	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T14	1		T39	8		T253	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T144	8		T247	10		T280	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T11	1		T265	2		T294	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T132	8		T134	8		T144	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T1	2		T12	7		T29	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T16	2		T150	21		T41	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	8		T32	13		T134	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T223	6		T150	6		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	11		T132	4		T184	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T31	17		T196	13		T224	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T186	3		T271	9		T105	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T165	6		T215	4		T317	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T1	1		T15	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T279	8		T322	2		T259	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T239	1		T231	7		T324	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T225	1		T224	3		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T255	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	2		T9	11		T28	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	1		T225	1		T161	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T15	1		T245	3		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T2	1		T12	1		T148	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T2	1		T31	11		T137	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	8		T12	1		T13	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T37	2		T243	8		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T7	6		T148	7		T141	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T204	1		T39	16		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T148	3		T149	1		T156	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T14	3		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T31	1		T37	3		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T12	1		T38	11		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T13	7		T16	4		T150	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T1	3		T7	9		T28	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	1		T28	9		T223	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T5	12		T29	2		T30	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T31	12		T132	1		T150	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T239	2		T231	5		T324	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T224	2		T309	11		T165	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T6	1		T31	11		T133	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T2	9		T279	8		T280	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T273	2		T162	10		T285	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T2	8		T12	13		T186	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T2	4		T31	10		T137	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	8		T12	10		T13	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T272	5		T248	12		T163	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	5		T143	14		T144	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T39	8		T229	11		T224	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T144	8		T247	10		T146	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T11	1		T14	1		T265	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T132	8		T134	8		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	7		T38	9		T136	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T16	2		T150	21		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	2		T7	8		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T223	6		T40	2		T248	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1011	1			T5	11		T29	14		T160	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T31	17		T150	6		T196	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T6	2		T9	1		T31	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T2	19		T148	1		T225	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	5		T15	1		T245	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	25		T142	2		T307	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T31	11		T137	9		T15	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	9		T13	8		T27	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T229	12		T224	13		T253	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	6		T148	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	3		T204	1		T39	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T148	1		T149	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T11	2		T24	1		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	1		T37	2		T132	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T1	3		T12	8		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	1		T28	1		T16	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	9		T32	14		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	1		T223	7		T150	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	12		T132	5		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T31	18		T132	1		T196	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T186	4		T220	1		T302	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T307	1		T301	1		T165	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16950	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T323	1		T163	1		T279	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T6	1		T9	10		T31	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T148	14		T161	17		T186	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T245	2		T273	4		T285	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T242	8		T248	4		T164	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T31	10		T137	7		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	7		T13	9		T144	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T229	2		T224	14		T253	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T7	5		T148	6		T141	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T14	1		T39	11		T253	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T148	2		T156	13		T144	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T294	17		T319	5		T22	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T37	1		T134	9		T144	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1173	1			T1	2		T28	8		T30	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	6		T28	8		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	8		T32	3		T141	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T223	6		T150	6		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	11		T141	9		T262	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T31	11		T245	11		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T186	9		T220	11		T271	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T215	3		T321	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T28	13		T133	8		T161	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T322	4		T255	11		T109	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T239	3		T231	6		T324	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T225	1		T224	3		T301	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T255	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T6	2		T9	1		T28	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T2	10		T225	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	1		T245	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T2	9		T12	14		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	5		T31	11		T137	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	9		T12	11		T13	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T37	2		T243	1		T136	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	6		T148	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T204	1		T39	13		T226	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T148	1		T149	1		T156	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	2		T14	3		T24	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T31	1		T37	2		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	8		T38	14		T136	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	1		T16	4		T150	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	3		T7	9		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	1		T28	1		T223	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T5	12		T29	16		T30	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T31	18		T132	1		T150	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T231	6		T324	2		T325	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T224	2		T309	12		T326	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T255	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T6	1		T9	10		T28	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T161	17		T249	10		T280	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T245	2		T273	4		T285	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T148	14		T186	5		T246	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T31	10		T137	7		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	7		T13	9		T221	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T243	7		T252	6		T272	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	5		T148	6		T141	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T39	11		T229	2		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T148	2		T156	13		T144	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T14	1		T294	17		T191	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T37	1		T134	9		T144	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T38	6		T254	8		T249	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	6		T16	2		T150	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	2		T7	8		T28	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T28	8		T223	6		T40	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T5	11		T30	15		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T31	11		T150	6		T39	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1