Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25532

1

T1

20

T2

24

T3

13

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22108

1

T1

20

T2

15

T3

13

auto[ADC_CTRL_FILTER_COND_OUT]

3424

1

T2

9

T7

28

T11

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19805

1

T1

15

T2

9

T3

13

auto[1]

5727

1

T1

5

T2

15

T6

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21753

1

T1

17

T2

3

T3

13

auto[1]

3779

1

T1

3

T2

21

T5

11

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	39	1			T267	14		T327	9		T88	16
values[0]	51	1			T132	5		T150	26		T188	13
values[1]	521	1			T11	2		T27	1		T15	4
values[2]	680	1			T13	17		T14	4		T37	2
values[3]	874	1			T2	9		T5	23		T11	16
values[4]	626	1			T9	11		T12	14		T31	44
values[5]	567	1			T2	5		T6	3		T7	11
values[6]	715	1			T2	10		T12	8		T27	16
values[7]	522	1			T13	7		T24	1		T28	14
values[8]	2872	1			T7	17		T12	11		T29	16
values[9]	1154	1			T1	5		T28	18		T148	15
minimum	16911	1			T1	15		T3	13		T4	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	730	1			T11	2		T27	1		T15	4
values[1]	590	1			T13	17		T14	4		T37	2
values[2]	886	1			T2	9		T5	23		T9	11
values[3]	689	1			T2	5		T31	73		T204	1
values[4]	613	1			T2	10		T6	3		T7	11
values[5]	631	1			T13	7		T24	1		T27	16
values[6]	2757	1			T28	14		T29	16		T30	17
values[7]	710	1			T7	17		T12	11		T132	9
values[8]	799	1			T1	5		T28	18		T148	15
values[9]	215	1			T37	3		T222	1		T143	1
minimum	16912	1			T1	15		T3	13		T4	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

3933

1

T1

2

T5

11

T6

1

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	1		T27	1		T148	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	3		T142	1		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T13	10		T37	2		T39	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	3		T196	1		T221	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	12		T9	11		T137	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T2	1		T11	8		T32	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T2	1		T134	11		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T31	35		T204	1		T141	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T2	1		T6	2		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	6		T12	1		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T13	7		T144	5		T307	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T24	1		T27	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1518	1			T28	14		T29	2		T30	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	1		T142	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T132	1		T252	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	9		T141	10		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T1	3		T28	9		T134	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	9		T148	15		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T231	7		T268	1		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T37	3		T222	1		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T328	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	1		T16	2		T223	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	1		T132	4		T274	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	7		T39	9		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T14	1		T196	13		T221	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	11		T137	8		T144	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T2	8		T11	8		T32	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T2	4		T134	11		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T31	38		T144	19		T273	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T2	9		T6	1		T12	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	5		T12	7		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T144	8		T145	2		T227	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T27	15		T18	2		T237	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1007	1			T29	14		T160	4		T189	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T150	6		T17	3		T136	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T12	10		T132	8		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	8		T253	17		T163	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	2		T134	8		T146	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T224	14		T253	7		T272	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T231	5		T268	9		T80	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T35	2		T241	10		T267	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T267	1		T327	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T88	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T150	11		T188	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T132	1		T329	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T27	1		T148	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T15	3		T222	1		T274	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	10		T37	2		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	3		T142	1		T196	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T5	12		T142	1		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T2	1		T11	8		T32	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	11		T12	1		T137	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T31	23		T204	1		T141	25
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T2	1		T6	2		T134	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	6		T31	12		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	1		T307	1		T34	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T27	1		T143	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T13	7		T28	14		T38	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T24	1		T149	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1563	1			T12	1		T29	2		T30	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T7	9		T149	1		T141	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T1	3		T28	9		T134	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T28	9		T148	15		T37	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16793	1			T1	14		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T267	13		T327	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T88	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T150	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T132	4		T329	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	1		T41	3		T224	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T15	1		T274	9		T45	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	7		T16	2		T223	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T196	13		T221	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	11		T39	1		T144	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	8		T11	8		T32	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	13		T137	8		T232	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T31	21		T257	9		T273	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T2	4		T6	1		T134	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	5		T31	17		T150	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T2	9		T34	12		T145	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	7		T27	15		T143	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T38	9		T144	8		T241	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T150	6		T17	3		T136	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T12	10		T29	14		T160	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	8		T163	4		T313	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	2		T134	8		T231	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T224	14		T253	24		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T1	1		T15	1		T16	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	2		T27	1		T148	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	3		T142	1		T132	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	8		T37	2		T39	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	3		T196	14		T221	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	12		T9	1		T137	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T2	9		T11	9		T32	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T2	5		T134	12		T225	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T31	42		T204	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T2	10		T6	2		T12	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	6		T12	8		T15	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	1		T144	9		T307	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T24	1		T27	16		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T28	1		T29	16		T30	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	1		T142	1		T150	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	11		T132	9		T252	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	9		T141	1		T40	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	3		T28	1		T134	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T28	1		T148	1		T225	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T231	6		T268	10		T312	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T37	2		T222	1		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T328	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T148	2		T16	2		T223	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	1		T274	4		T45	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T13	9		T39	12		T245	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T14	1		T221	16		T246	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	11		T9	10		T137	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	7		T32	3		T133	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T134	10		T40	6		T232	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	31		T141	14		T243	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T6	1		T34	10		T145	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	5		T150	6		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T13	6		T144	4		T145	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T156	13		T18	1		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1185	1			T28	13		T30	15		T151	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T150	8		T17	3		T187	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T252	6		T221	14		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	8		T141	9		T243	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	2		T28	8		T134	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	8		T148	14		T245	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T231	6		T167	13		T310	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T37	1		T241	8		T255	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T267	14		T327	9		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T88	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T150	16		T188	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T132	5		T329	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	2		T27	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T15	3		T222	1		T274	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T13	8		T37	2		T16	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	3		T142	1		T196	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	12		T142	1		T39	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T2	9		T11	9		T32	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	1		T12	14		T137	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T31	24		T204	1		T141	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T2	5		T6	2		T134	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	6		T31	18		T15	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T2	10		T307	1		T34	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	8		T27	16		T143	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	1		T28	1		T38	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	1		T149	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T12	11		T29	16		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	9		T149	1		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T1	3		T28	1		T134	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T28	1		T148	1		T37	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T1	15		T3	13		T4	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T88	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T150	10		T188	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T148	2		T41	2		T224	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T15	1		T274	4		T45	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	9		T16	2		T223	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T14	1		T221	16		T246	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	11		T39	1		T161	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	7		T32	3		T133	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	10		T137	7		T232	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T31	20		T141	23		T243	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T6	1		T134	10		T40	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	5		T31	11		T150	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	10		T145	15		T84	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T143	11		T18	1		T191	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T13	6		T28	13		T38	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T150	8		T17	3		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1227	1			T30	15		T151	7		T148	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	8		T141	9		T243	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T1	2		T28	8		T134	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T28	8		T148	14		T37	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21599

1

T1

18

T2

24

T3

13

auto[1]

auto[0]

3933

1

T1

2

T5

11

T6

1