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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.92


Total test records in report: 917
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T797 /workspace/coverage/default/32.adc_ctrl_filters_polled.2787765905 Apr 30 03:03:49 PM PDT 24 Apr 30 03:08:46 PM PDT 24 496071194804 ps
T798 /workspace/coverage/default/41.adc_ctrl_clock_gating.1705755108 Apr 30 03:04:50 PM PDT 24 Apr 30 03:11:41 PM PDT 24 324251220190 ps
T55 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4080549408 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:14 PM PDT 24 497092278 ps
T112 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4272694188 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:13 PM PDT 24 474694355 ps
T91 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.763700169 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 576070765 ps
T56 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2584839576 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:16 PM PDT 24 620558219 ps
T62 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3945492341 Apr 30 03:02:18 PM PDT 24 Apr 30 03:02:22 PM PDT 24 497662757 ps
T799 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2209250595 Apr 30 03:02:29 PM PDT 24 Apr 30 03:02:31 PM PDT 24 427784041 ps
T51 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2714844087 Apr 30 03:02:26 PM PDT 24 Apr 30 03:02:39 PM PDT 24 4710584491 ps
T127 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2073391365 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 338426528 ps
T71 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3825391665 Apr 30 03:02:17 PM PDT 24 Apr 30 03:02:19 PM PDT 24 498102077 ps
T72 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.577134169 Apr 30 03:02:05 PM PDT 24 Apr 30 03:02:08 PM PDT 24 675840083 ps
T52 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1195802818 Apr 30 03:02:06 PM PDT 24 Apr 30 03:02:29 PM PDT 24 8498257657 ps
T800 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3770659580 Apr 30 03:02:26 PM PDT 24 Apr 30 03:02:28 PM PDT 24 415504311 ps
T801 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.883443855 Apr 30 03:02:42 PM PDT 24 Apr 30 03:02:44 PM PDT 24 523347329 ps
T802 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.242559582 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:17 PM PDT 24 422009709 ps
T70 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3217739282 Apr 30 03:02:09 PM PDT 24 Apr 30 03:02:11 PM PDT 24 646213863 ps
T48 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2373102251 Apr 30 03:02:30 PM PDT 24 Apr 30 03:02:41 PM PDT 24 2609629787 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1648589706 Apr 30 03:02:07 PM PDT 24 Apr 30 03:02:14 PM PDT 24 734870240 ps
T68 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.315977645 Apr 30 03:02:18 PM PDT 24 Apr 30 03:02:20 PM PDT 24 602774978 ps
T803 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2672675327 Apr 30 03:02:32 PM PDT 24 Apr 30 03:02:33 PM PDT 24 517883872 ps
T63 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2658688448 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:19 PM PDT 24 524322517 ps
T49 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.671486767 Apr 30 03:02:13 PM PDT 24 Apr 30 03:02:21 PM PDT 24 2570680722 ps
T53 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1945807096 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:25 PM PDT 24 8374349032 ps
T50 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3712498542 Apr 30 03:02:32 PM PDT 24 Apr 30 03:02:41 PM PDT 24 4239813280 ps
T804 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2388884198 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:19 PM PDT 24 464456774 ps
T67 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3888253926 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:15 PM PDT 24 738986145 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.957134025 Apr 30 03:02:01 PM PDT 24 Apr 30 03:02:06 PM PDT 24 1393779985 ps
T805 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.391093534 Apr 30 03:02:25 PM PDT 24 Apr 30 03:02:27 PM PDT 24 619370762 ps
T806 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1317466412 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:18 PM PDT 24 315469042 ps
T128 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.982210807 Apr 30 03:02:09 PM PDT 24 Apr 30 03:02:16 PM PDT 24 2427028379 ps
T807 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2675537563 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:21 PM PDT 24 4658394332 ps
T129 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4007873582 Apr 30 03:02:37 PM PDT 24 Apr 30 03:02:48 PM PDT 24 2458367008 ps
T808 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3482099998 Apr 30 03:02:23 PM PDT 24 Apr 30 03:02:24 PM PDT 24 452860463 ps
T69 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2105027856 Apr 30 03:02:25 PM PDT 24 Apr 30 03:02:33 PM PDT 24 8053268693 ps
T60 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3170097394 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:15 PM PDT 24 381336175 ps
T809 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4011906782 Apr 30 03:02:23 PM PDT 24 Apr 30 03:02:25 PM PDT 24 416187039 ps
T61 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1945143225 Apr 30 03:02:26 PM PDT 24 Apr 30 03:02:30 PM PDT 24 555861688 ps
T810 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3321100096 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 393078701 ps
T130 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.616817508 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 540378070 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2724785281 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:18 PM PDT 24 676836927 ps
T116 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1537162949 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:19 PM PDT 24 384291129 ps
T811 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1856287588 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:12 PM PDT 24 501204198 ps
T812 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3648122025 Apr 30 03:01:59 PM PDT 24 Apr 30 03:02:07 PM PDT 24 1313577216 ps
T813 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2881630065 Apr 30 03:02:17 PM PDT 24 Apr 30 03:02:20 PM PDT 24 428541322 ps
T814 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3966409489 Apr 30 03:02:07 PM PDT 24 Apr 30 03:02:10 PM PDT 24 436581248 ps
T356 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.397461962 Apr 30 03:02:17 PM PDT 24 Apr 30 03:02:29 PM PDT 24 4135656505 ps
T815 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3313910864 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:12 PM PDT 24 586178590 ps
T816 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1709029363 Apr 30 03:02:34 PM PDT 24 Apr 30 03:02:38 PM PDT 24 961935783 ps
T817 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2336781884 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:15 PM PDT 24 324350384 ps
T818 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1521578692 Apr 30 03:02:32 PM PDT 24 Apr 30 03:02:34 PM PDT 24 403490662 ps
T819 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2833893791 Apr 30 03:02:07 PM PDT 24 Apr 30 03:02:10 PM PDT 24 471796818 ps
T820 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2629403363 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:12 PM PDT 24 432838830 ps
T131 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1503816011 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:23 PM PDT 24 5233377522 ps
T821 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2192588893 Apr 30 03:02:21 PM PDT 24 Apr 30 03:02:23 PM PDT 24 496724017 ps
T822 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2003871217 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:20 PM PDT 24 4418272707 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1294131017 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:12 PM PDT 24 313937600 ps
T824 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2347840171 Apr 30 03:02:03 PM PDT 24 Apr 30 03:02:06 PM PDT 24 421050590 ps
T825 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3232642186 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:17 PM PDT 24 484646505 ps
T826 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1898537438 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:13 PM PDT 24 451578543 ps
T827 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3095132666 Apr 30 03:02:19 PM PDT 24 Apr 30 03:02:21 PM PDT 24 457031821 ps
T828 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.524175532 Apr 30 03:02:03 PM PDT 24 Apr 30 03:02:06 PM PDT 24 380347384 ps
T829 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1172385275 Apr 30 03:02:14 PM PDT 24 Apr 30 03:02:22 PM PDT 24 847244128 ps
T830 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1593730227 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 344235963 ps
T831 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1766167174 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:17 PM PDT 24 394253652 ps
T357 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2230115567 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:26 PM PDT 24 9510204419 ps
T117 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.334413958 Apr 30 03:02:08 PM PDT 24 Apr 30 03:02:46 PM PDT 24 9933340412 ps
T832 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3112085534 Apr 30 03:02:14 PM PDT 24 Apr 30 03:02:17 PM PDT 24 441822967 ps
T833 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2791133650 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:12 PM PDT 24 395288784 ps
T834 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2579740355 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:18 PM PDT 24 5308555047 ps
T118 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4054334909 Apr 30 03:02:02 PM PDT 24 Apr 30 03:02:06 PM PDT 24 1206594001 ps
T835 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2954348046 Apr 30 03:02:42 PM PDT 24 Apr 30 03:02:44 PM PDT 24 520147852 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3388892833 Apr 30 03:02:14 PM PDT 24 Apr 30 03:02:19 PM PDT 24 414083596 ps
T837 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2593748331 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:18 PM PDT 24 478297300 ps
T838 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1430432641 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:18 PM PDT 24 374216163 ps
T839 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2827467890 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:15 PM PDT 24 521456762 ps
T840 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3932586954 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:20 PM PDT 24 415485820 ps
T119 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.897879215 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:17 PM PDT 24 378039485 ps
T120 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2450125457 Apr 30 03:02:29 PM PDT 24 Apr 30 03:02:30 PM PDT 24 566239928 ps
T841 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4204195268 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:25 PM PDT 24 4356026982 ps
T842 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.40001222 Apr 30 03:02:02 PM PDT 24 Apr 30 03:02:05 PM PDT 24 407641681 ps
T843 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1614393427 Apr 30 03:02:17 PM PDT 24 Apr 30 03:02:21 PM PDT 24 4716916242 ps
T121 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.460333515 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:17 PM PDT 24 762211807 ps
T844 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2521932547 Apr 30 03:02:07 PM PDT 24 Apr 30 03:02:11 PM PDT 24 353605829 ps
T73 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2419773445 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:38 PM PDT 24 8081582928 ps
T845 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.789989130 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:28 PM PDT 24 4644357327 ps
T846 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.754865162 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:15 PM PDT 24 404288322 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1368489218 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:21 PM PDT 24 4039673176 ps
T848 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.7489541 Apr 30 03:02:37 PM PDT 24 Apr 30 03:02:38 PM PDT 24 585866332 ps
T849 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4226344911 Apr 30 03:02:29 PM PDT 24 Apr 30 03:02:35 PM PDT 24 396747734 ps
T850 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1831460532 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:19 PM PDT 24 461370452 ps
T124 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.416500245 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:13 PM PDT 24 736903457 ps
T125 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2369184802 Apr 30 03:02:30 PM PDT 24 Apr 30 03:02:32 PM PDT 24 572645104 ps
T851 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3373341831 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 833123614 ps
T852 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1278573340 Apr 30 03:02:33 PM PDT 24 Apr 30 03:02:35 PM PDT 24 418912614 ps
T358 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3651834436 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:17 PM PDT 24 4573796416 ps
T853 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.4164109524 Apr 30 03:02:38 PM PDT 24 Apr 30 03:02:46 PM PDT 24 4228915355 ps
T854 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1142883464 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 570448797 ps
T122 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2786260115 Apr 30 03:02:09 PM PDT 24 Apr 30 03:02:12 PM PDT 24 440756435 ps
T855 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3862147853 Apr 30 03:02:34 PM PDT 24 Apr 30 03:02:35 PM PDT 24 565966872 ps
T856 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2680164702 Apr 30 03:02:38 PM PDT 24 Apr 30 03:02:40 PM PDT 24 390219976 ps
T123 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2395999053 Apr 30 03:02:08 PM PDT 24 Apr 30 03:02:10 PM PDT 24 400884354 ps
T359 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3310668690 Apr 30 03:02:31 PM PDT 24 Apr 30 03:02:43 PM PDT 24 4418493398 ps
T857 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2499534312 Apr 30 03:02:34 PM PDT 24 Apr 30 03:02:36 PM PDT 24 403259050 ps
T858 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2031397614 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:17 PM PDT 24 415137245 ps
T859 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3593734378 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:15 PM PDT 24 2576962576 ps
T860 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3132853706 Apr 30 03:02:18 PM PDT 24 Apr 30 03:02:20 PM PDT 24 640466703 ps
T861 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.612258802 Apr 30 03:02:30 PM PDT 24 Apr 30 03:02:31 PM PDT 24 511538414 ps
T862 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1173446941 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:17 PM PDT 24 491771947 ps
T126 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.13201854 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 360448198 ps
T863 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.682874096 Apr 30 03:02:12 PM PDT 24 Apr 30 03:03:08 PM PDT 24 23589522915 ps
T864 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1492560917 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:22 PM PDT 24 8830554068 ps
T865 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1142453682 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:19 PM PDT 24 549129803 ps
T866 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2766698414 Apr 30 03:02:22 PM PDT 24 Apr 30 03:02:24 PM PDT 24 336035972 ps
T867 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.564860639 Apr 30 03:02:20 PM PDT 24 Apr 30 03:02:22 PM PDT 24 437321505 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.370841504 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 400779587 ps
T869 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3356050753 Apr 30 03:02:27 PM PDT 24 Apr 30 03:02:29 PM PDT 24 356384628 ps
T870 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.902728294 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 513894931 ps
T871 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2721819335 Apr 30 03:02:08 PM PDT 24 Apr 30 03:02:20 PM PDT 24 492093453 ps
T872 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4277511788 Apr 30 03:02:07 PM PDT 24 Apr 30 03:02:10 PM PDT 24 397453866 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2099739357 Apr 30 03:02:05 PM PDT 24 Apr 30 03:04:03 PM PDT 24 31709543267 ps
T874 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.446377622 Apr 30 03:02:34 PM PDT 24 Apr 30 03:02:35 PM PDT 24 407296725 ps
T875 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.908246090 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:19 PM PDT 24 4642728935 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3458057743 Apr 30 03:02:08 PM PDT 24 Apr 30 03:02:27 PM PDT 24 4451038598 ps
T877 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1393957242 Apr 30 03:02:09 PM PDT 24 Apr 30 03:02:13 PM PDT 24 4214748407 ps
T878 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4134478878 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:20 PM PDT 24 2152751016 ps
T879 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1520447105 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:20 PM PDT 24 4415224486 ps
T880 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2140871824 Apr 30 03:02:17 PM PDT 24 Apr 30 03:02:19 PM PDT 24 440617492 ps
T881 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.142876105 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:17 PM PDT 24 9325321094 ps
T882 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1363669232 Apr 30 03:02:14 PM PDT 24 Apr 30 03:02:17 PM PDT 24 511419597 ps
T883 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2529995912 Apr 30 03:02:38 PM PDT 24 Apr 30 03:02:40 PM PDT 24 485785256 ps
T884 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2942714287 Apr 30 03:02:37 PM PDT 24 Apr 30 03:02:49 PM PDT 24 4380929807 ps
T885 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3649446255 Apr 30 03:02:08 PM PDT 24 Apr 30 03:02:12 PM PDT 24 1020496347 ps
T74 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.175931188 Apr 30 03:02:06 PM PDT 24 Apr 30 03:02:14 PM PDT 24 8740241021 ps
T886 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3734009223 Apr 30 03:02:29 PM PDT 24 Apr 30 03:02:30 PM PDT 24 887895851 ps
T887 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2018204557 Apr 30 03:02:09 PM PDT 24 Apr 30 03:02:13 PM PDT 24 8559921483 ps
T888 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.618408619 Apr 30 03:02:21 PM PDT 24 Apr 30 03:02:23 PM PDT 24 689968801 ps
T889 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3742617566 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:18 PM PDT 24 342705112 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2678618389 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 380552197 ps
T891 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1081096826 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:19 PM PDT 24 481827733 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4059289410 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:15 PM PDT 24 514081845 ps
T893 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3166641585 Apr 30 03:02:31 PM PDT 24 Apr 30 03:02:32 PM PDT 24 331059075 ps
T894 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.470029632 Apr 30 03:02:17 PM PDT 24 Apr 30 03:02:19 PM PDT 24 523329441 ps
T895 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3645202319 Apr 30 03:02:13 PM PDT 24 Apr 30 03:02:17 PM PDT 24 492488564 ps
T896 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2295101636 Apr 30 03:02:40 PM PDT 24 Apr 30 03:02:42 PM PDT 24 499935021 ps
T897 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1775322477 Apr 30 03:02:18 PM PDT 24 Apr 30 03:02:20 PM PDT 24 422380086 ps
T898 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2205841910 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:21 PM PDT 24 2205041947 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2991265443 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:17 PM PDT 24 840448860 ps
T900 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1586460054 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:17 PM PDT 24 389866196 ps
T901 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.138609894 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:21 PM PDT 24 4260953167 ps
T902 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2028396469 Apr 30 03:02:32 PM PDT 24 Apr 30 03:02:55 PM PDT 24 8088891312 ps
T903 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4104096958 Apr 30 03:02:12 PM PDT 24 Apr 30 03:04:54 PM PDT 24 46123776966 ps
T904 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1575184824 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:14 PM PDT 24 411081705 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2667219533 Apr 30 03:02:10 PM PDT 24 Apr 30 03:02:14 PM PDT 24 595605668 ps
T906 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4138211480 Apr 30 03:02:09 PM PDT 24 Apr 30 03:02:12 PM PDT 24 617860320 ps
T907 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.380344783 Apr 30 03:02:11 PM PDT 24 Apr 30 03:02:13 PM PDT 24 525521702 ps
T908 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2567061787 Apr 30 03:02:27 PM PDT 24 Apr 30 03:02:29 PM PDT 24 523711521 ps
T909 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2816046798 Apr 30 03:02:08 PM PDT 24 Apr 30 03:02:17 PM PDT 24 925487201 ps
T910 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1554652168 Apr 30 03:02:13 PM PDT 24 Apr 30 03:02:19 PM PDT 24 4099730518 ps
T75 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1081272719 Apr 30 03:02:23 PM PDT 24 Apr 30 03:02:45 PM PDT 24 8813638973 ps
T911 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.395830061 Apr 30 03:02:14 PM PDT 24 Apr 30 03:02:17 PM PDT 24 480620337 ps
T912 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4146716679 Apr 30 03:02:35 PM PDT 24 Apr 30 03:02:36 PM PDT 24 328392871 ps
T913 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2427883794 Apr 30 03:02:23 PM PDT 24 Apr 30 03:02:24 PM PDT 24 338494840 ps
T914 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.916739308 Apr 30 03:02:16 PM PDT 24 Apr 30 03:02:20 PM PDT 24 3421032044 ps
T915 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4119240204 Apr 30 03:02:15 PM PDT 24 Apr 30 03:02:18 PM PDT 24 360020896 ps
T916 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4144817591 Apr 30 03:02:09 PM PDT 24 Apr 30 03:02:11 PM PDT 24 455682143 ps
T917 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2355385169 Apr 30 03:02:12 PM PDT 24 Apr 30 03:02:15 PM PDT 24 555273993 ps

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2024410197
Short name T7
Test name
Test status
Simulation time 475502381282 ps
CPU time 752.88 seconds
Started Apr 30 03:03:04 PM PDT 24
Finished Apr 30 03:15:38 PM PDT 24
Peak memory 202660 kb
Host smart-addef5e8-3870-4d8d-9b25-d3373272e269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024410197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2024410197
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2619605745
Short name T15
Test name
Test status
Simulation time 109212707535 ps
CPU time 298.9 seconds
Started Apr 30 03:03:42 PM PDT 24
Finished Apr 30 03:08:42 PM PDT 24
Peak memory 211004 kb
Host smart-0d582d18-bd38-4450-8e4d-e78d3bf0fa35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619605745 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2619605745
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3798018475
Short name T28
Test name
Test status
Simulation time 544223048697 ps
CPU time 348.83 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:08:35 PM PDT 24
Peak memory 202324 kb
Host smart-6697a69b-06b9-4c7c-8966-be8331f89097
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798018475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3798018475
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2132864421
Short name T31
Test name
Test status
Simulation time 695825079347 ps
CPU time 876.45 seconds
Started Apr 30 03:03:44 PM PDT 24
Finished Apr 30 03:18:21 PM PDT 24
Peak memory 202248 kb
Host smart-b498c2cd-a2ab-4392-8d33-2b17fa7add74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132864421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2132864421
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2094794027
Short name T143
Test name
Test status
Simulation time 697973101867 ps
CPU time 619.67 seconds
Started Apr 30 03:06:01 PM PDT 24
Finished Apr 30 03:16:21 PM PDT 24
Peak memory 202748 kb
Host smart-f7d7d8c0-37f7-4ec4-ab17-0c8deb11c838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094794027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2094794027
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.406686847
Short name T144
Test name
Test status
Simulation time 545838206577 ps
CPU time 594.72 seconds
Started Apr 30 03:03:48 PM PDT 24
Finished Apr 30 03:13:44 PM PDT 24
Peak memory 202344 kb
Host smart-cd923209-0b7d-4619-bda1-675544df062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406686847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.406686847
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2279832656
Short name T2
Test name
Test status
Simulation time 491443081671 ps
CPU time 1136.03 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:22:28 PM PDT 24
Peak memory 202364 kb
Host smart-3263c617-3e5e-4bf6-a82b-756d6285d9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279832656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2279832656
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.409534420
Short name T150
Test name
Test status
Simulation time 548649565680 ps
CPU time 310.16 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:08:14 PM PDT 24
Peak memory 202304 kb
Host smart-9c327342-cf8e-4900-b78e-20c14e4d687e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409534420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.409534420
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1034000510
Short name T45
Test name
Test status
Simulation time 305275426540 ps
CPU time 433.41 seconds
Started Apr 30 03:05:54 PM PDT 24
Finished Apr 30 03:13:08 PM PDT 24
Peak memory 211012 kb
Host smart-6562a899-6c19-4a03-ad09-85198abd7e32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034000510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1034000510
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2301867740
Short name T221
Test name
Test status
Simulation time 503439350838 ps
CPU time 984.44 seconds
Started Apr 30 03:02:34 PM PDT 24
Finished Apr 30 03:18:59 PM PDT 24
Peak memory 202384 kb
Host smart-8b259010-4740-4d67-851f-dfddc335c4a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301867740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2301867740
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.4080549408
Short name T55
Test name
Test status
Simulation time 497092278 ps
CPU time 2.39 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:14 PM PDT 24
Peak memory 201444 kb
Host smart-3243fed8-429a-47da-bd5f-d753204adc99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080549408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.4080549408
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.39524712
Short name T241
Test name
Test status
Simulation time 498486803656 ps
CPU time 1231.25 seconds
Started Apr 30 03:04:15 PM PDT 24
Finished Apr 30 03:24:46 PM PDT 24
Peak memory 202332 kb
Host smart-f7f738fe-b29b-4698-bd27-8f2492d10839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39524712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.39524712
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.4046843596
Short name T132
Test name
Test status
Simulation time 499670291340 ps
CPU time 311.43 seconds
Started Apr 30 03:05:34 PM PDT 24
Finished Apr 30 03:10:46 PM PDT 24
Peak memory 202296 kb
Host smart-4e3ba193-e354-49d0-a1a0-264546eacd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046843596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.4046843596
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3009337891
Short name T248
Test name
Test status
Simulation time 516175258541 ps
CPU time 229.49 seconds
Started Apr 30 03:02:47 PM PDT 24
Finished Apr 30 03:06:37 PM PDT 24
Peak memory 202272 kb
Host smart-4690994f-58aa-4992-b3fc-85295ed154e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009337891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3009337891
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.456687124
Short name T39
Test name
Test status
Simulation time 238607141321 ps
CPU time 92.5 seconds
Started Apr 30 03:02:30 PM PDT 24
Finished Apr 30 03:04:03 PM PDT 24
Peak memory 210584 kb
Host smart-250840a5-e90a-4156-93fd-d20423781efe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456687124 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.456687124
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1357022084
Short name T384
Test name
Test status
Simulation time 484777166 ps
CPU time 1.16 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:03:08 PM PDT 24
Peak memory 201976 kb
Host smart-7b5748f1-1b97-4dfa-91d8-8102452ac415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357022084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1357022084
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.2987721322
Short name T266
Test name
Test status
Simulation time 508534269755 ps
CPU time 176.58 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:06:32 PM PDT 24
Peak memory 202272 kb
Host smart-275fca5f-3a7a-4383-8462-08afdfc01092
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987721322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.2987721322
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.334413958
Short name T117
Test name
Test status
Simulation time 9933340412 ps
CPU time 36.54 seconds
Started Apr 30 03:02:08 PM PDT 24
Finished Apr 30 03:02:46 PM PDT 24
Peak memory 201512 kb
Host smart-8008ba17-a164-442f-8282-ea1f09923d46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334413958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_b
ash.334413958
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1945807096
Short name T53
Test name
Test status
Simulation time 8374349032 ps
CPU time 7.65 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:25 PM PDT 24
Peak memory 201512 kb
Host smart-0143cc42-75bd-4110-a99b-32500982b3be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945807096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1945807096
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3023886567
Short name T224
Test name
Test status
Simulation time 496559350482 ps
CPU time 289.92 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:08:02 PM PDT 24
Peak memory 202248 kb
Host smart-83e2c40d-bbd5-400c-ab47-c0ecd9ec5c62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023886567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3023886567
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3032231331
Short name T186
Test name
Test status
Simulation time 328518367344 ps
CPU time 156.18 seconds
Started Apr 30 03:02:49 PM PDT 24
Finished Apr 30 03:05:26 PM PDT 24
Peak memory 202340 kb
Host smart-833d299e-3ffd-42be-a6c3-2bc1698a2435
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032231331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3032231331
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2567546428
Short name T280
Test name
Test status
Simulation time 568133564732 ps
CPU time 651.16 seconds
Started Apr 30 03:05:54 PM PDT 24
Finished Apr 30 03:16:46 PM PDT 24
Peak memory 202300 kb
Host smart-d3922434-5268-494e-a6c4-b69d8b692d41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567546428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2567546428
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.786555428
Short name T160
Test name
Test status
Simulation time 162923190967 ps
CPU time 394.83 seconds
Started Apr 30 03:03:57 PM PDT 24
Finished Apr 30 03:10:33 PM PDT 24
Peak memory 202276 kb
Host smart-8c215cfc-a4c3-4b02-ae99-152cbf1d91c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=786555428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.786555428
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.898660689
Short name T175
Test name
Test status
Simulation time 493108291488 ps
CPU time 222.76 seconds
Started Apr 30 03:02:14 PM PDT 24
Finished Apr 30 03:05:59 PM PDT 24
Peak memory 202280 kb
Host smart-b0b1b2a5-47cb-4e71-848e-297ea09464ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898660689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.898660689
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1146368557
Short name T38
Test name
Test status
Simulation time 81586199844 ps
CPU time 84.82 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:04:27 PM PDT 24
Peak memory 212480 kb
Host smart-18ec11de-13f7-4ac6-8ca3-37575c3685ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146368557 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1146368557
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1568346409
Short name T322
Test name
Test status
Simulation time 331686334776 ps
CPU time 188.52 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:06:12 PM PDT 24
Peak memory 202308 kb
Host smart-a289e1bb-bfcf-49dc-8546-6ed7d4d8b877
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568346409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1568346409
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2564769856
Short name T253
Test name
Test status
Simulation time 509930860786 ps
CPU time 281.37 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:07:55 PM PDT 24
Peak memory 202232 kb
Host smart-8eee1738-f98d-4b65-bd96-5ca0e25425fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564769856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2564769856
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2414324211
Short name T145
Test name
Test status
Simulation time 382040879966 ps
CPU time 217.11 seconds
Started Apr 30 03:04:44 PM PDT 24
Finished Apr 30 03:08:21 PM PDT 24
Peak memory 202592 kb
Host smart-82fb191f-e808-40b3-8cc2-fa08cf5c8d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414324211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2414324211
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.660680320
Short name T187
Test name
Test status
Simulation time 374654514230 ps
CPU time 66.85 seconds
Started Apr 30 03:04:30 PM PDT 24
Finished Apr 30 03:05:37 PM PDT 24
Peak memory 202268 kb
Host smart-994ab539-94db-405d-94d0-d213a0c3a19e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660680320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.660680320
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.310670200
Short name T294
Test name
Test status
Simulation time 167433528137 ps
CPU time 192.17 seconds
Started Apr 30 03:04:29 PM PDT 24
Finished Apr 30 03:07:41 PM PDT 24
Peak memory 202248 kb
Host smart-2a47c425-569e-41b1-8f16-c7deb796e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310670200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.310670200
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2421294484
Short name T59
Test name
Test status
Simulation time 7590661883 ps
CPU time 10.24 seconds
Started Apr 30 03:02:40 PM PDT 24
Finished Apr 30 03:02:51 PM PDT 24
Peak memory 218800 kb
Host smart-f0d5ba49-85f9-4cb7-913f-151c97b515bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421294484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2421294484
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3996059228
Short name T193
Test name
Test status
Simulation time 542325065217 ps
CPU time 119.77 seconds
Started Apr 30 03:03:04 PM PDT 24
Finished Apr 30 03:05:10 PM PDT 24
Peak memory 202372 kb
Host smart-d8ee1ed7-7489-4eb8-b40f-b2cb3002a948
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996059228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3996059228
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.4898549
Short name T147
Test name
Test status
Simulation time 625940331001 ps
CPU time 670.41 seconds
Started Apr 30 03:02:33 PM PDT 24
Finished Apr 30 03:13:44 PM PDT 24
Peak memory 202680 kb
Host smart-da3b1188-c090-47ad-9183-a6e601c2d9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4898549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.4898549
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3662341571
Short name T301
Test name
Test status
Simulation time 497337609597 ps
CPU time 1184.64 seconds
Started Apr 30 03:04:02 PM PDT 24
Finished Apr 30 03:23:47 PM PDT 24
Peak memory 202316 kb
Host smart-b71d6234-2353-4b9f-9f11-f69820b11b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662341571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3662341571
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3227186491
Short name T288
Test name
Test status
Simulation time 370730231172 ps
CPU time 123.03 seconds
Started Apr 30 03:05:13 PM PDT 24
Finished Apr 30 03:07:17 PM PDT 24
Peak memory 202224 kb
Host smart-b3889f06-a543-45a0-a633-d2efccd1e7ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227186491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3227186491
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2073391365
Short name T127
Test name
Test status
Simulation time 338426528 ps
CPU time 1.09 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201140 kb
Host smart-50375f4d-6bb9-430d-877d-0a63b3426108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073391365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2073391365
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1300549076
Short name T231
Test name
Test status
Simulation time 484985913182 ps
CPU time 457.28 seconds
Started Apr 30 03:02:39 PM PDT 24
Finished Apr 30 03:10:17 PM PDT 24
Peak memory 202308 kb
Host smart-2394823c-182f-4c8d-98d4-86d8d9fb6e83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300549076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1300549076
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1184386063
Short name T100
Test name
Test status
Simulation time 320034439953 ps
CPU time 773.47 seconds
Started Apr 30 03:03:59 PM PDT 24
Finished Apr 30 03:16:54 PM PDT 24
Peak memory 202368 kb
Host smart-7acf8062-6f0f-43f5-a4b8-7689875e4231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184386063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1184386063
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1445628804
Short name T82
Test name
Test status
Simulation time 94347772811 ps
CPU time 249.93 seconds
Started Apr 30 03:05:48 PM PDT 24
Finished Apr 30 03:09:58 PM PDT 24
Peak memory 212004 kb
Host smart-52227f04-0778-40ec-baca-cf8fe05de564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445628804 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1445628804
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1625118264
Short name T330
Test name
Test status
Simulation time 523256018233 ps
CPU time 1178.36 seconds
Started Apr 30 03:03:29 PM PDT 24
Finished Apr 30 03:23:09 PM PDT 24
Peak memory 202356 kb
Host smart-9ece82e3-e4f6-423f-8296-8a0e8fa53f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625118264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1625118264
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1274589566
Short name T238
Test name
Test status
Simulation time 362620670456 ps
CPU time 148.44 seconds
Started Apr 30 03:04:22 PM PDT 24
Finished Apr 30 03:06:51 PM PDT 24
Peak memory 202276 kb
Host smart-50f3f826-9204-44a4-a747-1b7072f20073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274589566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1274589566
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4065136577
Short name T297
Test name
Test status
Simulation time 302047042248 ps
CPU time 340.61 seconds
Started Apr 30 03:02:44 PM PDT 24
Finished Apr 30 03:08:25 PM PDT 24
Peak memory 202740 kb
Host smart-6a45f8bc-0b6f-47de-9644-b9c09cd430a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065136577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4065136577
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2336781884
Short name T817
Test name
Test status
Simulation time 324350384 ps
CPU time 3.23 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 217588 kb
Host smart-8f756370-b693-494e-8027-f3f3cb17fda8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336781884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2336781884
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.781607505
Short name T342
Test name
Test status
Simulation time 534494842240 ps
CPU time 676.49 seconds
Started Apr 30 03:03:19 PM PDT 24
Finished Apr 30 03:14:36 PM PDT 24
Peak memory 202284 kb
Host smart-11713551-5d19-4de4-bf70-87acbcbc243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781607505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.781607505
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1556872074
Short name T285
Test name
Test status
Simulation time 90929110544 ps
CPU time 163.5 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:05:46 PM PDT 24
Peak memory 210576 kb
Host smart-b3ec74a5-ffe1-4dce-95f2-2d5b1bd60042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556872074 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1556872074
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2347097721
Short name T34
Test name
Test status
Simulation time 211695161040 ps
CPU time 123.17 seconds
Started Apr 30 03:03:16 PM PDT 24
Finished Apr 30 03:05:20 PM PDT 24
Peak memory 202364 kb
Host smart-9c21c0a6-2e8f-4d01-a161-d1175f9b5daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347097721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2347097721
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1956513021
Short name T163
Test name
Test status
Simulation time 494056036310 ps
CPU time 221.52 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:07:05 PM PDT 24
Peak memory 202236 kb
Host smart-59f9cff1-5a51-42d6-a3e4-a66296ad7121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956513021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1956513021
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3063284865
Short name T255
Test name
Test status
Simulation time 553169613693 ps
CPU time 1253.01 seconds
Started Apr 30 03:03:29 PM PDT 24
Finished Apr 30 03:24:23 PM PDT 24
Peak memory 202296 kb
Host smart-8aecab1f-c899-4434-a2a9-b5928e70696d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063284865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3063284865
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.380404315
Short name T88
Test name
Test status
Simulation time 283118448906 ps
CPU time 114.7 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:05:07 PM PDT 24
Peak memory 210744 kb
Host smart-2f6ae72d-6327-42eb-b1f6-df3a4cc6cd18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380404315 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.380404315
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.151415546
Short name T165
Test name
Test status
Simulation time 478599251873 ps
CPU time 298.51 seconds
Started Apr 30 03:03:40 PM PDT 24
Finished Apr 30 03:08:39 PM PDT 24
Peak memory 202408 kb
Host smart-1398d0b8-ac74-49d3-a3e7-68c290294a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151415546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.151415546
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1307861665
Short name T171
Test name
Test status
Simulation time 592779543546 ps
CPU time 778.44 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:15:37 PM PDT 24
Peak memory 202248 kb
Host smart-af18ad09-de7f-4ac7-b8e4-2ff66e64064b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307861665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1307861665
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1871996673
Short name T350
Test name
Test status
Simulation time 572210841713 ps
CPU time 1103.81 seconds
Started Apr 30 03:04:23 PM PDT 24
Finished Apr 30 03:22:48 PM PDT 24
Peak memory 202248 kb
Host smart-10f3889b-b0a0-4fcb-990e-f37124ecf070
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871996673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1871996673
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4217460818
Short name T136
Test name
Test status
Simulation time 325518143433 ps
CPU time 395.98 seconds
Started Apr 30 03:03:18 PM PDT 24
Finished Apr 30 03:09:55 PM PDT 24
Peak memory 202232 kb
Host smart-89275d98-4bf9-4322-9f14-03dbfeb85356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217460818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4217460818
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2616127250
Short name T220
Test name
Test status
Simulation time 538153586531 ps
CPU time 365.24 seconds
Started Apr 30 03:03:42 PM PDT 24
Finished Apr 30 03:09:48 PM PDT 24
Peak memory 202388 kb
Host smart-c45fb099-f3b4-484f-a6ae-08c72c3de587
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616127250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2616127250
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1839766300
Short name T271
Test name
Test status
Simulation time 513400831799 ps
CPU time 1250.03 seconds
Started Apr 30 03:04:38 PM PDT 24
Finished Apr 30 03:25:29 PM PDT 24
Peak memory 202300 kb
Host smart-e8c4b006-e32b-42d2-8d19-2c845cde90c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839766300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1839766300
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.4079898514
Short name T109
Test name
Test status
Simulation time 393007276885 ps
CPU time 438.01 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:10:09 PM PDT 24
Peak memory 202328 kb
Host smart-f8104980-5397-4933-97e8-b515c5f120b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079898514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.4079898514
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3416201525
Short name T313
Test name
Test status
Simulation time 196569861665 ps
CPU time 215.21 seconds
Started Apr 30 03:02:48 PM PDT 24
Finished Apr 30 03:06:24 PM PDT 24
Peak memory 211032 kb
Host smart-3b3dd51b-dc13-4d94-ae34-f979a21511ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416201525 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3416201525
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1195802818
Short name T52
Test name
Test status
Simulation time 8498257657 ps
CPU time 22.34 seconds
Started Apr 30 03:02:06 PM PDT 24
Finished Apr 30 03:02:29 PM PDT 24
Peak memory 201424 kb
Host smart-10cd2d20-4fb7-441f-9f74-643b32642f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195802818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1195802818
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3708199982
Short name T106
Test name
Test status
Simulation time 348711569670 ps
CPU time 395.48 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:09:49 PM PDT 24
Peak memory 202308 kb
Host smart-4e5904c0-505c-4b66-81b0-5df6f842fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708199982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3708199982
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2675755371
Short name T43
Test name
Test status
Simulation time 120100779353 ps
CPU time 473.61 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:11:00 PM PDT 24
Peak memory 202724 kb
Host smart-f8b93457-0176-4e7e-bd8a-fec1e16d2f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675755371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2675755371
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2057716596
Short name T346
Test name
Test status
Simulation time 175846129406 ps
CPU time 435.76 seconds
Started Apr 30 03:02:34 PM PDT 24
Finished Apr 30 03:09:50 PM PDT 24
Peak memory 202348 kb
Host smart-5fa218ee-6517-47e1-a5d9-f9cb8fc07878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057716596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2057716596
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1079341665
Short name T284
Test name
Test status
Simulation time 346869969755 ps
CPU time 727.33 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:14:54 PM PDT 24
Peak memory 202412 kb
Host smart-3235d984-9d52-4fd9-9275-727d4bd63517
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079341665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1079341665
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2201578122
Short name T327
Test name
Test status
Simulation time 167179880277 ps
CPU time 167.37 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:05:54 PM PDT 24
Peak memory 202276 kb
Host smart-15740e50-3f3c-4282-b9a0-148c442b0178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201578122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2201578122
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3525475942
Short name T215
Test name
Test status
Simulation time 78748471369 ps
CPU time 147.04 seconds
Started Apr 30 03:03:28 PM PDT 24
Finished Apr 30 03:05:56 PM PDT 24
Peak memory 210992 kb
Host smart-06614c15-a377-4402-b0ba-d3f0af377ab3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525475942 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3525475942
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1533665707
Short name T213
Test name
Test status
Simulation time 106057908741 ps
CPU time 259.38 seconds
Started Apr 30 03:02:43 PM PDT 24
Finished Apr 30 03:07:03 PM PDT 24
Peak memory 211068 kb
Host smart-4d5d40ab-55d5-4dae-a122-81fc819b2a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533665707 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1533665707
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1660986120
Short name T329
Test name
Test status
Simulation time 483129389965 ps
CPU time 719.81 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:16:07 PM PDT 24
Peak memory 202316 kb
Host smart-f11e1b0b-639b-43f6-84b4-a56e0467ff71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660986120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1660986120
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.274467669
Short name T345
Test name
Test status
Simulation time 557935773456 ps
CPU time 97.69 seconds
Started Apr 30 03:02:56 PM PDT 24
Finished Apr 30 03:04:35 PM PDT 24
Peak memory 212384 kb
Host smart-a2a250f4-a9e4-4697-88e7-c1dc9ef5ca2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274467669 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.274467669
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3426628986
Short name T302
Test name
Test status
Simulation time 511010146497 ps
CPU time 439.12 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 202316 kb
Host smart-79ebd07a-5daf-4273-a9cc-7b9860e530be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426628986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3426628986
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.974317306
Short name T334
Test name
Test status
Simulation time 166527702718 ps
CPU time 74.44 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:04:14 PM PDT 24
Peak memory 202576 kb
Host smart-33cb4b50-6fe0-464b-96a9-996187679996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974317306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.974317306
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2693186451
Short name T210
Test name
Test status
Simulation time 137235215789 ps
CPU time 652.86 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:14:05 PM PDT 24
Peak memory 202652 kb
Host smart-3a66dbb9-58ca-4192-9199-a9b55f8352e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693186451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2693186451
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.2839178010
Short name T104
Test name
Test status
Simulation time 320695274643 ps
CPU time 78.99 seconds
Started Apr 30 03:03:25 PM PDT 24
Finished Apr 30 03:04:45 PM PDT 24
Peak memory 202356 kb
Host smart-37626082-dc70-4cf3-ba23-fee41858193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839178010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.2839178010
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1540240497
Short name T227
Test name
Test status
Simulation time 325410689091 ps
CPU time 363.7 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:09:39 PM PDT 24
Peak memory 202508 kb
Host smart-627749c6-7114-4822-b5e4-5d74c88b53da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540240497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1540240497
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.807721611
Short name T214
Test name
Test status
Simulation time 139929784899 ps
CPU time 468.42 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:11:55 PM PDT 24
Peak memory 202760 kb
Host smart-155c5ab7-4533-407a-9674-c29db50d3f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807721611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.807721611
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.1041041794
Short name T328
Test name
Test status
Simulation time 323766796304 ps
CPU time 205.75 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 202280 kb
Host smart-ae85608a-21a0-4fed-9809-d6a23a44e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041041794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.1041041794
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1081272719
Short name T75
Test name
Test status
Simulation time 8813638973 ps
CPU time 21.62 seconds
Started Apr 30 03:02:23 PM PDT 24
Finished Apr 30 03:02:45 PM PDT 24
Peak memory 201492 kb
Host smart-f758ddf6-076f-42a2-91a8-7e0ad5f8e7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081272719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1081272719
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.2552392134
Short name T333
Test name
Test status
Simulation time 559760669820 ps
CPU time 488.56 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:11:12 PM PDT 24
Peak memory 202264 kb
Host smart-cd1a6ab1-28d9-4fee-a135-f8b8833eed81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552392134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.2552392134
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.1766696147
Short name T321
Test name
Test status
Simulation time 348860609353 ps
CPU time 774.09 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:16:26 PM PDT 24
Peak memory 202328 kb
Host smart-1f753959-a943-4f36-8a75-82ec78d21a44
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766696147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.1766696147
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.4116836451
Short name T154
Test name
Test status
Simulation time 103610947687 ps
CPU time 420.33 seconds
Started Apr 30 03:03:27 PM PDT 24
Finished Apr 30 03:10:28 PM PDT 24
Peak memory 202628 kb
Host smart-c2bb9a6e-5e34-4f92-9174-3a2f962b2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116836451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.4116836451
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1902600529
Short name T641
Test name
Test status
Simulation time 83303424844 ps
CPU time 154.71 seconds
Started Apr 30 03:03:48 PM PDT 24
Finished Apr 30 03:06:23 PM PDT 24
Peak memory 211024 kb
Host smart-c0981d6d-75b8-47aa-bda6-a8c648f38cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902600529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1902600529
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2214543021
Short name T316
Test name
Test status
Simulation time 438158422521 ps
CPU time 579.68 seconds
Started Apr 30 03:04:21 PM PDT 24
Finished Apr 30 03:14:01 PM PDT 24
Peak memory 211040 kb
Host smart-2dfb9b92-e778-4e03-9af1-403c8d51886a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214543021 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2214543021
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3978239936
Short name T279
Test name
Test status
Simulation time 165029792512 ps
CPU time 392.49 seconds
Started Apr 30 03:05:23 PM PDT 24
Finished Apr 30 03:11:56 PM PDT 24
Peak memory 202316 kb
Host smart-96416daf-41d5-4068-99e7-592431828831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978239936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3978239936
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.957134025
Short name T114
Test name
Test status
Simulation time 1393779985 ps
CPU time 3.29 seconds
Started Apr 30 03:02:01 PM PDT 24
Finished Apr 30 03:02:06 PM PDT 24
Peak memory 201404 kb
Host smart-abf5028f-ceeb-4b95-a319-753afb12debe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957134025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alias
ing.957134025
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.682874096
Short name T863
Test name
Test status
Simulation time 23589522915 ps
CPU time 54.67 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:03:08 PM PDT 24
Peak memory 201420 kb
Host smart-54c4fe01-8087-475f-9a96-391ea4f9e85c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682874096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.682874096
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2816046798
Short name T909
Test name
Test status
Simulation time 925487201 ps
CPU time 2.86 seconds
Started Apr 30 03:02:08 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201184 kb
Host smart-e1480ba3-c805-4b5f-9b8e-82ed08085e7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816046798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2816046798
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.577134169
Short name T72
Test name
Test status
Simulation time 675840083 ps
CPU time 1.21 seconds
Started Apr 30 03:02:05 PM PDT 24
Finished Apr 30 03:02:08 PM PDT 24
Peak memory 209640 kb
Host smart-e927b35b-f72d-44ec-b701-7d4c0643165a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577134169 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.577134169
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2678618389
Short name T890
Test name
Test status
Simulation time 380552197 ps
CPU time 1.79 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201196 kb
Host smart-9c903c4a-a8fe-46ea-8d7a-13fc76050616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678618389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2678618389
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.380344783
Short name T907
Test name
Test status
Simulation time 525521702 ps
CPU time 0.89 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:13 PM PDT 24
Peak memory 201176 kb
Host smart-4d259714-2867-4713-b054-012702a13069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380344783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.380344783
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.1520447105
Short name T879
Test name
Test status
Simulation time 4415224486 ps
CPU time 5.84 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201448 kb
Host smart-963c3088-b868-442a-a7eb-909dc12af024
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520447105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.1520447105
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3645202319
Short name T895
Test name
Test status
Simulation time 492488564 ps
CPU time 2.87 seconds
Started Apr 30 03:02:13 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201440 kb
Host smart-4c17d1e1-33e4-4bab-a517-e2bc7e096167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645202319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3645202319
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1492560917
Short name T864
Test name
Test status
Simulation time 8830554068 ps
CPU time 8.44 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:22 PM PDT 24
Peak memory 201448 kb
Host smart-cf374dd2-e7b8-4309-b213-7aee7d0d1273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492560917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1492560917
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3648122025
Short name T812
Test name
Test status
Simulation time 1313577216 ps
CPU time 6.96 seconds
Started Apr 30 03:01:59 PM PDT 24
Finished Apr 30 03:02:07 PM PDT 24
Peak memory 201380 kb
Host smart-e869dd04-0bc0-4a1a-a48e-bc153eb40d14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648122025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3648122025
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2099739357
Short name T873
Test name
Test status
Simulation time 31709543267 ps
CPU time 116.73 seconds
Started Apr 30 03:02:05 PM PDT 24
Finished Apr 30 03:04:03 PM PDT 24
Peak memory 201424 kb
Host smart-214f5400-85b2-466c-b95c-7c9e92d68949
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099739357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2099739357
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.416500245
Short name T124
Test name
Test status
Simulation time 736903457 ps
CPU time 1 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:13 PM PDT 24
Peak memory 201200 kb
Host smart-27eff055-cdcc-4016-acf7-9c89bebff0b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416500245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.416500245
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.40001222
Short name T842
Test name
Test status
Simulation time 407641681 ps
CPU time 1.95 seconds
Started Apr 30 03:02:02 PM PDT 24
Finished Apr 30 03:02:05 PM PDT 24
Peak memory 201188 kb
Host smart-19a6c5eb-a090-425b-aa48-e8845b68b625
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40001222 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.40001222
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2395999053
Short name T123
Test name
Test status
Simulation time 400884354 ps
CPU time 0.99 seconds
Started Apr 30 03:02:08 PM PDT 24
Finished Apr 30 03:02:10 PM PDT 24
Peak memory 201196 kb
Host smart-16f59172-feab-4941-8274-79c3fea7ce30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395999053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2395999053
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.2347840171
Short name T824
Test name
Test status
Simulation time 421050590 ps
CPU time 0.75 seconds
Started Apr 30 03:02:03 PM PDT 24
Finished Apr 30 03:02:06 PM PDT 24
Peak memory 201232 kb
Host smart-12228944-9333-4214-b132-865e962997ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347840171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.2347840171
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1554652168
Short name T910
Test name
Test status
Simulation time 4099730518 ps
CPU time 5.16 seconds
Started Apr 30 03:02:13 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201420 kb
Host smart-8976a170-f206-4739-b936-cad77afb20a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554652168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1554652168
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2833893791
Short name T819
Test name
Test status
Simulation time 471796818 ps
CPU time 1.46 seconds
Started Apr 30 03:02:07 PM PDT 24
Finished Apr 30 03:02:10 PM PDT 24
Peak memory 201540 kb
Host smart-846a95e7-7999-42a7-ac67-792a9e2fc331
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833893791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2833893791
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3321100096
Short name T810
Test name
Test status
Simulation time 393078701 ps
CPU time 1.75 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201272 kb
Host smart-8303bcc1-4a57-4e68-8455-9bbef25bd067
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321100096 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3321100096
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2629403363
Short name T820
Test name
Test status
Simulation time 432838830 ps
CPU time 0.89 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201264 kb
Host smart-8125bf3d-3a28-4da9-a5c5-4c7d3d4842c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629403363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2629403363
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1368489218
Short name T847
Test name
Test status
Simulation time 4039673176 ps
CPU time 3.6 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:21 PM PDT 24
Peak memory 201440 kb
Host smart-fb74c7db-ce0e-47c0-86fe-c6a0789e4c4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368489218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1368489218
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2355385169
Short name T917
Test name
Test status
Simulation time 555273993 ps
CPU time 1.56 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201272 kb
Host smart-d861b851-29db-4ba2-be25-75ea368d7f7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355385169 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2355385169
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1537162949
Short name T116
Test name
Test status
Simulation time 384291129 ps
CPU time 0.97 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201172 kb
Host smart-620e3d12-1e7e-41a7-bc64-8b1b3d0dd9a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537162949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1537162949
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3095132666
Short name T827
Test name
Test status
Simulation time 457031821 ps
CPU time 1.23 seconds
Started Apr 30 03:02:19 PM PDT 24
Finished Apr 30 03:02:21 PM PDT 24
Peak memory 201208 kb
Host smart-4d23d3ff-fc49-4353-b812-e484d643a94e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095132666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3095132666
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1614393427
Short name T843
Test name
Test status
Simulation time 4716916242 ps
CPU time 3.18 seconds
Started Apr 30 03:02:17 PM PDT 24
Finished Apr 30 03:02:21 PM PDT 24
Peak memory 201456 kb
Host smart-895aa21f-db47-4e30-8066-20559dbfdb34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614393427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1614393427
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3388892833
Short name T836
Test name
Test status
Simulation time 414083596 ps
CPU time 3 seconds
Started Apr 30 03:02:14 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 210676 kb
Host smart-76b13ef9-7635-43d5-ae4a-9d339cd55b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388892833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3388892833
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3310668690
Short name T359
Test name
Test status
Simulation time 4418493398 ps
CPU time 11.13 seconds
Started Apr 30 03:02:31 PM PDT 24
Finished Apr 30 03:02:43 PM PDT 24
Peak memory 201724 kb
Host smart-2f1cf153-06e1-4f4f-a2bd-d861f23f1e46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310668690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3310668690
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2667219533
Short name T905
Test name
Test status
Simulation time 595605668 ps
CPU time 2.13 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:14 PM PDT 24
Peak memory 201460 kb
Host smart-035552bc-5b78-4ae0-87f6-fe99772c101a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667219533 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2667219533
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2786260115
Short name T122
Test name
Test status
Simulation time 440756435 ps
CPU time 1.12 seconds
Started Apr 30 03:02:09 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201136 kb
Host smart-0a281eee-aa99-47da-a22c-c26d2fccc7be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786260115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2786260115
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2427883794
Short name T913
Test name
Test status
Simulation time 338494840 ps
CPU time 0.87 seconds
Started Apr 30 03:02:23 PM PDT 24
Finished Apr 30 03:02:24 PM PDT 24
Peak memory 201248 kb
Host smart-6ecc305f-ed30-4da8-aa76-60e8b8ce84da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427883794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2427883794
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3593734378
Short name T859
Test name
Test status
Simulation time 2576962576 ps
CPU time 2.48 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201276 kb
Host smart-25c69ff9-e497-438d-9707-a6f63e9f758a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593734378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3593734378
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2658688448
Short name T63
Test name
Test status
Simulation time 524322517 ps
CPU time 2.25 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201560 kb
Host smart-d44e5630-7cf9-43cb-910b-c8828ab091fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658688448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2658688448
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3217739282
Short name T70
Test name
Test status
Simulation time 646213863 ps
CPU time 1.62 seconds
Started Apr 30 03:02:09 PM PDT 24
Finished Apr 30 03:02:11 PM PDT 24
Peak memory 201284 kb
Host smart-77629314-bd54-4283-9eb1-18c5d4885a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217739282 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3217739282
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4059289410
Short name T892
Test name
Test status
Simulation time 514081845 ps
CPU time 1.96 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201024 kb
Host smart-650f2e54-1818-4a5e-976c-93b40b4ca20c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059289410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4059289410
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1294131017
Short name T823
Test name
Test status
Simulation time 313937600 ps
CPU time 0.83 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201204 kb
Host smart-f8178d09-b4d5-4da4-b314-82442cc04e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294131017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1294131017
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2579740355
Short name T834
Test name
Test status
Simulation time 5308555047 ps
CPU time 4.41 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:18 PM PDT 24
Peak memory 201432 kb
Host smart-410585ee-de0d-4499-8a09-eca253502313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579740355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2579740355
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1709029363
Short name T816
Test name
Test status
Simulation time 961935783 ps
CPU time 3.58 seconds
Started Apr 30 03:02:34 PM PDT 24
Finished Apr 30 03:02:38 PM PDT 24
Peak memory 210712 kb
Host smart-381a284f-dc02-4e6b-97bd-8c23014207b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709029363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1709029363
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.908246090
Short name T875
Test name
Test status
Simulation time 4642728935 ps
CPU time 6.81 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201508 kb
Host smart-fc06cf85-1852-4051-a1f2-350d6da5a9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908246090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_in
tg_err.908246090
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3742617566
Short name T889
Test name
Test status
Simulation time 342705112 ps
CPU time 1.62 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:18 PM PDT 24
Peak memory 201280 kb
Host smart-0bb891a6-635e-4892-98c5-6a91197b68f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742617566 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3742617566
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.395830061
Short name T911
Test name
Test status
Simulation time 480620337 ps
CPU time 1.31 seconds
Started Apr 30 03:02:14 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201220 kb
Host smart-5def703b-dc45-4877-8a17-86db6e84fd55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395830061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.395830061
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1766167174
Short name T831
Test name
Test status
Simulation time 394253652 ps
CPU time 0.82 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201212 kb
Host smart-aceb0c12-f35e-417b-b10b-387c41087573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766167174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1766167174
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2373102251
Short name T48
Test name
Test status
Simulation time 2609629787 ps
CPU time 10.94 seconds
Started Apr 30 03:02:30 PM PDT 24
Finished Apr 30 03:02:41 PM PDT 24
Peak memory 201276 kb
Host smart-4846bca6-bb60-467d-a196-224eafb8bf4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373102251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2373102251
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2419773445
Short name T73
Test name
Test status
Simulation time 8081582928 ps
CPU time 20.84 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:38 PM PDT 24
Peak memory 201488 kb
Host smart-b3e409a0-f6d1-491b-9c41-8d22ecbb1634
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419773445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2419773445
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3825391665
Short name T71
Test name
Test status
Simulation time 498102077 ps
CPU time 1.22 seconds
Started Apr 30 03:02:17 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201284 kb
Host smart-fe026375-45f7-4d28-b001-3d74756f0c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825391665 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3825391665
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2567061787
Short name T908
Test name
Test status
Simulation time 523711521 ps
CPU time 2.03 seconds
Started Apr 30 03:02:27 PM PDT 24
Finished Apr 30 03:02:29 PM PDT 24
Peak memory 201252 kb
Host smart-27cb7cd8-b71a-43a8-b0fb-2f0754399258
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567061787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2567061787
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2209250595
Short name T799
Test name
Test status
Simulation time 427784041 ps
CPU time 1.56 seconds
Started Apr 30 03:02:29 PM PDT 24
Finished Apr 30 03:02:31 PM PDT 24
Peak memory 201240 kb
Host smart-d49f2573-3065-420d-ba35-0892c4b24f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209250595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2209250595
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.4007873582
Short name T129
Test name
Test status
Simulation time 2458367008 ps
CPU time 9.62 seconds
Started Apr 30 03:02:37 PM PDT 24
Finished Apr 30 03:02:48 PM PDT 24
Peak memory 201264 kb
Host smart-f2e6d266-ba84-4dcd-898e-04820bc229cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007873582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.4007873582
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3932586954
Short name T840
Test name
Test status
Simulation time 415485820 ps
CPU time 3.47 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201492 kb
Host smart-7909d03a-4c68-4bd5-8d59-1fbafce63f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932586954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3932586954
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2028396469
Short name T902
Test name
Test status
Simulation time 8088891312 ps
CPU time 22.61 seconds
Started Apr 30 03:02:32 PM PDT 24
Finished Apr 30 03:02:55 PM PDT 24
Peak memory 201500 kb
Host smart-8b153381-1cd1-47b1-b905-11405b4e57fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028396469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2028396469
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.315977645
Short name T68
Test name
Test status
Simulation time 602774978 ps
CPU time 0.97 seconds
Started Apr 30 03:02:18 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201280 kb
Host smart-45680cd4-8f3a-4348-88e6-4cb6548deb04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315977645 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.315977645
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3734009223
Short name T886
Test name
Test status
Simulation time 887895851 ps
CPU time 0.92 seconds
Started Apr 30 03:02:29 PM PDT 24
Finished Apr 30 03:02:30 PM PDT 24
Peak memory 201220 kb
Host smart-cd1c2662-fcbc-4eae-8685-cea999d3c216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734009223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3734009223
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.470029632
Short name T894
Test name
Test status
Simulation time 523329441 ps
CPU time 0.92 seconds
Started Apr 30 03:02:17 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201240 kb
Host smart-e92fd6cb-4776-44e3-9228-96d8297a9fa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470029632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.470029632
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2003871217
Short name T822
Test name
Test status
Simulation time 4418272707 ps
CPU time 3.4 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201476 kb
Host smart-23a34a88-dfec-4142-898c-73caaedabe9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003871217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2003871217
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1081096826
Short name T891
Test name
Test status
Simulation time 481827733 ps
CPU time 2.24 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201376 kb
Host smart-6aeab9eb-f227-4b12-8ab0-eca2affaa6b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081096826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1081096826
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2230115567
Short name T357
Test name
Test status
Simulation time 9510204419 ps
CPU time 8.08 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:26 PM PDT 24
Peak memory 201524 kb
Host smart-ed229079-4d6e-4f26-bbcd-fab98aefd9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230115567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2230115567
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2295101636
Short name T896
Test name
Test status
Simulation time 499935021 ps
CPU time 1.41 seconds
Started Apr 30 03:02:40 PM PDT 24
Finished Apr 30 03:02:42 PM PDT 24
Peak memory 201320 kb
Host smart-c24ba228-c6ce-4485-b6cd-d254ab0209de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295101636 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2295101636
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2450125457
Short name T120
Test name
Test status
Simulation time 566239928 ps
CPU time 1.07 seconds
Started Apr 30 03:02:29 PM PDT 24
Finished Apr 30 03:02:30 PM PDT 24
Peak memory 201144 kb
Host smart-38049577-11bf-4431-82ec-97303919b4b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450125457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2450125457
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.2388884198
Short name T804
Test name
Test status
Simulation time 464456774 ps
CPU time 1.65 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201180 kb
Host smart-40139ca1-8bdf-421c-889c-b6905cd72b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388884198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.2388884198
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.671486767
Short name T49
Test name
Test status
Simulation time 2570680722 ps
CPU time 5.82 seconds
Started Apr 30 03:02:13 PM PDT 24
Finished Apr 30 03:02:21 PM PDT 24
Peak memory 201244 kb
Host smart-0d36ce65-32fc-4f3b-921a-317f19762a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671486767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.671486767
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1142453682
Short name T865
Test name
Test status
Simulation time 549129803 ps
CPU time 1.76 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201484 kb
Host smart-30bdea76-4938-4492-8cf8-40dd0c1b6e4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142453682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1142453682
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.2714844087
Short name T51
Test name
Test status
Simulation time 4710584491 ps
CPU time 12.43 seconds
Started Apr 30 03:02:26 PM PDT 24
Finished Apr 30 03:02:39 PM PDT 24
Peak memory 201424 kb
Host smart-4db1961c-b25b-4ed5-b724-73fb1d0e7b61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714844087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.2714844087
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2766698414
Short name T866
Test name
Test status
Simulation time 336035972 ps
CPU time 1.59 seconds
Started Apr 30 03:02:22 PM PDT 24
Finished Apr 30 03:02:24 PM PDT 24
Peak memory 201284 kb
Host smart-ffb3b6ed-5ad7-4f94-9cc5-aa77ddaa738c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766698414 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2766698414
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2369184802
Short name T125
Test name
Test status
Simulation time 572645104 ps
CPU time 1.19 seconds
Started Apr 30 03:02:30 PM PDT 24
Finished Apr 30 03:02:32 PM PDT 24
Peak memory 201208 kb
Host smart-85e402ab-9d0f-4d81-81df-83d78a66461c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369184802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2369184802
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2140871824
Short name T880
Test name
Test status
Simulation time 440617492 ps
CPU time 1.12 seconds
Started Apr 30 03:02:17 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201232 kb
Host smart-7da570be-c0da-4248-95cf-3dae8b34f957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140871824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2140871824
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2942714287
Short name T884
Test name
Test status
Simulation time 4380929807 ps
CPU time 10.79 seconds
Started Apr 30 03:02:37 PM PDT 24
Finished Apr 30 03:02:49 PM PDT 24
Peak memory 201512 kb
Host smart-23365fc3-3760-4b39-955c-335bd16339d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942714287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2942714287
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3132853706
Short name T860
Test name
Test status
Simulation time 640466703 ps
CPU time 1.55 seconds
Started Apr 30 03:02:18 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201472 kb
Host smart-89798383-f6a7-4b12-93d8-5926a4c20cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132853706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3132853706
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.397461962
Short name T356
Test name
Test status
Simulation time 4135656505 ps
CPU time 10.97 seconds
Started Apr 30 03:02:17 PM PDT 24
Finished Apr 30 03:02:29 PM PDT 24
Peak memory 201464 kb
Host smart-0f553f54-e087-48d6-ab86-e3571aac1fe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397461962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.397461962
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.391093534
Short name T805
Test name
Test status
Simulation time 619370762 ps
CPU time 1.17 seconds
Started Apr 30 03:02:25 PM PDT 24
Finished Apr 30 03:02:27 PM PDT 24
Peak memory 201288 kb
Host smart-7f0ecb7e-c9f9-4ff3-91b2-e7f444e9f7dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391093534 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.391093534
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1831460532
Short name T850
Test name
Test status
Simulation time 461370452 ps
CPU time 1.74 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:19 PM PDT 24
Peak memory 201200 kb
Host smart-a86a1fd9-23df-48e2-a894-d66c2bbb58e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831460532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1831460532
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3482099998
Short name T808
Test name
Test status
Simulation time 452860463 ps
CPU time 1.18 seconds
Started Apr 30 03:02:23 PM PDT 24
Finished Apr 30 03:02:24 PM PDT 24
Peak memory 201216 kb
Host smart-2ba6bde5-3227-44be-b338-74069b1a8999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482099998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3482099998
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.4134478878
Short name T878
Test name
Test status
Simulation time 2152751016 ps
CPU time 2.87 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201332 kb
Host smart-9e6a1028-206f-4540-9262-ac1deb1f3639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134478878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.4134478878
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.3945492341
Short name T62
Test name
Test status
Simulation time 497662757 ps
CPU time 3.34 seconds
Started Apr 30 03:02:18 PM PDT 24
Finished Apr 30 03:02:22 PM PDT 24
Peak memory 201416 kb
Host smart-e4da3904-ed4c-458f-b5f8-8e8b4bcab353
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945492341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.3945492341
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.4164109524
Short name T853
Test name
Test status
Simulation time 4228915355 ps
CPU time 6.61 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:02:46 PM PDT 24
Peak memory 201528 kb
Host smart-409924f8-a97a-4bc1-b473-4f4f8207fafe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164109524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.4164109524
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.460333515
Short name T121
Test name
Test status
Simulation time 762211807 ps
CPU time 3.03 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201424 kb
Host smart-fde42c2f-1603-4572-8c68-70711ebaaf98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460333515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.460333515
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2724785281
Short name T115
Test name
Test status
Simulation time 676836927 ps
CPU time 4.58 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:18 PM PDT 24
Peak memory 201416 kb
Host smart-af66fc1b-7d1c-4d1b-a6a8-cda68aa38bd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724785281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2724785281
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.4054334909
Short name T118
Test name
Test status
Simulation time 1206594001 ps
CPU time 3.35 seconds
Started Apr 30 03:02:02 PM PDT 24
Finished Apr 30 03:02:06 PM PDT 24
Peak memory 201136 kb
Host smart-16dd7761-a0c3-471e-be6c-473f1ff862b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054334909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.4054334909
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.3966409489
Short name T814
Test name
Test status
Simulation time 436581248 ps
CPU time 1.34 seconds
Started Apr 30 03:02:07 PM PDT 24
Finished Apr 30 03:02:10 PM PDT 24
Peak memory 209656 kb
Host smart-bf6aa883-07b1-4e25-91dc-68f7bd9b6f51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966409489 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.3966409489
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1648589706
Short name T113
Test name
Test status
Simulation time 734870240 ps
CPU time 0.91 seconds
Started Apr 30 03:02:07 PM PDT 24
Finished Apr 30 03:02:14 PM PDT 24
Peak memory 201240 kb
Host smart-c3a90085-2ca2-4154-b229-938ee6d0b54d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648589706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1648589706
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.524175532
Short name T828
Test name
Test status
Simulation time 380347384 ps
CPU time 0.89 seconds
Started Apr 30 03:02:03 PM PDT 24
Finished Apr 30 03:02:06 PM PDT 24
Peak memory 201208 kb
Host smart-d67de7f2-7589-4a74-8f88-d2e095405e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524175532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.524175532
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1503816011
Short name T131
Test name
Test status
Simulation time 5233377522 ps
CPU time 9.54 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:23 PM PDT 24
Peak memory 201452 kb
Host smart-0d284c05-a753-4749-8a82-0b32b9f3f1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503816011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1503816011
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4277511788
Short name T872
Test name
Test status
Simulation time 397453866 ps
CPU time 2.26 seconds
Started Apr 30 03:02:07 PM PDT 24
Finished Apr 30 03:02:10 PM PDT 24
Peak memory 201452 kb
Host smart-2c4e1ac1-710d-4a21-be89-c2d8b057dab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277511788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4277511788
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4204195268
Short name T841
Test name
Test status
Simulation time 4356026982 ps
CPU time 11.6 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:25 PM PDT 24
Peak memory 201448 kb
Host smart-21c069c2-2a7a-4821-a8ca-a2e51c5d25db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204195268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.4204195268
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3112085534
Short name T832
Test name
Test status
Simulation time 441822967 ps
CPU time 1.2 seconds
Started Apr 30 03:02:14 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201204 kb
Host smart-ee2e7267-5f86-45ae-b499-9612f4c08f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112085534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3112085534
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.4146716679
Short name T912
Test name
Test status
Simulation time 328392871 ps
CPU time 0.91 seconds
Started Apr 30 03:02:35 PM PDT 24
Finished Apr 30 03:02:36 PM PDT 24
Peak memory 201224 kb
Host smart-7ddca4af-d845-447b-b868-e2e1d291d94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146716679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.4146716679
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4011906782
Short name T809
Test name
Test status
Simulation time 416187039 ps
CPU time 1.6 seconds
Started Apr 30 03:02:23 PM PDT 24
Finished Apr 30 03:02:25 PM PDT 24
Peak memory 201208 kb
Host smart-cf9d93a0-1ac2-4a85-a35a-5b283ed36a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011906782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4011906782
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2192588893
Short name T821
Test name
Test status
Simulation time 496724017 ps
CPU time 1.37 seconds
Started Apr 30 03:02:21 PM PDT 24
Finished Apr 30 03:02:23 PM PDT 24
Peak memory 201208 kb
Host smart-708fbe1c-5d29-4a3b-9baa-2c992c60da4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192588893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2192588893
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.2881630065
Short name T813
Test name
Test status
Simulation time 428541322 ps
CPU time 1.73 seconds
Started Apr 30 03:02:17 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201184 kb
Host smart-e8875eee-f7c9-4266-81ee-c4aa9fc4a10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881630065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.2881630065
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.883443855
Short name T801
Test name
Test status
Simulation time 523347329 ps
CPU time 0.95 seconds
Started Apr 30 03:02:42 PM PDT 24
Finished Apr 30 03:02:44 PM PDT 24
Peak memory 201224 kb
Host smart-0f3177b1-b162-4729-abaf-5999ea841d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883443855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.883443855
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.446377622
Short name T874
Test name
Test status
Simulation time 407296725 ps
CPU time 0.93 seconds
Started Apr 30 03:02:34 PM PDT 24
Finished Apr 30 03:02:35 PM PDT 24
Peak memory 201224 kb
Host smart-6182ab26-6bc4-4cbb-ada7-025cd3812859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446377622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.446377622
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.612258802
Short name T861
Test name
Test status
Simulation time 511538414 ps
CPU time 0.97 seconds
Started Apr 30 03:02:30 PM PDT 24
Finished Apr 30 03:02:31 PM PDT 24
Peak memory 201264 kb
Host smart-b23305e6-e971-4d8f-a269-9be781f7f76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612258802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.612258802
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3232642186
Short name T825
Test name
Test status
Simulation time 484646505 ps
CPU time 0.82 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201132 kb
Host smart-58e03ee1-ee42-42df-87a8-34c6b1769ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232642186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3232642186
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.242559582
Short name T802
Test name
Test status
Simulation time 422009709 ps
CPU time 0.87 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201120 kb
Host smart-b0b7773a-6c53-49ce-bf06-1cbdebee7df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242559582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.242559582
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3373341831
Short name T851
Test name
Test status
Simulation time 833123614 ps
CPU time 2.04 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201380 kb
Host smart-22de8523-e351-4e85-ab11-43ff1d334506
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373341831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3373341831
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.4104096958
Short name T903
Test name
Test status
Simulation time 46123776966 ps
CPU time 160.71 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:04:54 PM PDT 24
Peak memory 201520 kb
Host smart-eb41998b-ce1d-4393-8737-be1ecaed4488
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104096958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.4104096958
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2991265443
Short name T899
Test name
Test status
Simulation time 840448860 ps
CPU time 1.2 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201176 kb
Host smart-39d2a2bc-71c6-42eb-b901-d520c5cfcd47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991265443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2991265443
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4138211480
Short name T906
Test name
Test status
Simulation time 617860320 ps
CPU time 2.27 seconds
Started Apr 30 03:02:09 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201280 kb
Host smart-eb636b92-28bd-4a66-9458-801ef206a723
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138211480 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4138211480
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.4272694188
Short name T112
Test name
Test status
Simulation time 474694355 ps
CPU time 1.05 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:13 PM PDT 24
Peak memory 201240 kb
Host smart-d83fbc57-9cfb-46cb-b646-8ef823ccebd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272694188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.4272694188
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1575184824
Short name T904
Test name
Test status
Simulation time 411081705 ps
CPU time 0.85 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:14 PM PDT 24
Peak memory 201208 kb
Host smart-9f7129ca-c9c8-4446-aa68-1d98a36f7363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575184824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1575184824
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3458057743
Short name T876
Test name
Test status
Simulation time 4451038598 ps
CPU time 17.53 seconds
Started Apr 30 03:02:08 PM PDT 24
Finished Apr 30 03:02:27 PM PDT 24
Peak memory 201396 kb
Host smart-5ddab17e-9815-4f3b-9342-0198acc37799
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458057743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3458057743
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3888253926
Short name T67
Test name
Test status
Simulation time 738986145 ps
CPU time 1.92 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201228 kb
Host smart-841146ad-2632-46bc-8672-8adf3c188a57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888253926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3888253926
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.138609894
Short name T901
Test name
Test status
Simulation time 4260953167 ps
CPU time 7.2 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:21 PM PDT 24
Peak memory 201440 kb
Host smart-c78099df-0874-4a90-ad22-00b0b849e503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138609894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.138609894
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3356050753
Short name T869
Test name
Test status
Simulation time 356384628 ps
CPU time 1.21 seconds
Started Apr 30 03:02:27 PM PDT 24
Finished Apr 30 03:02:29 PM PDT 24
Peak memory 201180 kb
Host smart-f3f541e6-15f6-4b88-9a28-a3ded763fa37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356050753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3356050753
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.7489541
Short name T848
Test name
Test status
Simulation time 585866332 ps
CPU time 0.75 seconds
Started Apr 30 03:02:37 PM PDT 24
Finished Apr 30 03:02:38 PM PDT 24
Peak memory 201236 kb
Host smart-8eb07605-f0aa-4253-bd97-babeb07d101c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7489541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.7489541
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1775322477
Short name T897
Test name
Test status
Simulation time 422380086 ps
CPU time 1.58 seconds
Started Apr 30 03:02:18 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201208 kb
Host smart-ec2d58f3-a841-43c2-bfff-3591928dda87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775322477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1775322477
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1278573340
Short name T852
Test name
Test status
Simulation time 418912614 ps
CPU time 1.63 seconds
Started Apr 30 03:02:33 PM PDT 24
Finished Apr 30 03:02:35 PM PDT 24
Peak memory 201244 kb
Host smart-7e4176d3-a708-480d-9cdf-9fe4207bc87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278573340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1278573340
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3770659580
Short name T800
Test name
Test status
Simulation time 415504311 ps
CPU time 1.61 seconds
Started Apr 30 03:02:26 PM PDT 24
Finished Apr 30 03:02:28 PM PDT 24
Peak memory 201244 kb
Host smart-db5b808a-3a9e-4090-882d-5b6aa3928ed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770659580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3770659580
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3862147853
Short name T855
Test name
Test status
Simulation time 565966872 ps
CPU time 0.76 seconds
Started Apr 30 03:02:34 PM PDT 24
Finished Apr 30 03:02:35 PM PDT 24
Peak memory 201224 kb
Host smart-7992d59b-7e9a-4a80-a4d2-25dd3c3f42d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862147853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3862147853
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2593748331
Short name T837
Test name
Test status
Simulation time 478297300 ps
CPU time 0.93 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:18 PM PDT 24
Peak memory 201204 kb
Host smart-ad3fa781-339f-4114-9ed0-93b4f055ae9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593748331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2593748331
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2672675327
Short name T803
Test name
Test status
Simulation time 517883872 ps
CPU time 0.91 seconds
Started Apr 30 03:02:32 PM PDT 24
Finished Apr 30 03:02:33 PM PDT 24
Peak memory 201204 kb
Host smart-ec0258e6-b9b3-49fa-8660-d75e92093e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672675327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2672675327
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3166641585
Short name T893
Test name
Test status
Simulation time 331059075 ps
CPU time 0.98 seconds
Started Apr 30 03:02:31 PM PDT 24
Finished Apr 30 03:02:32 PM PDT 24
Peak memory 201204 kb
Host smart-e1f5323e-fe64-498c-9152-895895072459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166641585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3166641585
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2499534312
Short name T857
Test name
Test status
Simulation time 403259050 ps
CPU time 1.55 seconds
Started Apr 30 03:02:34 PM PDT 24
Finished Apr 30 03:02:36 PM PDT 24
Peak memory 201248 kb
Host smart-d36b79c2-10dc-49fe-ab4f-4578958a3018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499534312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2499534312
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3649446255
Short name T885
Test name
Test status
Simulation time 1020496347 ps
CPU time 3.61 seconds
Started Apr 30 03:02:08 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201324 kb
Host smart-6717840f-178a-4b40-ad76-2a00063e7d87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649446255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3649446255
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1142883464
Short name T854
Test name
Test status
Simulation time 570448797 ps
CPU time 1.59 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201160 kb
Host smart-e9fcbac5-75c6-4a7e-ae85-87fe1bfeb89d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142883464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1142883464
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1856287588
Short name T811
Test name
Test status
Simulation time 501204198 ps
CPU time 1.98 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201104 kb
Host smart-ee08bab2-207d-4f6f-a353-4fd297f6351e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856287588 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1856287588
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.902728294
Short name T870
Test name
Test status
Simulation time 513894931 ps
CPU time 1.92 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201196 kb
Host smart-3e3c539d-74ca-4ed0-a2ac-66e1b9d7348f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902728294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.902728294
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1593730227
Short name T830
Test name
Test status
Simulation time 344235963 ps
CPU time 1.41 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201152 kb
Host smart-7170c8b0-0218-4a82-8464-a02efdd2b844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593730227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1593730227
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.982210807
Short name T128
Test name
Test status
Simulation time 2427028379 ps
CPU time 6.27 seconds
Started Apr 30 03:02:09 PM PDT 24
Finished Apr 30 03:02:16 PM PDT 24
Peak memory 201316 kb
Host smart-482ab3eb-b0fd-4466-9c86-64e22a650ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982210807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.982210807
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2721819335
Short name T871
Test name
Test status
Simulation time 492093453 ps
CPU time 1.56 seconds
Started Apr 30 03:02:08 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201488 kb
Host smart-7013a83c-5af4-4972-9fb0-18621eb5cda3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721819335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2721819335
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.175931188
Short name T74
Test name
Test status
Simulation time 8740241021 ps
CPU time 7.35 seconds
Started Apr 30 03:02:06 PM PDT 24
Finished Apr 30 03:02:14 PM PDT 24
Peak memory 201416 kb
Host smart-2d2f2cfa-a280-4bf0-b9f7-01c9b154e66a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175931188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_int
g_err.175931188
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1317466412
Short name T806
Test name
Test status
Simulation time 315469042 ps
CPU time 1.35 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:18 PM PDT 24
Peak memory 201192 kb
Host smart-a18e9540-d824-4b79-a32f-233f9b9e73fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317466412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1317466412
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2954348046
Short name T835
Test name
Test status
Simulation time 520147852 ps
CPU time 1.03 seconds
Started Apr 30 03:02:42 PM PDT 24
Finished Apr 30 03:02:44 PM PDT 24
Peak memory 201208 kb
Host smart-30ae372b-5683-4c03-8f47-36ab6a68ec2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954348046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2954348046
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2031397614
Short name T858
Test name
Test status
Simulation time 415137245 ps
CPU time 0.73 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201220 kb
Host smart-99375992-e375-4964-bcc3-84d7b69f985c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031397614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2031397614
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4226344911
Short name T849
Test name
Test status
Simulation time 396747734 ps
CPU time 0.87 seconds
Started Apr 30 03:02:29 PM PDT 24
Finished Apr 30 03:02:35 PM PDT 24
Peak memory 201204 kb
Host smart-41f23373-de6d-4feb-aec5-1f192d8651cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226344911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4226344911
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.564860639
Short name T867
Test name
Test status
Simulation time 437321505 ps
CPU time 1.71 seconds
Started Apr 30 03:02:20 PM PDT 24
Finished Apr 30 03:02:22 PM PDT 24
Peak memory 201240 kb
Host smart-5b996748-16e4-4699-aae7-5a59d1af63dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564860639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.564860639
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1430432641
Short name T838
Test name
Test status
Simulation time 374216163 ps
CPU time 1.08 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:18 PM PDT 24
Peak memory 201168 kb
Host smart-93eeb5cf-e42f-47ba-a653-a1c7b6834fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430432641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1430432641
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.2680164702
Short name T856
Test name
Test status
Simulation time 390219976 ps
CPU time 1.54 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:02:40 PM PDT 24
Peak memory 201204 kb
Host smart-353328cc-eb70-4214-97b7-8a2db369be0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680164702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.2680164702
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.2529995912
Short name T883
Test name
Test status
Simulation time 485785256 ps
CPU time 0.77 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:02:40 PM PDT 24
Peak memory 201204 kb
Host smart-a71ee6ff-36ed-46c8-86fb-fa2b5e14e75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529995912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.2529995912
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1363669232
Short name T882
Test name
Test status
Simulation time 511419597 ps
CPU time 1.07 seconds
Started Apr 30 03:02:14 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201240 kb
Host smart-69102500-917b-4fa9-a732-0a6e9f7177e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363669232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1363669232
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.1521578692
Short name T818
Test name
Test status
Simulation time 403490662 ps
CPU time 1.62 seconds
Started Apr 30 03:02:32 PM PDT 24
Finished Apr 30 03:02:34 PM PDT 24
Peak memory 201224 kb
Host smart-097eb9f8-37b0-40a5-97f4-aca6fb9ba02b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521578692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.1521578692
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3313910864
Short name T815
Test name
Test status
Simulation time 586178590 ps
CPU time 1.15 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201316 kb
Host smart-2ba3c0fd-bbed-41ef-a7d0-7809d35c1140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313910864 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3313910864
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4144817591
Short name T916
Test name
Test status
Simulation time 455682143 ps
CPU time 1.38 seconds
Started Apr 30 03:02:09 PM PDT 24
Finished Apr 30 03:02:11 PM PDT 24
Peak memory 201156 kb
Host smart-b1b5e52d-9b07-44c7-b272-c0c20afe24b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144817591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4144817591
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2827467890
Short name T839
Test name
Test status
Simulation time 521456762 ps
CPU time 1.96 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201156 kb
Host smart-fc73ddad-abc0-4b65-bf08-e5b1a8c745bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827467890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2827467890
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.789989130
Short name T845
Test name
Test status
Simulation time 4644357327 ps
CPU time 11.73 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:28 PM PDT 24
Peak memory 201572 kb
Host smart-0af5ec96-18b8-42d8-8a6b-cbb5e5302771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789989130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.789989130
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2521932547
Short name T844
Test name
Test status
Simulation time 353605829 ps
CPU time 3.02 seconds
Started Apr 30 03:02:07 PM PDT 24
Finished Apr 30 03:02:11 PM PDT 24
Peak memory 210588 kb
Host smart-64454c6e-438d-4e08-ba4b-67334af05ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521932547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2521932547
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.142876105
Short name T881
Test name
Test status
Simulation time 9325321094 ps
CPU time 4.72 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201496 kb
Host smart-a4385506-dd34-4c6e-bbf1-eb85ffaf68bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142876105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.142876105
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2584839576
Short name T56
Test name
Test status
Simulation time 620558219 ps
CPU time 2.27 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:16 PM PDT 24
Peak memory 201316 kb
Host smart-a0b94acb-a7d3-4228-b7c4-0f2842a10712
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584839576 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2584839576
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.13201854
Short name T126
Test name
Test status
Simulation time 360448198 ps
CPU time 1.5 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201164 kb
Host smart-73043c7d-e030-4090-9def-6f1df40cd4cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13201854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.13201854
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2791133650
Short name T833
Test name
Test status
Simulation time 395288784 ps
CPU time 0.86 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:12 PM PDT 24
Peak memory 201212 kb
Host smart-a5561d0c-fe52-493e-8cbf-0390818fa748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791133650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2791133650
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2205841910
Short name T898
Test name
Test status
Simulation time 2205041947 ps
CPU time 3.79 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:21 PM PDT 24
Peak memory 201280 kb
Host smart-90c97b77-b562-40bd-b19b-ec46abb37d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205841910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2205841910
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3170097394
Short name T60
Test name
Test status
Simulation time 381336175 ps
CPU time 1.65 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201492 kb
Host smart-88b1b343-55fb-442e-aa17-3bfb12216791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170097394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3170097394
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3651834436
Short name T358
Test name
Test status
Simulation time 4573796416 ps
CPU time 3.11 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201404 kb
Host smart-576bdfe7-ba6e-4334-93d2-e0a87a45f908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651834436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3651834436
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.763700169
Short name T91
Test name
Test status
Simulation time 576070765 ps
CPU time 1.2 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201224 kb
Host smart-adbdbec4-fd54-49c7-a599-801c62a01e51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763700169 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.763700169
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.897879215
Short name T119
Test name
Test status
Simulation time 378039485 ps
CPU time 0.97 seconds
Started Apr 30 03:02:10 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201108 kb
Host smart-859265d2-2e84-43c5-91d4-707ccf9e2766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897879215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.897879215
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1173446941
Short name T862
Test name
Test status
Simulation time 491771947 ps
CPU time 0.99 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201204 kb
Host smart-9341202e-f205-4fe1-8c2e-f8f16c36bd71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173446941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1173446941
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.1393957242
Short name T877
Test name
Test status
Simulation time 4214748407 ps
CPU time 2.7 seconds
Started Apr 30 03:02:09 PM PDT 24
Finished Apr 30 03:02:13 PM PDT 24
Peak memory 201472 kb
Host smart-a78a3ddb-7875-4da8-8d39-b04371f2bd9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393957242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.1393957242
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1945143225
Short name T61
Test name
Test status
Simulation time 555861688 ps
CPU time 3.36 seconds
Started Apr 30 03:02:26 PM PDT 24
Finished Apr 30 03:02:30 PM PDT 24
Peak memory 201436 kb
Host smart-9e69f843-79bf-4c4b-ac07-45a96483335d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945143225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1945143225
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2018204557
Short name T887
Test name
Test status
Simulation time 8559921483 ps
CPU time 3.45 seconds
Started Apr 30 03:02:09 PM PDT 24
Finished Apr 30 03:02:13 PM PDT 24
Peak memory 201512 kb
Host smart-d506a039-853c-48fb-82eb-35120d6de198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018204557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2018204557
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1586460054
Short name T900
Test name
Test status
Simulation time 389866196 ps
CPU time 1.29 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:17 PM PDT 24
Peak memory 201260 kb
Host smart-3f55e92b-fa8c-448d-aae5-9f03d3ce9d7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586460054 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1586460054
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.616817508
Short name T130
Test name
Test status
Simulation time 540378070 ps
CPU time 1.9 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201224 kb
Host smart-c9c78b5f-2f72-4854-9fef-edc428d4bdb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616817508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.616817508
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.370841504
Short name T868
Test name
Test status
Simulation time 400779587 ps
CPU time 0.8 seconds
Started Apr 30 03:02:12 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 201188 kb
Host smart-946f0733-8e5d-4b3c-b757-b6e5df3b2d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370841504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.370841504
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3712498542
Short name T50
Test name
Test status
Simulation time 4239813280 ps
CPU time 8.66 seconds
Started Apr 30 03:02:32 PM PDT 24
Finished Apr 30 03:02:41 PM PDT 24
Peak memory 201540 kb
Host smart-508d84de-a5ff-4ffc-95fc-2355f7ae2344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712498542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3712498542
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.754865162
Short name T846
Test name
Test status
Simulation time 404288322 ps
CPU time 2.66 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:15 PM PDT 24
Peak memory 209600 kb
Host smart-b76525dd-498b-42ff-9357-76357cbf2910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754865162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.754865162
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2675537563
Short name T807
Test name
Test status
Simulation time 4658394332 ps
CPU time 4.16 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:21 PM PDT 24
Peak memory 201492 kb
Host smart-54f82708-0c18-4f66-9181-372cc3446b14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675537563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2675537563
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.618408619
Short name T888
Test name
Test status
Simulation time 689968801 ps
CPU time 1.07 seconds
Started Apr 30 03:02:21 PM PDT 24
Finished Apr 30 03:02:23 PM PDT 24
Peak memory 201272 kb
Host smart-fe62e944-c657-4b8d-8e69-98fcd25e773c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618408619 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.618408619
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4119240204
Short name T915
Test name
Test status
Simulation time 360020896 ps
CPU time 0.94 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:18 PM PDT 24
Peak memory 201212 kb
Host smart-cce592bb-3695-4fde-9929-85bc84e83b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119240204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4119240204
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1898537438
Short name T826
Test name
Test status
Simulation time 451578543 ps
CPU time 0.72 seconds
Started Apr 30 03:02:11 PM PDT 24
Finished Apr 30 03:02:13 PM PDT 24
Peak memory 201176 kb
Host smart-7ee593c6-56b6-4093-a96c-2818cd28efea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898537438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1898537438
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.916739308
Short name T914
Test name
Test status
Simulation time 3421032044 ps
CPU time 2.02 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201444 kb
Host smart-6177a5e3-1f8e-4bc8-8b11-8f8891bf37cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916739308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.916739308
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.1172385275
Short name T829
Test name
Test status
Simulation time 847244128 ps
CPU time 2.57 seconds
Started Apr 30 03:02:14 PM PDT 24
Finished Apr 30 03:02:22 PM PDT 24
Peak memory 217628 kb
Host smart-265b58aa-7b86-4c06-ba4a-eee6098f9974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172385275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.1172385275
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2105027856
Short name T69
Test name
Test status
Simulation time 8053268693 ps
CPU time 7.27 seconds
Started Apr 30 03:02:25 PM PDT 24
Finished Apr 30 03:02:33 PM PDT 24
Peak memory 201456 kb
Host smart-62d9eac1-b4ff-41c7-ba1a-9bfc9cd010aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105027856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2105027856
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2771722624
Short name T705
Test name
Test status
Simulation time 397082960 ps
CPU time 1.42 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:02:48 PM PDT 24
Peak memory 201968 kb
Host smart-f18e9bd5-1dd9-4bef-80c3-509512c4e7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771722624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2771722624
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.4055576951
Short name T727
Test name
Test status
Simulation time 502378705877 ps
CPU time 1260.73 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:23:17 PM PDT 24
Peak memory 202260 kb
Host smart-d9e69b2b-d974-49c9-a1ab-05bef7f7ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055576951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.4055576951
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1915234148
Short name T668
Test name
Test status
Simulation time 324112552591 ps
CPU time 188.56 seconds
Started Apr 30 03:02:35 PM PDT 24
Finished Apr 30 03:05:44 PM PDT 24
Peak memory 202236 kb
Host smart-88a114d1-b73d-49e7-9187-fb4f3a6bfdc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915234148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1915234148
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.709716519
Short name T142
Test name
Test status
Simulation time 486783971711 ps
CPU time 266.03 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:06:43 PM PDT 24
Peak memory 201552 kb
Host smart-17f8bd2c-05b9-499b-8068-c1e26d507192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709716519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.709716519
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3851239092
Short name T511
Test name
Test status
Simulation time 162025077524 ps
CPU time 342.23 seconds
Started Apr 30 03:02:17 PM PDT 24
Finished Apr 30 03:08:00 PM PDT 24
Peak memory 202184 kb
Host smart-4895793a-4dc5-4a96-bf3e-d5b097c9263b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851239092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3851239092
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3300256766
Short name T749
Test name
Test status
Simulation time 568798144055 ps
CPU time 304.29 seconds
Started Apr 30 03:02:16 PM PDT 24
Finished Apr 30 03:07:22 PM PDT 24
Peak memory 202212 kb
Host smart-52dd48ff-60ea-4211-b6a4-d55c38bca164
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300256766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3300256766
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.307951242
Short name T527
Test name
Test status
Simulation time 191362210033 ps
CPU time 32.03 seconds
Started Apr 30 03:02:23 PM PDT 24
Finished Apr 30 03:02:55 PM PDT 24
Peak memory 202304 kb
Host smart-a438ed9d-5579-49d5-95db-8ea7ef31f647
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307951242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.307951242
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3701917758
Short name T520
Test name
Test status
Simulation time 116706602896 ps
CPU time 416.68 seconds
Started Apr 30 03:02:43 PM PDT 24
Finished Apr 30 03:09:40 PM PDT 24
Peak memory 202688 kb
Host smart-58c8de83-e9f9-4123-9898-b24988ce2527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701917758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3701917758
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1060856200
Short name T513
Test name
Test status
Simulation time 29077162357 ps
CPU time 69.2 seconds
Started Apr 30 03:02:42 PM PDT 24
Finished Apr 30 03:03:52 PM PDT 24
Peak memory 202064 kb
Host smart-519f58c4-aab5-4e24-8533-5e3d87bec95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060856200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1060856200
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1270212745
Short name T772
Test name
Test status
Simulation time 3300888432 ps
CPU time 4.19 seconds
Started Apr 30 03:02:40 PM PDT 24
Finished Apr 30 03:02:45 PM PDT 24
Peak memory 202136 kb
Host smart-dffc1613-48a7-4d96-9238-6d46cb395985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270212745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1270212745
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.2026311396
Short name T381
Test name
Test status
Simulation time 6036960692 ps
CPU time 3.76 seconds
Started Apr 30 03:02:15 PM PDT 24
Finished Apr 30 03:02:20 PM PDT 24
Peak memory 201304 kb
Host smart-75d4a6c1-bdfe-433d-8787-44552fb98cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026311396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.2026311396
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.881073652
Short name T228
Test name
Test status
Simulation time 167983712665 ps
CPU time 186.28 seconds
Started Apr 30 03:02:43 PM PDT 24
Finished Apr 30 03:05:50 PM PDT 24
Peak memory 202320 kb
Host smart-a20c7d7f-95c7-4980-a61d-802b9d3ccf70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881073652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.881073652
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3973173518
Short name T456
Test name
Test status
Simulation time 408419416 ps
CPU time 1.52 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:02:47 PM PDT 24
Peak memory 201928 kb
Host smart-30efc4b4-5b4a-464f-b6ff-dc581c1c5636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973173518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3973173518
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2416745365
Short name T223
Test name
Test status
Simulation time 202735917509 ps
CPU time 475.85 seconds
Started Apr 30 03:02:40 PM PDT 24
Finished Apr 30 03:10:36 PM PDT 24
Peak memory 202152 kb
Host smart-e13c0320-dff2-4756-a7b7-7093db367888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416745365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2416745365
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1475744329
Short name T105
Test name
Test status
Simulation time 486832500804 ps
CPU time 1060.03 seconds
Started Apr 30 03:02:41 PM PDT 24
Finished Apr 30 03:20:21 PM PDT 24
Peak memory 202316 kb
Host smart-a86424a9-5b23-405b-9132-9ab151d65a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475744329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1475744329
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2095883300
Short name T486
Test name
Test status
Simulation time 502799621262 ps
CPU time 900.68 seconds
Started Apr 30 03:02:44 PM PDT 24
Finished Apr 30 03:17:45 PM PDT 24
Peak memory 202268 kb
Host smart-4a6846bc-3bed-4557-bf82-b2f67b700e6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095883300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2095883300
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.4165953022
Short name T225
Test name
Test status
Simulation time 497534899846 ps
CPU time 962.61 seconds
Started Apr 30 03:02:41 PM PDT 24
Finished Apr 30 03:18:44 PM PDT 24
Peak memory 202332 kb
Host smart-ddec9941-9ab8-4f69-be30-de7d7a68c7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165953022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.4165953022
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1013581412
Short name T706
Test name
Test status
Simulation time 325685620818 ps
CPU time 276.03 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:07:15 PM PDT 24
Peak memory 202264 kb
Host smart-99b50b3f-12a8-4ca3-8637-55d113063a5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013581412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1013581412
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3570381560
Short name T245
Test name
Test status
Simulation time 341915776211 ps
CPU time 697.56 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:14:24 PM PDT 24
Peak memory 202324 kb
Host smart-f1c8be81-d8f8-4ccd-b02d-535d07c6fb23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570381560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3570381560
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.3069493445
Short name T424
Test name
Test status
Simulation time 212580975592 ps
CPU time 102.23 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:04:29 PM PDT 24
Peak memory 202248 kb
Host smart-38acc016-2235-4688-8003-e6b5def25d4d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069493445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.3069493445
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1232897759
Short name T47
Test name
Test status
Simulation time 121672872949 ps
CPU time 429.42 seconds
Started Apr 30 03:02:41 PM PDT 24
Finished Apr 30 03:09:51 PM PDT 24
Peak memory 202648 kb
Host smart-29da7656-420b-464f-8f34-523ad91450ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232897759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1232897759
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.758839969
Short name T661
Test name
Test status
Simulation time 26892822385 ps
CPU time 34.34 seconds
Started Apr 30 03:02:36 PM PDT 24
Finished Apr 30 03:03:11 PM PDT 24
Peak memory 202072 kb
Host smart-294151b6-aa60-41f1-9b84-66566d303c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758839969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.758839969
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2268668396
Short name T378
Test name
Test status
Simulation time 4770861047 ps
CPU time 3.53 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:02:43 PM PDT 24
Peak memory 202068 kb
Host smart-ecb86a45-083e-419e-81aa-c89cacda74c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268668396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2268668396
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.482798782
Short name T78
Test name
Test status
Simulation time 4223141149 ps
CPU time 3.11 seconds
Started Apr 30 03:02:43 PM PDT 24
Finished Apr 30 03:02:46 PM PDT 24
Peak memory 217960 kb
Host smart-ead21072-8ac4-4d47-af34-560c62373aa1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482798782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.482798782
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4114037281
Short name T631
Test name
Test status
Simulation time 5911478723 ps
CPU time 3.96 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:02:49 PM PDT 24
Peak memory 202136 kb
Host smart-e0608984-817a-4d9f-963c-7fbf860c1b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114037281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4114037281
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3898870158
Short name T14
Test name
Test status
Simulation time 63110363563 ps
CPU time 61.58 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:03:41 PM PDT 24
Peak memory 202328 kb
Host smart-13c3b2ed-3aab-4e6b-8fa6-095f430eaea2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898870158 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3898870158
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1551540138
Short name T773
Test name
Test status
Simulation time 175615223860 ps
CPU time 442.24 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:10:18 PM PDT 24
Peak memory 202240 kb
Host smart-7a5818f4-4e95-4a81-a059-95248282267d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551540138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1551540138
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1364634944
Short name T344
Test name
Test status
Simulation time 486954907753 ps
CPU time 1070.41 seconds
Started Apr 30 03:02:52 PM PDT 24
Finished Apr 30 03:20:43 PM PDT 24
Peak memory 202324 kb
Host smart-797bbe52-170a-4132-b7c7-3ff6e32931d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364634944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1364634944
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1719770937
Short name T189
Test name
Test status
Simulation time 492342408298 ps
CPU time 607.6 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:12:59 PM PDT 24
Peak memory 202244 kb
Host smart-14fde3a8-abbf-4c18-bbfa-1d81ec7b921b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719770937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1719770937
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.656368475
Short name T732
Test name
Test status
Simulation time 326146629976 ps
CPU time 747.25 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:15:29 PM PDT 24
Peak memory 202380 kb
Host smart-5927566c-1210-4e9c-ba7d-0314f0fd7e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656368475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.656368475
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.174689443
Short name T685
Test name
Test status
Simulation time 163962801843 ps
CPU time 70.68 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:04:11 PM PDT 24
Peak memory 202264 kb
Host smart-3284d5a2-4b6f-4591-8341-746934d8a30b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=174689443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.174689443
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.2042419219
Short name T479
Test name
Test status
Simulation time 609704108596 ps
CPU time 374.16 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:09:13 PM PDT 24
Peak memory 202284 kb
Host smart-7fabe83d-53b2-4114-9e72-866cd41f5856
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042419219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.2042419219
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3483435389
Short name T687
Test name
Test status
Simulation time 83963091130 ps
CPU time 437.06 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:10:11 PM PDT 24
Peak memory 202668 kb
Host smart-ca366096-84d2-4857-b32b-ad60a052673f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483435389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3483435389
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.4023100718
Short name T370
Test name
Test status
Simulation time 43394494709 ps
CPU time 89.19 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:04:26 PM PDT 24
Peak memory 202136 kb
Host smart-8092d1b9-0e53-4437-8363-adde23a19780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023100718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.4023100718
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1349044005
Short name T700
Test name
Test status
Simulation time 4871096505 ps
CPU time 12.49 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:03:16 PM PDT 24
Peak memory 202112 kb
Host smart-5c8ac395-d321-4378-bfd0-6a5d51b2b0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349044005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1349044005
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3531117959
Short name T708
Test name
Test status
Simulation time 5694679521 ps
CPU time 2.89 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:03:02 PM PDT 24
Peak memory 202072 kb
Host smart-00dedd6c-8631-49a6-9ba5-3b63a63c4765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531117959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3531117959
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2721903279
Short name T545
Test name
Test status
Simulation time 227327417926 ps
CPU time 141.04 seconds
Started Apr 30 03:03:05 PM PDT 24
Finished Apr 30 03:05:27 PM PDT 24
Peak memory 202400 kb
Host smart-929df49b-ac6d-4ce4-bba7-bea3d25ea176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721903279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2721903279
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.362528419
Short name T207
Test name
Test status
Simulation time 14762379705 ps
CPU time 59.88 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:03:54 PM PDT 24
Peak memory 211004 kb
Host smart-d3caa66c-f270-4076-94dc-653cd97d1257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362528419 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.362528419
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.4280766168
Short name T783
Test name
Test status
Simulation time 374045194 ps
CPU time 1.03 seconds
Started Apr 30 03:02:56 PM PDT 24
Finished Apr 30 03:02:57 PM PDT 24
Peak memory 201980 kb
Host smart-1052173a-cf86-4ae2-83bc-bd08e6fcff1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280766168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.4280766168
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3627829188
Short name T524
Test name
Test status
Simulation time 344320843467 ps
CPU time 443.74 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:10:19 PM PDT 24
Peak memory 202276 kb
Host smart-169f1968-ec27-4f81-87e8-3b65144c7c2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627829188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3627829188
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.172563667
Short name T32
Test name
Test status
Simulation time 164278100042 ps
CPU time 378.33 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:09:22 PM PDT 24
Peak memory 201928 kb
Host smart-e765ad31-7636-4701-aa68-3d40d5683018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172563667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.172563667
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1051139090
Short name T594
Test name
Test status
Simulation time 165191177414 ps
CPU time 337.26 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:08:41 PM PDT 24
Peak memory 202324 kb
Host smart-882745f6-5840-469a-a095-11ef1a22c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051139090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1051139090
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2200667606
Short name T488
Test name
Test status
Simulation time 331789842489 ps
CPU time 762.61 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:15:45 PM PDT 24
Peak memory 202304 kb
Host smart-cd3eb6f4-15d5-4c72-a59a-7a0c51879a1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200667606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2200667606
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1532412505
Short name T323
Test name
Test status
Simulation time 166736919503 ps
CPU time 204.83 seconds
Started Apr 30 03:02:56 PM PDT 24
Finished Apr 30 03:06:21 PM PDT 24
Peak memory 202304 kb
Host smart-e35cddcf-178d-4c96-baf1-282db28e0f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532412505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1532412505
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1671906185
Short name T584
Test name
Test status
Simulation time 166449621536 ps
CPU time 93.3 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:04:37 PM PDT 24
Peak memory 202224 kb
Host smart-7bd2e1c6-e0ae-40b9-b713-7f220c4b2e2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671906185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1671906185
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.92570011
Short name T188
Test name
Test status
Simulation time 550897010260 ps
CPU time 324.34 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:08:31 PM PDT 24
Peak memory 202368 kb
Host smart-0f63600b-05af-467c-b92a-05b29614100b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92570011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_w
akeup.92570011
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2276820244
Short name T674
Test name
Test status
Simulation time 199801820521 ps
CPU time 35.52 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:03:47 PM PDT 24
Peak memory 202264 kb
Host smart-46348b03-f007-45ec-8bdc-eb4c927dc3c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276820244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2276820244
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.4237881956
Short name T216
Test name
Test status
Simulation time 105918631135 ps
CPU time 359.42 seconds
Started Apr 30 03:02:52 PM PDT 24
Finished Apr 30 03:08:52 PM PDT 24
Peak memory 202684 kb
Host smart-549a8ca9-b445-422a-8c61-31a3abe6b66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237881956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.4237881956
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1069835407
Short name T784
Test name
Test status
Simulation time 29397647072 ps
CPU time 63.77 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:04:07 PM PDT 24
Peak memory 201892 kb
Host smart-ab518826-b87b-4b69-a95c-ee6056f7b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069835407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1069835407
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2943933137
Short name T599
Test name
Test status
Simulation time 3182197815 ps
CPU time 7.16 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:03:15 PM PDT 24
Peak memory 202116 kb
Host smart-d6f64e1c-8d33-4f2e-ac18-057e53bc5c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943933137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2943933137
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.843911878
Short name T368
Test name
Test status
Simulation time 5932513619 ps
CPU time 4.44 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:03:07 PM PDT 24
Peak memory 202152 kb
Host smart-199f9a66-f3bb-48a1-85e1-3127759e48c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843911878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.843911878
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2586605528
Short name T634
Test name
Test status
Simulation time 196261451047 ps
CPU time 410.06 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:09:48 PM PDT 24
Peak memory 211400 kb
Host smart-5efd40ba-7f82-45ea-9e60-3b9920a78730
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586605528 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2586605528
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1317037026
Short name T445
Test name
Test status
Simulation time 488004840 ps
CPU time 1.83 seconds
Started Apr 30 03:03:18 PM PDT 24
Finished Apr 30 03:03:20 PM PDT 24
Peak memory 202024 kb
Host smart-26075d6a-012a-41e8-9581-dd7aeb979077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317037026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1317037026
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2696770145
Short name T703
Test name
Test status
Simulation time 180345732805 ps
CPU time 11.31 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:03:04 PM PDT 24
Peak memory 202280 kb
Host smart-bdd31356-4cca-4656-96d8-fdb9deac020d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696770145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2696770145
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.977716557
Short name T277
Test name
Test status
Simulation time 497954555364 ps
CPU time 610.97 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:13:10 PM PDT 24
Peak memory 202252 kb
Host smart-d5581d46-92d7-4328-8294-2458099fa0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977716557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.977716557
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3797108001
Short name T714
Test name
Test status
Simulation time 336294905603 ps
CPU time 784.68 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:16:03 PM PDT 24
Peak memory 202308 kb
Host smart-cd074e9d-9ddd-49fe-bfa3-1b05c0936c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797108001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3797108001
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1292259862
Short name T200
Test name
Test status
Simulation time 482015341369 ps
CPU time 870.92 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:17:32 PM PDT 24
Peak memory 202280 kb
Host smart-76ef4d44-4d2c-4a2e-8c06-17eecefd61aa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292259862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1292259862
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3496920571
Short name T517
Test name
Test status
Simulation time 166506512001 ps
CPU time 105.48 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:04:40 PM PDT 24
Peak memory 202344 kb
Host smart-b58a692d-15bc-4d86-a6c4-ea3469c29c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496920571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3496920571
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3857677895
Short name T731
Test name
Test status
Simulation time 488270246872 ps
CPU time 1171.9 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:22:35 PM PDT 24
Peak memory 202320 kb
Host smart-7053864a-75d0-4386-962f-5b62583ee521
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857677895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3857677895
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.63744813
Short name T595
Test name
Test status
Simulation time 171380821768 ps
CPU time 160.19 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:05:39 PM PDT 24
Peak memory 202380 kb
Host smart-9e2af11d-8228-4f22-899b-00f86776255c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63744813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_w
akeup.63744813
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.4252191090
Short name T79
Test name
Test status
Simulation time 200761253890 ps
CPU time 119.77 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:05:03 PM PDT 24
Peak memory 202336 kb
Host smart-3a4a7ce8-0831-4850-88e9-8525736dcf35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252191090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.4252191090
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2686731314
Short name T496
Test name
Test status
Simulation time 103594584770 ps
CPU time 570.66 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:12:39 PM PDT 24
Peak memory 202724 kb
Host smart-009b01e5-74dc-4d8b-99a6-1d8940ac5863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686731314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2686731314
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3758646156
Short name T611
Test name
Test status
Simulation time 31671238079 ps
CPU time 14.33 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:03:22 PM PDT 24
Peak memory 202120 kb
Host smart-53692e15-958a-44f4-bd0e-00e7a94870fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758646156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3758646156
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3138021880
Short name T25
Test name
Test status
Simulation time 3118398474 ps
CPU time 2.53 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:02:57 PM PDT 24
Peak memory 202072 kb
Host smart-243a3ef8-d0a6-4be9-8086-c6fde6176988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138021880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3138021880
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.106927269
Short name T639
Test name
Test status
Simulation time 5660550291 ps
CPU time 10.18 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:03:08 PM PDT 24
Peak memory 202056 kb
Host smart-ccbe9fb8-e9c2-49c2-b35d-8c656dd96a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106927269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.106927269
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2599111569
Short name T20
Test name
Test status
Simulation time 298184290857 ps
CPU time 628.29 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:13:32 PM PDT 24
Peak memory 210640 kb
Host smart-4e26195b-7a80-418a-bb52-3b097aea1249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599111569 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2599111569
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.1837554394
Short name T183
Test name
Test status
Simulation time 357032773 ps
CPU time 0.87 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 202056 kb
Host smart-5c9725b3-4877-4a16-8320-69061ee47c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837554394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.1837554394
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3892999217
Short name T96
Test name
Test status
Simulation time 167805572668 ps
CPU time 396.64 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:09:40 PM PDT 24
Peak memory 202288 kb
Host smart-9d6cd619-621b-478b-becf-665f42fc20f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892999217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3892999217
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4151300638
Short name T80
Test name
Test status
Simulation time 494690093763 ps
CPU time 307.75 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:08:06 PM PDT 24
Peak memory 202320 kb
Host smart-621f3354-d4bf-42db-9410-e518200d37f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151300638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4151300638
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.943984290
Short name T590
Test name
Test status
Simulation time 330793141420 ps
CPU time 371.03 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:09:13 PM PDT 24
Peak memory 202272 kb
Host smart-b1b4d220-4cd8-4204-a2d4-4db541fb1efa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943984290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.943984290
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.4215082865
Short name T341
Test name
Test status
Simulation time 487567258448 ps
CPU time 600.52 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:12:56 PM PDT 24
Peak memory 202260 kb
Host smart-95bb4ad6-40cd-40ef-aaef-9ca282791c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215082865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.4215082865
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.430711242
Short name T422
Test name
Test status
Simulation time 164491455279 ps
CPU time 39.96 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:03:38 PM PDT 24
Peak memory 202212 kb
Host smart-ad2386e5-a711-4642-8443-9f26a2af69ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=430711242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.430711242
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.2085401088
Short name T107
Test name
Test status
Simulation time 243265131586 ps
CPU time 566.98 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:12:26 PM PDT 24
Peak memory 202344 kb
Host smart-78b87436-3c94-4dc0-a6d3-55085da97612
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085401088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.2085401088
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2557468450
Short name T788
Test name
Test status
Simulation time 384087101089 ps
CPU time 199.29 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:06:20 PM PDT 24
Peak memory 202264 kb
Host smart-3ad5f2fa-a4bc-4fa2-bf55-89dfdcb93ef8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557468450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2557468450
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2931648534
Short name T177
Test name
Test status
Simulation time 86475954109 ps
CPU time 266.98 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:07:38 PM PDT 24
Peak memory 202688 kb
Host smart-9dc7ca02-dbc4-49fc-a806-6abd32662e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931648534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2931648534
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3638571075
Short name T42
Test name
Test status
Simulation time 46143000401 ps
CPU time 28.04 seconds
Started Apr 30 03:03:09 PM PDT 24
Finished Apr 30 03:03:39 PM PDT 24
Peak memory 202116 kb
Host smart-592284db-ef32-4cc3-a36c-b37a3eee7dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638571075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3638571075
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.485362581
Short name T609
Test name
Test status
Simulation time 4398566857 ps
CPU time 1.57 seconds
Started Apr 30 03:03:20 PM PDT 24
Finished Apr 30 03:03:22 PM PDT 24
Peak memory 202156 kb
Host smart-a2c05ffc-9c64-4f7e-89b7-aaab75fa096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485362581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.485362581
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3320856403
Short name T547
Test name
Test status
Simulation time 5922807838 ps
CPU time 4.96 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 202112 kb
Host smart-3e2ed948-44bf-4b06-9c43-9698f3f023a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320856403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3320856403
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.4139797692
Short name T736
Test name
Test status
Simulation time 238002861218 ps
CPU time 506.4 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:11:51 PM PDT 24
Peak memory 202396 kb
Host smart-841f734a-7c8b-4c67-b18a-593c3bd618de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139797692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.4139797692
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1995846185
Short name T762
Test name
Test status
Simulation time 10194148893 ps
CPU time 9.54 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 211600 kb
Host smart-616ec51d-5f7e-4e57-a5bc-7cc779d8767e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995846185 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1995846185
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4155799259
Short name T405
Test name
Test status
Simulation time 335763669 ps
CPU time 0.85 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:03:04 PM PDT 24
Peak memory 202000 kb
Host smart-7716000c-7d78-42f4-bd6c-b37c223c118d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155799259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4155799259
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2447030840
Short name T133
Test name
Test status
Simulation time 160658634048 ps
CPU time 404.28 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:09:52 PM PDT 24
Peak memory 202300 kb
Host smart-4f937bd8-0c43-4ba4-a4e3-89c26402aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447030840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2447030840
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.994495360
Short name T12
Test name
Test status
Simulation time 498143441622 ps
CPU time 455.19 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:10:36 PM PDT 24
Peak memory 202284 kb
Host smart-6b1257af-5ef0-437b-9360-ca01446ab2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994495360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.994495360
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2739717743
Short name T680
Test name
Test status
Simulation time 325223545261 ps
CPU time 405.21 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:09:41 PM PDT 24
Peak memory 202240 kb
Host smart-87d0ed5a-8879-4a4e-a54f-7ca77017caae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739717743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2739717743
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3774539603
Short name T448
Test name
Test status
Simulation time 162301972224 ps
CPU time 331.94 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:08:39 PM PDT 24
Peak memory 202320 kb
Host smart-44813cb9-6c09-489c-bd28-9a05984ecc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774539603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3774539603
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.168482310
Short name T398
Test name
Test status
Simulation time 491625341154 ps
CPU time 243.27 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:07:07 PM PDT 24
Peak memory 202404 kb
Host smart-2ce41fe9-763a-4244-b786-18614bdcb136
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=168482310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.168482310
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2571030327
Short name T734
Test name
Test status
Simulation time 186427122666 ps
CPU time 73.65 seconds
Started Apr 30 03:03:08 PM PDT 24
Finished Apr 30 03:04:22 PM PDT 24
Peak memory 202296 kb
Host smart-c2bd625b-880c-4272-9acc-839e13c4a613
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571030327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2571030327
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3567144945
Short name T612
Test name
Test status
Simulation time 617264984563 ps
CPU time 118.55 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:05:02 PM PDT 24
Peak memory 202148 kb
Host smart-7280a216-66d8-4814-ba17-010aeb8229dc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567144945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3567144945
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3358519741
Short name T567
Test name
Test status
Simulation time 63073802773 ps
CPU time 364.1 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:09:04 PM PDT 24
Peak memory 202596 kb
Host smart-d6aa51f2-4230-4966-97be-a4869c4a0f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358519741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3358519741
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2433578913
Short name T591
Test name
Test status
Simulation time 26905704358 ps
CPU time 18.87 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:03:21 PM PDT 24
Peak memory 202072 kb
Host smart-6d70de6c-9923-4d0c-bafd-9abf22a961ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433578913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2433578913
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2085073846
Short name T725
Test name
Test status
Simulation time 3271871939 ps
CPU time 8.71 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:03:04 PM PDT 24
Peak memory 202104 kb
Host smart-0b4e088b-889c-434a-9865-91c9c5618d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085073846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2085073846
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1976964099
Short name T760
Test name
Test status
Simulation time 5718889975 ps
CPU time 14.1 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:03:14 PM PDT 24
Peak memory 202060 kb
Host smart-aadad3bf-f44c-4267-a11a-47a4e93383b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976964099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1976964099
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.243377715
Short name T795
Test name
Test status
Simulation time 194469891745 ps
CPU time 607.86 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:13:11 PM PDT 24
Peak memory 202880 kb
Host smart-5d1267b1-6fd0-43f4-b13f-ad4ad254496f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243377715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
243377715
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3549978328
Short name T695
Test name
Test status
Simulation time 73978284927 ps
CPU time 98.05 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:04:41 PM PDT 24
Peak memory 210484 kb
Host smart-52a7d7f6-e209-4388-b56d-59c09cd40484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549978328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3549978328
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.4080976751
Short name T429
Test name
Test status
Simulation time 327395418 ps
CPU time 0.73 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:03:09 PM PDT 24
Peak memory 201960 kb
Host smart-7570406a-9fd1-48e5-85e8-f3190b35bece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080976751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.4080976751
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2730132732
Short name T627
Test name
Test status
Simulation time 330937155151 ps
CPU time 129.32 seconds
Started Apr 30 03:03:16 PM PDT 24
Finished Apr 30 03:05:26 PM PDT 24
Peak memory 202268 kb
Host smart-d11eac50-9c54-4dd1-811a-cc484684faa9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730132732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2730132732
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.3193121024
Short name T314
Test name
Test status
Simulation time 323012333554 ps
CPU time 392.1 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:09:30 PM PDT 24
Peak memory 202244 kb
Host smart-5f998de1-c2b1-40f8-973b-3a07f9d1c086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193121024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.3193121024
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4007308482
Short name T704
Test name
Test status
Simulation time 486456944342 ps
CPU time 238.81 seconds
Started Apr 30 03:03:08 PM PDT 24
Finished Apr 30 03:07:08 PM PDT 24
Peak memory 202288 kb
Host smart-19e039ce-44c2-41d5-bf36-a7b6ee257458
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007308482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4007308482
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.61488472
Short name T460
Test name
Test status
Simulation time 485470722327 ps
CPU time 291.38 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:07:55 PM PDT 24
Peak memory 202276 kb
Host smart-b72a86ea-5277-4306-869a-cc2f8e4ad705
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=61488472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixed
.61488472
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.122682748
Short name T9
Test name
Test status
Simulation time 177735431876 ps
CPU time 51.5 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:04:00 PM PDT 24
Peak memory 202592 kb
Host smart-91f3c744-20fe-4f71-b228-e67c286935d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122682748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.122682748
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3506805235
Short name T780
Test name
Test status
Simulation time 196954045690 ps
CPU time 218.85 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:06:36 PM PDT 24
Peak memory 202224 kb
Host smart-c92369e5-41b2-4b6c-b368-5478f8cb99e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506805235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3506805235
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3405278204
Short name T694
Test name
Test status
Simulation time 84109005202 ps
CPU time 420.94 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:10:09 PM PDT 24
Peak memory 202724 kb
Host smart-8d834a44-81b6-4ea0-9590-7513f462123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405278204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3405278204
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.2995730726
Short name T521
Test name
Test status
Simulation time 45823574916 ps
CPU time 111.88 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:04:56 PM PDT 24
Peak memory 202060 kb
Host smart-13345b2c-2c97-4738-b201-a561408420fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995730726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.2995730726
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1671723459
Short name T575
Test name
Test status
Simulation time 4691713406 ps
CPU time 10.92 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:03:18 PM PDT 24
Peak memory 202108 kb
Host smart-9daa4e50-4701-44ea-a7ce-7eadad18ea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671723459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1671723459
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3638273000
Short name T205
Test name
Test status
Simulation time 5595014404 ps
CPU time 15.48 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:03:13 PM PDT 24
Peak memory 202128 kb
Host smart-40cdc3d3-b26d-4a5d-a730-e38c9f6a6a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638273000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3638273000
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4134252099
Short name T667
Test name
Test status
Simulation time 30810628130 ps
CPU time 123.73 seconds
Started Apr 30 03:03:17 PM PDT 24
Finished Apr 30 03:05:21 PM PDT 24
Peak memory 211040 kb
Host smart-089e0003-5321-4003-b46c-ca532be52782
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134252099 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4134252099
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.209805817
Short name T447
Test name
Test status
Simulation time 419282057 ps
CPU time 1.05 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:03:01 PM PDT 24
Peak memory 202000 kb
Host smart-fe116ce2-8e56-4a52-9899-6bba438e2c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209805817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.209805817
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3474445491
Short name T272
Test name
Test status
Simulation time 163982281478 ps
CPU time 87.62 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:04:41 PM PDT 24
Peak memory 202296 kb
Host smart-2510f1bd-7ff1-4b48-acd9-6cd35ed8ce3e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474445491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3474445491
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.709246385
Short name T233
Test name
Test status
Simulation time 489647113758 ps
CPU time 1140.61 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:21:54 PM PDT 24
Peak memory 202288 kb
Host smart-d14f72b7-8216-4f37-b3fc-ec203282a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709246385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.709246385
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2523970129
Short name T392
Test name
Test status
Simulation time 331620166551 ps
CPU time 744.65 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:15:26 PM PDT 24
Peak memory 202500 kb
Host smart-1d549444-5675-4350-8c8f-34d49cc3abe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523970129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2523970129
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.736882461
Short name T645
Test name
Test status
Simulation time 165829531212 ps
CPU time 91.65 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:04:27 PM PDT 24
Peak memory 202308 kb
Host smart-32e08dca-f31d-4f6e-9723-5dfc7aabdcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736882461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.736882461
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3354905570
Short name T434
Test name
Test status
Simulation time 326726228001 ps
CPU time 414.99 seconds
Started Apr 30 03:03:14 PM PDT 24
Finished Apr 30 03:10:10 PM PDT 24
Peak memory 202340 kb
Host smart-ade336b0-e416-4aa6-8ddf-e0a30aa5b7e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354905570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3354905570
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3440889078
Short name T191
Test name
Test status
Simulation time 429310873031 ps
CPU time 204.08 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:06:31 PM PDT 24
Peak memory 202296 kb
Host smart-ad22562c-4418-4da5-a44f-2b339df6335f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440889078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3440889078
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1326517265
Short name T583
Test name
Test status
Simulation time 598744430403 ps
CPU time 413.45 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:09:55 PM PDT 24
Peak memory 202364 kb
Host smart-fc860733-fcb0-4efc-87a6-cf5b8073d92e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326517265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1326517265
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1238255876
Short name T438
Test name
Test status
Simulation time 34940107998 ps
CPU time 11.44 seconds
Started Apr 30 03:03:18 PM PDT 24
Finished Apr 30 03:03:30 PM PDT 24
Peak memory 202080 kb
Host smart-5e3c6637-ba33-43c2-b55b-cb73edf82715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238255876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1238255876
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2583636849
Short name T399
Test name
Test status
Simulation time 4495129849 ps
CPU time 3.29 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:03:03 PM PDT 24
Peak memory 202092 kb
Host smart-eb512f0b-2367-4df6-b23a-70018c9dd4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583636849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2583636849
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1575937397
Short name T523
Test name
Test status
Simulation time 5740917555 ps
CPU time 13.58 seconds
Started Apr 30 03:03:15 PM PDT 24
Finished Apr 30 03:03:30 PM PDT 24
Peak memory 202096 kb
Host smart-90b5b076-495e-4288-b877-ea7858d4790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575937397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1575937397
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3732508756
Short name T510
Test name
Test status
Simulation time 71877256262 ps
CPU time 262.91 seconds
Started Apr 30 03:03:04 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 210840 kb
Host smart-5a361941-8111-43b9-b315-03949253ec0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732508756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3732508756
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1473129692
Short name T18
Test name
Test status
Simulation time 135178306125 ps
CPU time 442.12 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:10:27 PM PDT 24
Peak memory 219200 kb
Host smart-f45b7c05-0a37-4b13-b5d7-69a21b501e5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473129692 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1473129692
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.496281474
Short name T472
Test name
Test status
Simulation time 488593998 ps
CPU time 1.66 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 202024 kb
Host smart-5fbea0ee-3a40-4985-bb02-3cfd7294fe36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496281474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.496281474
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.4090233752
Short name T230
Test name
Test status
Simulation time 367217410835 ps
CPU time 389.82 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:09:33 PM PDT 24
Peak memory 202328 kb
Host smart-b769a1a3-5230-435d-9b87-7697c2c226fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090233752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.4090233752
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2265760932
Short name T571
Test name
Test status
Simulation time 164584753799 ps
CPU time 30.28 seconds
Started Apr 30 03:03:08 PM PDT 24
Finished Apr 30 03:03:39 PM PDT 24
Peak memory 202384 kb
Host smart-90950575-4b11-4a3a-b702-dad609e8941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265760932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2265760932
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1908507033
Short name T525
Test name
Test status
Simulation time 329540206649 ps
CPU time 742.72 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:15:27 PM PDT 24
Peak memory 202180 kb
Host smart-060f0bde-2aa5-43cc-a0dc-1c6527805146
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908507033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1908507033
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2885609033
Short name T264
Test name
Test status
Simulation time 492826102109 ps
CPU time 299.14 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:08:03 PM PDT 24
Peak memory 202248 kb
Host smart-01901c51-7b40-4154-9358-1167140ca465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885609033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2885609033
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2801055893
Short name T516
Test name
Test status
Simulation time 165172691075 ps
CPU time 185.78 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:06:07 PM PDT 24
Peak memory 202296 kb
Host smart-c3c5a828-e290-40e1-9c03-de16d76ce64b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801055893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2801055893
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3265902434
Short name T201
Test name
Test status
Simulation time 528751736218 ps
CPU time 343 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:08:46 PM PDT 24
Peak memory 202252 kb
Host smart-208c429b-5221-4bb4-a4d4-bde817d2ceab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265902434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3265902434
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1494250576
Short name T677
Test name
Test status
Simulation time 200064721340 ps
CPU time 242.38 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:07:16 PM PDT 24
Peak memory 202296 kb
Host smart-e39f85fb-3389-4984-aa6e-f560ae26d94e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494250576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1494250576
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4174671711
Short name T363
Test name
Test status
Simulation time 128200887169 ps
CPU time 419.98 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:10:03 PM PDT 24
Peak memory 202624 kb
Host smart-9577eb61-c891-471d-847a-6ccb5dfe373e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174671711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4174671711
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3772610235
Short name T579
Test name
Test status
Simulation time 37990348952 ps
CPU time 23.57 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:03:26 PM PDT 24
Peak memory 202040 kb
Host smart-8cea8a8f-36cc-4b65-9bcb-768ca85eff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772610235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3772610235
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2260204080
Short name T3
Test name
Test status
Simulation time 3530333783 ps
CPU time 9.57 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:03:10 PM PDT 24
Peak memory 202052 kb
Host smart-0db72595-a42c-45c0-9b1e-e9ab2c7e9a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260204080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2260204080
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.974650887
Short name T533
Test name
Test status
Simulation time 6012563867 ps
CPU time 14.11 seconds
Started Apr 30 03:03:12 PM PDT 24
Finished Apr 30 03:03:27 PM PDT 24
Peak memory 202136 kb
Host smart-85486d03-dc81-44ff-a451-a419d11f388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974650887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.974650887
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3779123255
Short name T36
Test name
Test status
Simulation time 169410005824 ps
CPU time 369.08 seconds
Started Apr 30 03:03:10 PM PDT 24
Finished Apr 30 03:09:20 PM PDT 24
Peak memory 202520 kb
Host smart-e1cc92d3-f5b4-4c9c-ae82-0270aa4de23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779123255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3779123255
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1998535554
Short name T691
Test name
Test status
Simulation time 421594459 ps
CPU time 0.71 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 201972 kb
Host smart-ea7606ce-84d4-4b5f-95fa-1ccae1e6d529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998535554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1998535554
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1239494059
Short name T134
Test name
Test status
Simulation time 326771695762 ps
CPU time 66.03 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:04:08 PM PDT 24
Peak memory 202248 kb
Host smart-bb45486d-76d8-4368-9528-2a16537e0588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239494059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1239494059
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3810847968
Short name T550
Test name
Test status
Simulation time 158591632256 ps
CPU time 37.31 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:03:41 PM PDT 24
Peak memory 202292 kb
Host smart-9a0c678b-b4ef-4f4e-a735-f620b5db65b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810847968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3810847968
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.376922664
Short name T461
Test name
Test status
Simulation time 323648658678 ps
CPU time 269.56 seconds
Started Apr 30 03:03:15 PM PDT 24
Finished Apr 30 03:07:46 PM PDT 24
Peak memory 202320 kb
Host smart-b6d9dd0b-958b-4941-8b48-f797ae2a30ac
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=376922664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrup
t_fixed.376922664
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.101879137
Short name T707
Test name
Test status
Simulation time 329509200156 ps
CPU time 103.29 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:04:47 PM PDT 24
Peak memory 202344 kb
Host smart-cfb57315-8f7c-4573-98c3-96d20002629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101879137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.101879137
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.512282538
Short name T557
Test name
Test status
Simulation time 333617392332 ps
CPU time 726.44 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:15:08 PM PDT 24
Peak memory 202260 kb
Host smart-2582d613-396a-46ff-b8e2-f860928b463c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=512282538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.512282538
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1876745265
Short name T738
Test name
Test status
Simulation time 355388819745 ps
CPU time 811.33 seconds
Started Apr 30 03:03:12 PM PDT 24
Finished Apr 30 03:16:44 PM PDT 24
Peak memory 202332 kb
Host smart-f24d517d-2253-468a-a16d-8ce8b21d52d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876745265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1876745265
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3240303106
Short name T689
Test name
Test status
Simulation time 409304977040 ps
CPU time 220.17 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:06:43 PM PDT 24
Peak memory 202308 kb
Host smart-8a566bed-aba9-49b9-987c-e06083c6abff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240303106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3240303106
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2929553831
Short name T209
Test name
Test status
Simulation time 131583762116 ps
CPU time 690.09 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:14:44 PM PDT 24
Peak memory 202700 kb
Host smart-6aa24f5a-2298-4c81-bca0-b1c152e299bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929553831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2929553831
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1461119036
Short name T366
Test name
Test status
Simulation time 30781193048 ps
CPU time 53.14 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:03:56 PM PDT 24
Peak memory 202032 kb
Host smart-5a58bca4-2033-497a-8f12-06d6fb2721b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461119036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1461119036
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1962238624
Short name T515
Test name
Test status
Simulation time 2870042853 ps
CPU time 4 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:03:08 PM PDT 24
Peak memory 202164 kb
Host smart-873683b5-ccd4-45c1-bb71-70608797305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962238624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1962238624
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1055126459
Short name T717
Test name
Test status
Simulation time 5907219848 ps
CPU time 15.9 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:03:17 PM PDT 24
Peak memory 202068 kb
Host smart-71f3aba0-cf1d-4438-8b15-63939e87bbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055126459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1055126459
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3834413316
Short name T577
Test name
Test status
Simulation time 1105151052066 ps
CPU time 2787.39 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:49:28 PM PDT 24
Peak memory 213072 kb
Host smart-4bcd5d1b-ffba-4386-8922-6e10675780e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834413316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3834413316
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2337016751
Short name T408
Test name
Test status
Simulation time 480328757 ps
CPU time 1.14 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:03:03 PM PDT 24
Peak memory 202016 kb
Host smart-0c82421b-5538-477f-baad-84573ebfc6f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337016751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2337016751
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2636328400
Short name T257
Test name
Test status
Simulation time 177790494526 ps
CPU time 197.49 seconds
Started Apr 30 03:03:04 PM PDT 24
Finished Apr 30 03:06:22 PM PDT 24
Peak memory 202268 kb
Host smart-68b7b9d6-2967-44ef-bfd6-e3e6bb222ab6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636328400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2636328400
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1335395251
Short name T671
Test name
Test status
Simulation time 165001570794 ps
CPU time 175.82 seconds
Started Apr 30 03:03:15 PM PDT 24
Finished Apr 30 03:06:11 PM PDT 24
Peak memory 202312 kb
Host smart-f384e423-01d5-4897-97b9-9955d13dcf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335395251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1335395251
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.684852855
Short name T454
Test name
Test status
Simulation time 327778620693 ps
CPU time 811.42 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:16:34 PM PDT 24
Peak memory 202304 kb
Host smart-a21b7a6d-957b-46ac-ac5d-bcf3418f6d84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=684852855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrup
t_fixed.684852855
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.395054102
Short name T135
Test name
Test status
Simulation time 330029166187 ps
CPU time 730.63 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:15:15 PM PDT 24
Peak memory 202336 kb
Host smart-09b34109-af31-40d0-80d5-ea1120932487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395054102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.395054102
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.4152723045
Short name T382
Test name
Test status
Simulation time 494201985323 ps
CPU time 618.89 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:13:23 PM PDT 24
Peak memory 202296 kb
Host smart-c533e935-c537-49f4-8593-a26993c49781
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152723045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.4152723045
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1993363347
Short name T349
Test name
Test status
Simulation time 568636363283 ps
CPU time 1319.04 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:25:03 PM PDT 24
Peak memory 202220 kb
Host smart-40510376-abe1-4ca4-9b2a-eaca2b57eeef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993363347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1993363347
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.507378579
Short name T702
Test name
Test status
Simulation time 402206156740 ps
CPU time 163.02 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:05:46 PM PDT 24
Peak memory 202236 kb
Host smart-f9aec6af-336c-4589-b77f-1378884c0278
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507378579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.507378579
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1515810194
Short name T777
Test name
Test status
Simulation time 75310346880 ps
CPU time 350.3 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:08:52 PM PDT 24
Peak memory 202676 kb
Host smart-0c6e7e37-f602-473f-9717-4ee6e1754ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515810194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1515810194
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1425179838
Short name T743
Test name
Test status
Simulation time 28626379762 ps
CPU time 17.05 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:03:40 PM PDT 24
Peak memory 202120 kb
Host smart-50c4df2a-a979-4692-8c4d-115b468088b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425179838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1425179838
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3181579576
Short name T439
Test name
Test status
Simulation time 5461747886 ps
CPU time 7.38 seconds
Started Apr 30 03:03:27 PM PDT 24
Finished Apr 30 03:03:35 PM PDT 24
Peak memory 202128 kb
Host smart-c42ee241-c62b-41ca-a273-d7f8774d8caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181579576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3181579576
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1349827208
Short name T514
Test name
Test status
Simulation time 6061977734 ps
CPU time 15.28 seconds
Started Apr 30 03:03:12 PM PDT 24
Finished Apr 30 03:03:28 PM PDT 24
Peak memory 202120 kb
Host smart-6854a935-794e-41ea-b435-8210afda752a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349827208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1349827208
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.3019658153
Short name T305
Test name
Test status
Simulation time 321218336681 ps
CPU time 356.02 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:09:01 PM PDT 24
Peak memory 202264 kb
Host smart-8a42a3aa-ffc1-4759-a350-b2e63ffd85b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019658153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.3019658153
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2241892840
Short name T535
Test name
Test status
Simulation time 223268325817 ps
CPU time 190.43 seconds
Started Apr 30 03:03:24 PM PDT 24
Finished Apr 30 03:06:35 PM PDT 24
Peak memory 210924 kb
Host smart-d2813973-8336-4bd2-84d0-f670a1bfbe07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241892840 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2241892840
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1246354155
Short name T745
Test name
Test status
Simulation time 383008355 ps
CPU time 0.77 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:02:40 PM PDT 24
Peak memory 201884 kb
Host smart-ec327044-8b1e-4a47-8e00-1351af4cfcf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246354155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1246354155
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3096577824
Short name T769
Test name
Test status
Simulation time 157662002642 ps
CPU time 65.5 seconds
Started Apr 30 03:02:49 PM PDT 24
Finished Apr 30 03:03:55 PM PDT 24
Peak memory 202336 kb
Host smart-dcbc7bf2-d11f-45c3-afe6-eba1231fcb39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096577824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3096577824
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4252390432
Short name T292
Test name
Test status
Simulation time 166225726572 ps
CPU time 112.52 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:04:31 PM PDT 24
Peak memory 202256 kb
Host smart-578a86a8-2415-4397-81ce-53dc36c8a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252390432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4252390432
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3434061203
Short name T549
Test name
Test status
Simulation time 162640333681 ps
CPU time 138.74 seconds
Started Apr 30 03:02:43 PM PDT 24
Finished Apr 30 03:05:02 PM PDT 24
Peak memory 202240 kb
Host smart-d8d56dca-2705-4284-8156-931562b6e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434061203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3434061203
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2775114403
Short name T651
Test name
Test status
Simulation time 169796135462 ps
CPU time 88.73 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:04:08 PM PDT 24
Peak memory 202236 kb
Host smart-8f0b69fe-de5e-43af-bb3b-09e3bc39925c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775114403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2775114403
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3881929916
Short name T494
Test name
Test status
Simulation time 171438886939 ps
CPU time 215.54 seconds
Started Apr 30 03:02:44 PM PDT 24
Finished Apr 30 03:06:20 PM PDT 24
Peak memory 202256 kb
Host smart-df4989bb-0841-483f-bfaa-436614b658bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881929916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3881929916
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4199235202
Short name T724
Test name
Test status
Simulation time 327561244812 ps
CPU time 192.76 seconds
Started Apr 30 03:02:32 PM PDT 24
Finished Apr 30 03:05:46 PM PDT 24
Peak memory 202180 kb
Host smart-5c7115b9-c586-4e30-ba1b-468c968a3945
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199235202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4199235202
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3132434223
Short name T665
Test name
Test status
Simulation time 600342782521 ps
CPU time 395.69 seconds
Started Apr 30 03:02:41 PM PDT 24
Finished Apr 30 03:09:17 PM PDT 24
Peak memory 202264 kb
Host smart-256faa71-ad21-4ecb-b12e-0d8403d00831
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132434223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3132434223
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2374077074
Short name T10
Test name
Test status
Simulation time 104560864902 ps
CPU time 516.26 seconds
Started Apr 30 03:02:40 PM PDT 24
Finished Apr 30 03:11:17 PM PDT 24
Peak memory 202676 kb
Host smart-8317ec00-8638-4ebe-af4e-78e47c991274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374077074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2374077074
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.96069489
Short name T556
Test name
Test status
Simulation time 21516604388 ps
CPU time 5.48 seconds
Started Apr 30 03:02:38 PM PDT 24
Finished Apr 30 03:02:44 PM PDT 24
Peak memory 202032 kb
Host smart-19b86ec0-6568-4334-8d37-ebe12b917b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96069489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.96069489
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4233541864
Short name T397
Test name
Test status
Simulation time 4270809599 ps
CPU time 3.19 seconds
Started Apr 30 03:02:42 PM PDT 24
Finished Apr 30 03:02:45 PM PDT 24
Peak memory 202104 kb
Host smart-4422b315-9600-451a-adc0-95807d43efae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233541864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4233541864
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1288719049
Short name T57
Test name
Test status
Simulation time 7392208283 ps
CPU time 17.15 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:03:03 PM PDT 24
Peak memory 218944 kb
Host smart-d343e026-747d-4866-9c2b-0de779c9433c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288719049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1288719049
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3126475369
Short name T507
Test name
Test status
Simulation time 6031462605 ps
CPU time 11.53 seconds
Started Apr 30 03:02:41 PM PDT 24
Finished Apr 30 03:02:53 PM PDT 24
Peak memory 202072 kb
Host smart-2de48a0a-c57f-491d-b3e1-2841996a6652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126475369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3126475369
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1460828024
Short name T90
Test name
Test status
Simulation time 205875822497 ps
CPU time 142.43 seconds
Started Apr 30 03:02:39 PM PDT 24
Finished Apr 30 03:05:02 PM PDT 24
Peak memory 211104 kb
Host smart-65ddbde8-e428-46c5-9863-53bb8d088c5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460828024 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1460828024
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.763288284
Short name T585
Test name
Test status
Simulation time 302690587 ps
CPU time 0.79 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 201996 kb
Host smart-7aac0e77-4c7c-4888-9131-2a22ee55a76a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763288284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.763288284
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1783908483
Short name T174
Test name
Test status
Simulation time 506810643572 ps
CPU time 111 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:05:15 PM PDT 24
Peak memory 202376 kb
Host smart-178067db-9666-48b8-a1f2-7e359cfdc766
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783908483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1783908483
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3505387474
Short name T275
Test name
Test status
Simulation time 163051656369 ps
CPU time 99.95 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:04:47 PM PDT 24
Peak memory 202276 kb
Host smart-9aced6b0-39cf-451b-b4e8-d2d1cb045e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505387474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3505387474
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2584589712
Short name T794
Test name
Test status
Simulation time 492046533802 ps
CPU time 580.46 seconds
Started Apr 30 03:03:28 PM PDT 24
Finished Apr 30 03:13:09 PM PDT 24
Peak memory 202228 kb
Host smart-21c67a28-93b8-4c38-8a5c-9e8a21d7ed7e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584589712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2584589712
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1009897971
Short name T312
Test name
Test status
Simulation time 165775970539 ps
CPU time 109.58 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:04:51 PM PDT 24
Peak memory 202372 kb
Host smart-9e07e47b-0397-43b0-a6ae-b6d4a4513d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009897971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1009897971
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3245831915
Short name T756
Test name
Test status
Simulation time 325735538967 ps
CPU time 813.06 seconds
Started Apr 30 03:03:18 PM PDT 24
Finished Apr 30 03:16:52 PM PDT 24
Peak memory 202228 kb
Host smart-382c1e1c-1263-4cc8-8a54-04b51fb7a9cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245831915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3245831915
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1465258966
Short name T610
Test name
Test status
Simulation time 605431775147 ps
CPU time 1460.88 seconds
Started Apr 30 03:03:21 PM PDT 24
Finished Apr 30 03:27:43 PM PDT 24
Peak memory 202272 kb
Host smart-3cb8987c-d3c1-45b9-b27b-6f2a37d39085
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465258966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1465258966
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4078438635
Short name T509
Test name
Test status
Simulation time 41556929162 ps
CPU time 18.76 seconds
Started Apr 30 03:03:20 PM PDT 24
Finished Apr 30 03:03:40 PM PDT 24
Peak memory 202108 kb
Host smart-76cd1eb8-25e3-4a39-a5d8-be5de59dab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078438635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4078438635
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.806779495
Short name T539
Test name
Test status
Simulation time 5316616024 ps
CPU time 6.89 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:03:11 PM PDT 24
Peak memory 202116 kb
Host smart-b70a84bb-e60c-4a19-9c11-07a9603e5995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806779495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.806779495
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2219508980
Short name T692
Test name
Test status
Simulation time 5612508514 ps
CPU time 4.11 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:03:27 PM PDT 24
Peak memory 202156 kb
Host smart-66744db7-d21d-4bde-93f6-0772c2f0b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219508980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2219508980
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3552391215
Short name T76
Test name
Test status
Simulation time 340930802 ps
CPU time 1.4 seconds
Started Apr 30 03:03:27 PM PDT 24
Finished Apr 30 03:03:29 PM PDT 24
Peak memory 201976 kb
Host smart-c373aec4-377d-44c1-b6a2-9d64cf60fc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552391215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3552391215
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.3239895198
Short name T663
Test name
Test status
Simulation time 195258708725 ps
CPU time 432.54 seconds
Started Apr 30 03:03:24 PM PDT 24
Finished Apr 30 03:10:37 PM PDT 24
Peak memory 202336 kb
Host smart-d735a82b-79fa-468f-8e35-c2f95957c027
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239895198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.3239895198
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.3790574928
Short name T146
Test name
Test status
Simulation time 513106886323 ps
CPU time 327.83 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:08:42 PM PDT 24
Peak memory 202340 kb
Host smart-79d1666b-cef4-4b63-8024-65bc5df545d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790574928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.3790574928
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2152651853
Short name T192
Test name
Test status
Simulation time 329689371772 ps
CPU time 202.19 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:06:29 PM PDT 24
Peak memory 202252 kb
Host smart-3572e183-1524-4316-b28c-e93d6266e3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152651853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2152651853
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.1883128423
Short name T643
Test name
Test status
Simulation time 328650791229 ps
CPU time 715.57 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:15:04 PM PDT 24
Peak memory 202260 kb
Host smart-b23f3ac8-8a4f-4ca0-a38c-965f7b240782
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883128423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.1883128423
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2664463377
Short name T637
Test name
Test status
Simulation time 159616692776 ps
CPU time 85.33 seconds
Started Apr 30 03:03:15 PM PDT 24
Finished Apr 30 03:04:41 PM PDT 24
Peak memory 202352 kb
Host smart-76b3458c-e528-487f-a695-46dec496717f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664463377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2664463377
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1712267019
Short name T771
Test name
Test status
Simulation time 164085948732 ps
CPU time 195.27 seconds
Started Apr 30 03:03:17 PM PDT 24
Finished Apr 30 03:06:32 PM PDT 24
Peak memory 202396 kb
Host smart-ea36afeb-216e-413a-9e05-6c27c516a69a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712267019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1712267019
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3820371370
Short name T252
Test name
Test status
Simulation time 249384336031 ps
CPU time 151.31 seconds
Started Apr 30 03:03:05 PM PDT 24
Finished Apr 30 03:05:37 PM PDT 24
Peak memory 202264 kb
Host smart-5ea5396f-e86a-4bc4-8c3e-a390c1637047
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820371370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3820371370
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.2639738414
Short name T555
Test name
Test status
Simulation time 596689293767 ps
CPU time 1493.29 seconds
Started Apr 30 03:03:25 PM PDT 24
Finished Apr 30 03:28:19 PM PDT 24
Peak memory 202296 kb
Host smart-e7774482-4bde-43b6-992c-53972b40ba0d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639738414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.2639738414
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.68907926
Short name T365
Test name
Test status
Simulation time 84187011671 ps
CPU time 285.15 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:07:57 PM PDT 24
Peak memory 202688 kb
Host smart-088ca7ce-c9e3-4151-8a6a-710f76537914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68907926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.68907926
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1237778526
Short name T573
Test name
Test status
Simulation time 25196963302 ps
CPU time 5.19 seconds
Started Apr 30 03:03:08 PM PDT 24
Finished Apr 30 03:03:14 PM PDT 24
Peak memory 202088 kb
Host smart-54535613-a4d5-48a4-b6d3-bbcf1dabc9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237778526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1237778526
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.891660610
Short name T383
Test name
Test status
Simulation time 4268803553 ps
CPU time 2.89 seconds
Started Apr 30 03:03:17 PM PDT 24
Finished Apr 30 03:03:20 PM PDT 24
Peak memory 202156 kb
Host smart-d8db347c-5f14-4bf7-aac1-1fe573904373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891660610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.891660610
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.1618752718
Short name T653
Test name
Test status
Simulation time 5957170134 ps
CPU time 4.33 seconds
Started Apr 30 03:03:06 PM PDT 24
Finished Apr 30 03:03:10 PM PDT 24
Peak memory 202068 kb
Host smart-6837a0b5-a050-43a8-a192-919ac90e6e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618752718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.1618752718
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1316881789
Short name T659
Test name
Test status
Simulation time 53830271687 ps
CPU time 93.99 seconds
Started Apr 30 03:03:04 PM PDT 24
Finished Apr 30 03:04:39 PM PDT 24
Peak memory 202248 kb
Host smart-68d73b0f-5fe0-4117-bba1-6b2ac0cdc9f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316881789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1316881789
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.453980758
Short name T276
Test name
Test status
Simulation time 110687979644 ps
CPU time 72.93 seconds
Started Apr 30 03:03:07 PM PDT 24
Finished Apr 30 03:04:20 PM PDT 24
Peak memory 218276 kb
Host smart-5f8c5377-4739-4c57-89a6-32b0570dd1af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453980758 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.453980758
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2467303964
Short name T522
Test name
Test status
Simulation time 528767903 ps
CPU time 1.18 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:03:33 PM PDT 24
Peak memory 201976 kb
Host smart-97f88e4f-f750-4b13-9089-d3f90d76f7be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467303964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2467303964
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1776965578
Short name T315
Test name
Test status
Simulation time 348392283577 ps
CPU time 200.48 seconds
Started Apr 30 03:03:10 PM PDT 24
Finished Apr 30 03:06:31 PM PDT 24
Peak memory 202300 kb
Host smart-5e0acde2-9d05-4bd0-ab87-129e3ad398d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776965578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1776965578
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1608182021
Short name T551
Test name
Test status
Simulation time 164659127387 ps
CPU time 82.78 seconds
Started Apr 30 03:03:25 PM PDT 24
Finished Apr 30 03:04:49 PM PDT 24
Peak memory 202344 kb
Host smart-36213121-2b17-453a-9f09-1f7bd0be2b5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608182021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1608182021
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2859960231
Short name T787
Test name
Test status
Simulation time 166719758126 ps
CPU time 138.6 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:05:32 PM PDT 24
Peak memory 202364 kb
Host smart-565d1522-7868-44f4-a329-3e868045db66
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859960231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2859960231
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.2912091363
Short name T474
Test name
Test status
Simulation time 410495285308 ps
CPU time 932.91 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:19:04 PM PDT 24
Peak memory 202348 kb
Host smart-4108539a-ab86-44f9-9f84-d37a4f716da9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912091363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.2912091363
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3670131647
Short name T600
Test name
Test status
Simulation time 78162074158 ps
CPU time 381.06 seconds
Started Apr 30 03:03:29 PM PDT 24
Finished Apr 30 03:09:51 PM PDT 24
Peak memory 202640 kb
Host smart-c960f481-d67b-4d16-988b-828fefeae267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670131647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3670131647
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.283286617
Short name T449
Test name
Test status
Simulation time 29531527817 ps
CPU time 18.03 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:03:29 PM PDT 24
Peak memory 202080 kb
Host smart-11f6deec-51b8-4fa0-9088-79dae43475c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283286617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.283286617
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1348542025
Short name T654
Test name
Test status
Simulation time 3112459551 ps
CPU time 7.92 seconds
Started Apr 30 03:03:27 PM PDT 24
Finished Apr 30 03:03:36 PM PDT 24
Peak memory 202084 kb
Host smart-a13753be-3784-4c5a-a13f-4eee679acce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348542025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1348542025
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.136460927
Short name T8
Test name
Test status
Simulation time 6007835233 ps
CPU time 3.68 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:03:27 PM PDT 24
Peak memory 202116 kb
Host smart-27561d37-ffa1-46af-b024-34828d1f64aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136460927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.136460927
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2292319055
Short name T792
Test name
Test status
Simulation time 624952908363 ps
CPU time 674.52 seconds
Started Apr 30 03:03:30 PM PDT 24
Finished Apr 30 03:14:45 PM PDT 24
Peak memory 202332 kb
Host smart-3849cd67-bcd0-45ce-a6a5-55d521a6defe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292319055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2292319055
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3016522915
Short name T101
Test name
Test status
Simulation time 47886858202 ps
CPU time 154.48 seconds
Started Apr 30 03:03:32 PM PDT 24
Finished Apr 30 03:06:07 PM PDT 24
Peak memory 211992 kb
Host smart-8865480f-20df-40af-a0f7-47c3c8cd3b3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016522915 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3016522915
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3206885961
Short name T64
Test name
Test status
Simulation time 541701218 ps
CPU time 0.99 seconds
Started Apr 30 03:03:20 PM PDT 24
Finished Apr 30 03:03:22 PM PDT 24
Peak memory 202000 kb
Host smart-058160a9-0f9f-4a1f-a19f-74a06d79781a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206885961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3206885961
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2202889069
Short name T242
Test name
Test status
Simulation time 279728398561 ps
CPU time 138.92 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:05:54 PM PDT 24
Peak memory 202280 kb
Host smart-85769c5a-f392-411b-9418-a9e7a290c150
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202889069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2202889069
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2393708636
Short name T754
Test name
Test status
Simulation time 189590677686 ps
CPU time 454.07 seconds
Started Apr 30 03:03:19 PM PDT 24
Finished Apr 30 03:10:54 PM PDT 24
Peak memory 202288 kb
Host smart-67d32280-919a-4a37-834b-36992afef4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393708636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2393708636
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.872706463
Short name T263
Test name
Test status
Simulation time 162764755528 ps
CPU time 69.56 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:04:41 PM PDT 24
Peak memory 202368 kb
Host smart-4e571fde-3e38-4e2e-9533-880cfe61e502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872706463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.872706463
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2231134105
Short name T747
Test name
Test status
Simulation time 329558269774 ps
CPU time 387.72 seconds
Started Apr 30 03:03:28 PM PDT 24
Finished Apr 30 03:09:56 PM PDT 24
Peak memory 202316 kb
Host smart-d635c9dd-9bcb-4561-84a0-53faf0f10be1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231134105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2231134105
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3193175676
Short name T471
Test name
Test status
Simulation time 168231541885 ps
CPU time 369.19 seconds
Started Apr 30 03:03:25 PM PDT 24
Finished Apr 30 03:09:34 PM PDT 24
Peak memory 202320 kb
Host smart-14abfbca-9a33-4b26-b6f4-e1256225d05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193175676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3193175676
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1125262063
Short name T140
Test name
Test status
Simulation time 331079567428 ps
CPU time 44.72 seconds
Started Apr 30 03:03:13 PM PDT 24
Finished Apr 30 03:03:59 PM PDT 24
Peak memory 202276 kb
Host smart-647b9a31-b852-4ca8-b6eb-88ecf1b06d95
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125262063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1125262063
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2179772743
Short name T98
Test name
Test status
Simulation time 542140140377 ps
CPU time 1282.6 seconds
Started Apr 30 03:03:27 PM PDT 24
Finished Apr 30 03:24:50 PM PDT 24
Peak memory 202328 kb
Host smart-786760ac-a792-43eb-9db6-58320ee01434
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179772743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2179772743
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2815994141
Short name T465
Test name
Test status
Simulation time 615092822934 ps
CPU time 1394.79 seconds
Started Apr 30 03:03:28 PM PDT 24
Finished Apr 30 03:26:43 PM PDT 24
Peak memory 202288 kb
Host smart-cb2e277d-1c35-42e8-97f5-b339bea3c07f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815994141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2815994141
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1509134004
Short name T592
Test name
Test status
Simulation time 114611184195 ps
CPU time 385.76 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:09:50 PM PDT 24
Peak memory 202632 kb
Host smart-ff32ff23-887b-468f-b9ad-632dba2bac0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509134004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1509134004
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.809260518
Short name T779
Test name
Test status
Simulation time 45272236158 ps
CPU time 26.14 seconds
Started Apr 30 03:03:12 PM PDT 24
Finished Apr 30 03:03:39 PM PDT 24
Peak memory 202088 kb
Host smart-824b609d-9f85-47c2-8063-eae95f712ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809260518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.809260518
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.456564171
Short name T407
Test name
Test status
Simulation time 3797454429 ps
CPU time 2.22 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:03:13 PM PDT 24
Peak memory 202056 kb
Host smart-4d96f08b-bba8-40ee-af5a-abd97df1d90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456564171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.456564171
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1789115965
Short name T512
Test name
Test status
Simulation time 5533714277 ps
CPU time 2.89 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:03:26 PM PDT 24
Peak memory 202164 kb
Host smart-38fa7d74-4a29-457d-8467-774bab6a05c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789115965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1789115965
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.595711385
Short name T361
Test name
Test status
Simulation time 130322937940 ps
CPU time 597.14 seconds
Started Apr 30 03:03:15 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 202648 kb
Host smart-7eafffee-2c1c-440e-a87c-3cd84e829932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595711385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
595711385
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1103949503
Short name T40
Test name
Test status
Simulation time 154345699733 ps
CPU time 94.3 seconds
Started Apr 30 03:03:11 PM PDT 24
Finished Apr 30 03:04:46 PM PDT 24
Peak memory 202448 kb
Host smart-3f7c7d2c-ba2d-4a7b-b9df-26b2fa32dc7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103949503 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1103949503
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1052349734
Short name T615
Test name
Test status
Simulation time 435675288 ps
CPU time 1.57 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:03:24 PM PDT 24
Peak memory 202040 kb
Host smart-2ad0e2ac-6962-49ad-a27e-33b5ce88d97e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052349734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1052349734
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.723386366
Short name T247
Test name
Test status
Simulation time 177362020296 ps
CPU time 45.49 seconds
Started Apr 30 03:03:30 PM PDT 24
Finished Apr 30 03:04:16 PM PDT 24
Peak memory 202192 kb
Host smart-8dc4fa46-cf81-4dd5-8cd7-77f784cffb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723386366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.723386366
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3500608400
Short name T308
Test name
Test status
Simulation time 161281729551 ps
CPU time 101.71 seconds
Started Apr 30 03:03:20 PM PDT 24
Finished Apr 30 03:05:03 PM PDT 24
Peak memory 202336 kb
Host smart-10406733-144b-45d5-84b8-4966f37ffd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500608400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3500608400
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3768708748
Short name T419
Test name
Test status
Simulation time 325994417268 ps
CPU time 169.1 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:06:12 PM PDT 24
Peak memory 202256 kb
Host smart-48170bf5-0589-43d5-a252-366e6233ae57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768708748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3768708748
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.999860305
Short name T464
Test name
Test status
Simulation time 493782170297 ps
CPU time 570.97 seconds
Started Apr 30 03:03:24 PM PDT 24
Finished Apr 30 03:12:56 PM PDT 24
Peak memory 202336 kb
Host smart-07129eb7-d8a1-41ef-88c6-c026884c1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999860305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.999860305
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1676415885
Short name T430
Test name
Test status
Simulation time 485890534359 ps
CPU time 1093.11 seconds
Started Apr 30 03:03:28 PM PDT 24
Finished Apr 30 03:21:42 PM PDT 24
Peak memory 202232 kb
Host smart-3d3f58d0-606d-4719-946b-e9e8ad787949
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676415885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1676415885
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1429284134
Short name T102
Test name
Test status
Simulation time 361470698965 ps
CPU time 94.91 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:05:07 PM PDT 24
Peak memory 202356 kb
Host smart-3f27b8e0-dad6-4806-944a-535928e7ead7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429284134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1429284134
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1004639363
Short name T544
Test name
Test status
Simulation time 198255222103 ps
CPU time 390.7 seconds
Started Apr 30 03:03:24 PM PDT 24
Finished Apr 30 03:09:55 PM PDT 24
Peak memory 202332 kb
Host smart-52c59416-2e56-4898-93f3-2416f7e06fd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004639363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1004639363
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3074205153
Short name T650
Test name
Test status
Simulation time 88667140467 ps
CPU time 307.11 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:08:30 PM PDT 24
Peak memory 202576 kb
Host smart-2f17d1e0-af4e-4568-b956-9fe1c4ec0e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074205153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3074205153
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2558400457
Short name T642
Test name
Test status
Simulation time 42273850619 ps
CPU time 91.68 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:05:06 PM PDT 24
Peak memory 202136 kb
Host smart-dd23fc91-e87e-4164-9dd9-958f5ee299fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558400457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2558400457
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2408100173
Short name T764
Test name
Test status
Simulation time 3729814453 ps
CPU time 4.98 seconds
Started Apr 30 03:03:32 PM PDT 24
Finished Apr 30 03:03:38 PM PDT 24
Peak memory 202120 kb
Host smart-396b26e9-d902-466f-afa6-b332d744470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408100173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2408100173
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2298879870
Short name T427
Test name
Test status
Simulation time 5779689590 ps
CPU time 7.55 seconds
Started Apr 30 03:03:29 PM PDT 24
Finished Apr 30 03:03:38 PM PDT 24
Peak memory 202072 kb
Host smart-0db7e341-3873-4b8d-a70a-6dc34d67278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298879870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2298879870
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.3398789443
Short name T458
Test name
Test status
Simulation time 86716803481 ps
CPU time 43.65 seconds
Started Apr 30 03:03:21 PM PDT 24
Finished Apr 30 03:04:05 PM PDT 24
Peak memory 202092 kb
Host smart-a504e2db-037b-4504-a885-6294a6895099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398789443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.3398789443
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2858926089
Short name T33
Test name
Test status
Simulation time 53539666638 ps
CPU time 59 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:04:22 PM PDT 24
Peak memory 210644 kb
Host smart-eb95ef9c-4a0c-4c9f-bb1d-37b2ebd8cf83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858926089 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2858926089
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2269661342
Short name T497
Test name
Test status
Simulation time 282650976 ps
CPU time 1.26 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:03:33 PM PDT 24
Peak memory 201996 kb
Host smart-b564840e-7db8-4e80-9532-f1370f478b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269661342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2269661342
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.285117088
Short name T11
Test name
Test status
Simulation time 322171729253 ps
CPU time 421.77 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:10:37 PM PDT 24
Peak memory 202300 kb
Host smart-97200224-7e16-473c-95d6-773d3b991a80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285117088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gati
ng.285117088
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3743555970
Short name T619
Test name
Test status
Simulation time 349669130703 ps
CPU time 766.59 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:16:10 PM PDT 24
Peak memory 202380 kb
Host smart-527e9e69-aec3-4985-884d-27b8e54d8a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743555970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3743555970
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1692192451
Short name T740
Test name
Test status
Simulation time 171202608688 ps
CPU time 111.39 seconds
Started Apr 30 03:03:27 PM PDT 24
Finished Apr 30 03:05:19 PM PDT 24
Peak memory 202284 kb
Host smart-5c72815b-a5e8-4870-895f-b17169f2be69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692192451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1692192451
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1126829575
Short name T518
Test name
Test status
Simulation time 334275226769 ps
CPU time 800.87 seconds
Started Apr 30 03:03:30 PM PDT 24
Finished Apr 30 03:16:52 PM PDT 24
Peak memory 202320 kb
Host smart-f3fd484a-6feb-487f-bbd4-ef44ba237245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126829575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1126829575
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3495831630
Short name T505
Test name
Test status
Simulation time 499404723943 ps
CPU time 260.94 seconds
Started Apr 30 03:03:33 PM PDT 24
Finished Apr 30 03:07:55 PM PDT 24
Peak memory 202212 kb
Host smart-80a22ad5-59e8-4ac6-b074-cd75d6986f23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495831630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3495831630
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3942676799
Short name T295
Test name
Test status
Simulation time 358179455321 ps
CPU time 830.09 seconds
Started Apr 30 03:03:21 PM PDT 24
Finished Apr 30 03:17:12 PM PDT 24
Peak memory 202272 kb
Host smart-c3eee469-569b-4603-abed-9c8264178842
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942676799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3942676799
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3713537776
Short name T451
Test name
Test status
Simulation time 406231880162 ps
CPU time 1001.96 seconds
Started Apr 30 03:03:32 PM PDT 24
Finished Apr 30 03:20:15 PM PDT 24
Peak memory 202316 kb
Host smart-4f82af3a-03dc-4263-861b-5416ffb1eb07
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713537776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3713537776
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2206931047
Short name T605
Test name
Test status
Simulation time 83680267678 ps
CPU time 338.64 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:09:14 PM PDT 24
Peak memory 202744 kb
Host smart-7aeded02-f0b0-4372-8f15-6407c91987f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206931047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2206931047
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.515881432
Short name T791
Test name
Test status
Simulation time 27981936633 ps
CPU time 69.37 seconds
Started Apr 30 03:03:29 PM PDT 24
Finished Apr 30 03:04:40 PM PDT 24
Peak memory 202076 kb
Host smart-0b6890ff-b953-4265-95ab-9ea9520e0956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515881432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.515881432
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.3039075153
Short name T785
Test name
Test status
Simulation time 3564822795 ps
CPU time 2.58 seconds
Started Apr 30 03:03:30 PM PDT 24
Finished Apr 30 03:03:33 PM PDT 24
Peak memory 202156 kb
Host smart-73c1f54f-6e80-4f03-8d5f-fa17616fd3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039075153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.3039075153
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.567553412
Short name T195
Test name
Test status
Simulation time 5663609342 ps
CPU time 14.62 seconds
Started Apr 30 03:03:22 PM PDT 24
Finished Apr 30 03:03:38 PM PDT 24
Peak memory 202060 kb
Host smart-a27a19b3-ead3-4064-9258-6b906fe55646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567553412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.567553412
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1747820373
Short name T450
Test name
Test status
Simulation time 141032149238 ps
CPU time 492.51 seconds
Started Apr 30 03:03:32 PM PDT 24
Finished Apr 30 03:11:45 PM PDT 24
Peak memory 202768 kb
Host smart-d8b1fcd0-43ef-4671-b195-24241a33aace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747820373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1747820373
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3630056668
Short name T111
Test name
Test status
Simulation time 65166538914 ps
CPU time 123.05 seconds
Started Apr 30 03:03:28 PM PDT 24
Finished Apr 30 03:05:31 PM PDT 24
Peak memory 210648 kb
Host smart-f18a0711-0de9-4459-8108-19c415d3528b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630056668 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3630056668
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1965943192
Short name T440
Test name
Test status
Simulation time 413391227 ps
CPU time 0.81 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:03:36 PM PDT 24
Peak memory 201932 kb
Host smart-91b2e371-e200-4915-bf20-142e351843c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965943192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1965943192
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2641203905
Short name T765
Test name
Test status
Simulation time 325379263111 ps
CPU time 112.39 seconds
Started Apr 30 03:03:29 PM PDT 24
Finished Apr 30 03:05:22 PM PDT 24
Peak memory 202272 kb
Host smart-ce27e09a-b75f-4897-9776-b42f979acb25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641203905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2641203905
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.286680671
Short name T625
Test name
Test status
Simulation time 166045410681 ps
CPU time 201.03 seconds
Started Apr 30 03:03:32 PM PDT 24
Finished Apr 30 03:06:54 PM PDT 24
Peak memory 202260 kb
Host smart-9598f0ca-ee75-48ce-9706-ca154ede7852
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=286680671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.286680671
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.88450581
Short name T307
Test name
Test status
Simulation time 328396624660 ps
CPU time 195.61 seconds
Started Apr 30 03:03:23 PM PDT 24
Finished Apr 30 03:06:39 PM PDT 24
Peak memory 202404 kb
Host smart-3d71c2f8-5e9c-4e3b-9aa7-9c3e55ee7e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88450581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.88450581
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3861132798
Short name T588
Test name
Test status
Simulation time 162671631923 ps
CPU time 349.84 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:09:24 PM PDT 24
Peak memory 202268 kb
Host smart-0aa8a2ac-ee4e-4a43-8e12-17aceed46982
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861132798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3861132798
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.378903858
Short name T168
Test name
Test status
Simulation time 530115869728 ps
CPU time 1279.07 seconds
Started Apr 30 03:03:27 PM PDT 24
Finished Apr 30 03:24:47 PM PDT 24
Peak memory 202296 kb
Host smart-0bd269c7-6a75-411d-905c-c9823060aa1e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378903858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.378903858
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3836170880
Short name T682
Test name
Test status
Simulation time 401186073955 ps
CPU time 228.92 seconds
Started Apr 30 03:03:38 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 202280 kb
Host smart-79cfd2d7-3848-4d1f-aa32-76d8a26398fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836170880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3836170880
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.10381882
Short name T676
Test name
Test status
Simulation time 44093851463 ps
CPU time 13.31 seconds
Started Apr 30 03:03:33 PM PDT 24
Finished Apr 30 03:03:47 PM PDT 24
Peak memory 202156 kb
Host smart-29164d4b-a3fa-4520-a3be-7641a4c0562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10381882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.10381882
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1067031051
Short name T678
Test name
Test status
Simulation time 4713567247 ps
CPU time 12.11 seconds
Started Apr 30 03:03:28 PM PDT 24
Finished Apr 30 03:03:41 PM PDT 24
Peak memory 202076 kb
Host smart-f3bf7b97-f353-4c7a-be9b-9b0e507a51d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067031051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1067031051
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1420608441
Short name T169
Test name
Test status
Simulation time 5556868018 ps
CPU time 11.09 seconds
Started Apr 30 03:03:38 PM PDT 24
Finished Apr 30 03:03:50 PM PDT 24
Peak memory 202132 kb
Host smart-7776d2f0-8913-482d-961e-20c91b5922e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420608441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1420608441
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.915749440
Short name T13
Test name
Test status
Simulation time 334881389680 ps
CPU time 187.56 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:06:44 PM PDT 24
Peak memory 202320 kb
Host smart-2831d773-ee67-4e45-92f9-600ba54d131b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915749440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
915749440
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3541390788
Short name T41
Test name
Test status
Simulation time 96770233561 ps
CPU time 137.65 seconds
Started Apr 30 03:03:33 PM PDT 24
Finished Apr 30 03:05:51 PM PDT 24
Peak memory 210968 kb
Host smart-16c612f0-1565-447a-97f0-043eeceae606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541390788 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3541390788
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1855185981
Short name T395
Test name
Test status
Simulation time 286107878 ps
CPU time 1.22 seconds
Started Apr 30 03:03:33 PM PDT 24
Finished Apr 30 03:03:35 PM PDT 24
Peak memory 202000 kb
Host smart-d41b6c37-7460-4a49-a85e-480757c9f4ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855185981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1855185981
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.170500470
Short name T633
Test name
Test status
Simulation time 167778154390 ps
CPU time 102.25 seconds
Started Apr 30 03:03:36 PM PDT 24
Finished Apr 30 03:05:19 PM PDT 24
Peak memory 202256 kb
Host smart-ba5dd149-b579-41d3-94f6-c21126699ee3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170500470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.170500470
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.933560465
Short name T108
Test name
Test status
Simulation time 329486117196 ps
CPU time 124.9 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:05:41 PM PDT 24
Peak memory 202248 kb
Host smart-c5c7e7c8-8fef-4c8b-97a6-b066de87b2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933560465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.933560465
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.483729017
Short name T166
Test name
Test status
Simulation time 497156244883 ps
CPU time 239.75 seconds
Started Apr 30 03:03:33 PM PDT 24
Finished Apr 30 03:07:33 PM PDT 24
Peak memory 202332 kb
Host smart-8df1fd5e-4f45-427d-97e5-fa19b7e46bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483729017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.483729017
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2510012385
Short name T751
Test name
Test status
Simulation time 482684963085 ps
CPU time 268.14 seconds
Started Apr 30 03:03:36 PM PDT 24
Finished Apr 30 03:08:05 PM PDT 24
Peak memory 202296 kb
Host smart-3f9fffc0-79f5-4ae7-bdad-9ace7e183596
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510012385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2510012385
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3735017700
Short name T656
Test name
Test status
Simulation time 487151085701 ps
CPU time 198.85 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:06:54 PM PDT 24
Peak memory 202360 kb
Host smart-3b6cbf10-5e1e-4105-a3fc-53fcd96057f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735017700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3735017700
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3207526015
Short name T410
Test name
Test status
Simulation time 504077530536 ps
CPU time 300.07 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:08:35 PM PDT 24
Peak memory 202344 kb
Host smart-3a699c38-ecde-4bdd-8439-0357a90aaf1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207526015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3207526015
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.1258970002
Short name T157
Test name
Test status
Simulation time 354409608388 ps
CPU time 202.47 seconds
Started Apr 30 03:03:30 PM PDT 24
Finished Apr 30 03:06:53 PM PDT 24
Peak memory 202396 kb
Host smart-5f2063a4-cef1-4e45-857e-fb6d11210a8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258970002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.1258970002
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.641832650
Short name T473
Test name
Test status
Simulation time 202533601015 ps
CPU time 129.05 seconds
Started Apr 30 03:03:31 PM PDT 24
Finished Apr 30 03:05:40 PM PDT 24
Peak memory 202308 kb
Host smart-52e3219d-2057-465a-a271-d1dbab94d8cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641832650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
adc_ctrl_filters_wakeup_fixed.641832650
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1695801496
Short name T776
Test name
Test status
Simulation time 95217127561 ps
CPU time 454.5 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:11:09 PM PDT 24
Peak memory 202632 kb
Host smart-d052ed65-d2e2-4f4b-b687-7b901911ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695801496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1695801496
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.73476802
Short name T581
Test name
Test status
Simulation time 38826062358 ps
CPU time 91.93 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:05:07 PM PDT 24
Peak memory 202136 kb
Host smart-c75e445e-afb1-43b1-bce8-f267a3cb4a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73476802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.73476802
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2090875964
Short name T428
Test name
Test status
Simulation time 3901554289 ps
CPU time 9.32 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:03:46 PM PDT 24
Peak memory 202072 kb
Host smart-2a7236dd-2c80-4e8c-ba0b-ea2745944021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090875964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2090875964
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.204523144
Short name T403
Test name
Test status
Simulation time 5999100366 ps
CPU time 14.76 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:03:50 PM PDT 24
Peak memory 202120 kb
Host smart-ef5d51d0-e768-4cff-bbb0-dcf86427a08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204523144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.204523144
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2169781494
Short name T616
Test name
Test status
Simulation time 436924043473 ps
CPU time 575.67 seconds
Started Apr 30 03:03:37 PM PDT 24
Finished Apr 30 03:13:13 PM PDT 24
Peak memory 202668 kb
Host smart-b6f9d56f-0aed-4bb9-9ca3-10bc335ba15c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169781494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2169781494
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3700649518
Short name T250
Test name
Test status
Simulation time 22461873518 ps
CPU time 41.51 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:04:18 PM PDT 24
Peak memory 210932 kb
Host smart-b54e1f7f-6a1b-4756-a7bc-2242b44c77f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700649518 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3700649518
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.267004866
Short name T65
Test name
Test status
Simulation time 395479911 ps
CPU time 1.06 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:03:37 PM PDT 24
Peak memory 202000 kb
Host smart-ea736fa5-172b-4a7e-b0d7-07ecd8f306b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267004866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.267004866
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3732470453
Short name T289
Test name
Test status
Simulation time 157623706406 ps
CPU time 206.91 seconds
Started Apr 30 03:03:38 PM PDT 24
Finished Apr 30 03:07:05 PM PDT 24
Peak memory 202308 kb
Host smart-7e2feab9-c0f1-40a5-95ff-cc2977c5e864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732470453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3732470453
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.724481552
Short name T414
Test name
Test status
Simulation time 503273427946 ps
CPU time 320.48 seconds
Started Apr 30 03:03:39 PM PDT 24
Finished Apr 30 03:09:00 PM PDT 24
Peak memory 202280 kb
Host smart-cf7b237c-2450-4eaf-a906-9a707def0ec4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=724481552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.724481552
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.692075851
Short name T311
Test name
Test status
Simulation time 327011842715 ps
CPU time 209.61 seconds
Started Apr 30 03:03:37 PM PDT 24
Finished Apr 30 03:07:07 PM PDT 24
Peak memory 202308 kb
Host smart-f64007cc-5a17-4e05-a860-15ba5ce027c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692075851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.692075851
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.786658335
Short name T675
Test name
Test status
Simulation time 328531001737 ps
CPU time 161.47 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:06:16 PM PDT 24
Peak memory 202268 kb
Host smart-bc0cb656-4513-47bf-bbec-5d486afd8317
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=786658335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.786658335
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.422694065
Short name T243
Test name
Test status
Simulation time 369218492955 ps
CPU time 768.95 seconds
Started Apr 30 03:03:37 PM PDT 24
Finished Apr 30 03:16:27 PM PDT 24
Peak memory 202328 kb
Host smart-1de2c9b8-7385-4ec3-bd7a-fef61faadad9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422694065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.422694065
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1833298836
Short name T97
Test name
Test status
Simulation time 388229978699 ps
CPU time 174.91 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:06:30 PM PDT 24
Peak memory 202264 kb
Host smart-77bc7917-0d55-46d1-a623-74b078791d30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833298836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1833298836
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.4109435895
Short name T219
Test name
Test status
Simulation time 71143439160 ps
CPU time 394.46 seconds
Started Apr 30 03:03:36 PM PDT 24
Finished Apr 30 03:10:11 PM PDT 24
Peak memory 202596 kb
Host smart-0276a6a5-3885-42ce-9ece-b494167ca099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109435895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.4109435895
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3308969543
Short name T379
Test name
Test status
Simulation time 25950626660 ps
CPU time 60.31 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:04:36 PM PDT 24
Peak memory 202072 kb
Host smart-4bec9716-3c13-432a-b832-13455a1d8506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308969543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3308969543
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1631580190
Short name T538
Test name
Test status
Simulation time 5058297813 ps
CPU time 3.66 seconds
Started Apr 30 03:03:38 PM PDT 24
Finished Apr 30 03:03:43 PM PDT 24
Peak memory 202076 kb
Host smart-748c346c-73b2-4d65-ac5c-5948734a574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631580190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1631580190
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3879651051
Short name T558
Test name
Test status
Simulation time 5929799838 ps
CPU time 9.17 seconds
Started Apr 30 03:03:39 PM PDT 24
Finished Apr 30 03:03:49 PM PDT 24
Peak memory 202156 kb
Host smart-c08089e9-7661-467d-b705-bdbae2764ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879651051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3879651051
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3070530958
Short name T282
Test name
Test status
Simulation time 412289201994 ps
CPU time 914.96 seconds
Started Apr 30 03:03:39 PM PDT 24
Finished Apr 30 03:18:55 PM PDT 24
Peak memory 202348 kb
Host smart-188e7e6c-fe7d-4e8d-89eb-3ecc2b18dfb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070530958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3070530958
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2212911648
Short name T265
Test name
Test status
Simulation time 182203235468 ps
CPU time 171.79 seconds
Started Apr 30 03:03:41 PM PDT 24
Finished Apr 30 03:06:34 PM PDT 24
Peak memory 211044 kb
Host smart-db44e865-5de0-4350-be60-3306876bf826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212911648 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2212911648
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1618700197
Short name T531
Test name
Test status
Simulation time 424847298 ps
CPU time 0.86 seconds
Started Apr 30 03:03:44 PM PDT 24
Finished Apr 30 03:03:46 PM PDT 24
Peak memory 201984 kb
Host smart-162aff2a-b6a0-41b7-a0e6-01303706ca9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618700197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1618700197
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1087285316
Short name T726
Test name
Test status
Simulation time 383329407506 ps
CPU time 874.04 seconds
Started Apr 30 03:03:33 PM PDT 24
Finished Apr 30 03:18:08 PM PDT 24
Peak memory 202204 kb
Host smart-50d0ef37-4a83-46b1-8b05-457a05b29d81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087285316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1087285316
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.379699263
Short name T194
Test name
Test status
Simulation time 510934403934 ps
CPU time 303.1 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:08:39 PM PDT 24
Peak memory 202256 kb
Host smart-e750f595-9d6f-45a9-9ef0-130cf9437578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379699263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.379699263
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.4100186631
Short name T340
Test name
Test status
Simulation time 504177211302 ps
CPU time 636.21 seconds
Started Apr 30 03:03:40 PM PDT 24
Finished Apr 30 03:14:17 PM PDT 24
Peak memory 202364 kb
Host smart-9e46d295-96e0-4d16-9058-4037265dd0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100186631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.4100186631
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.1695003450
Short name T380
Test name
Test status
Simulation time 328750101256 ps
CPU time 209.93 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:07:06 PM PDT 24
Peak memory 202240 kb
Host smart-c9f3fe73-73a5-4039-ae01-192730d8561f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695003450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.1695003450
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.644774918
Short name T664
Test name
Test status
Simulation time 164598458573 ps
CPU time 379.74 seconds
Started Apr 30 03:03:39 PM PDT 24
Finished Apr 30 03:09:59 PM PDT 24
Peak memory 202324 kb
Host smart-20d3b2e5-cca7-44d6-bf80-afd527945eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644774918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.644774918
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.4292430569
Short name T569
Test name
Test status
Simulation time 331945224043 ps
CPU time 195.23 seconds
Started Apr 30 03:03:34 PM PDT 24
Finished Apr 30 03:06:50 PM PDT 24
Peak memory 202252 kb
Host smart-b6a247a5-4d9a-4ee7-b2bc-0b2ef42971e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292430569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.4292430569
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3897148854
Short name T688
Test name
Test status
Simulation time 198285504962 ps
CPU time 245.45 seconds
Started Apr 30 03:03:36 PM PDT 24
Finished Apr 30 03:07:42 PM PDT 24
Peak memory 202216 kb
Host smart-6dc45dd8-7477-459f-9bd9-37a9c4b240a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897148854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3897148854
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4039407312
Short name T208
Test name
Test status
Simulation time 136605284990 ps
CPU time 724.11 seconds
Started Apr 30 03:03:42 PM PDT 24
Finished Apr 30 03:15:47 PM PDT 24
Peak memory 202616 kb
Host smart-aaa7757a-e200-44d3-9be2-74a47e243bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039407312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4039407312
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.2854005666
Short name T529
Test name
Test status
Simulation time 23143496090 ps
CPU time 14.06 seconds
Started Apr 30 03:03:41 PM PDT 24
Finished Apr 30 03:03:56 PM PDT 24
Peak memory 202132 kb
Host smart-0aeb77d7-a9c9-4a43-983a-114a4d65db95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854005666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.2854005666
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2750852931
Short name T504
Test name
Test status
Simulation time 3655692171 ps
CPU time 9.87 seconds
Started Apr 30 03:03:40 PM PDT 24
Finished Apr 30 03:03:50 PM PDT 24
Peak memory 202156 kb
Host smart-f190da2c-6512-46ab-af58-fe0cc071cdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750852931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2750852931
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.38320325
Short name T446
Test name
Test status
Simulation time 5716203023 ps
CPU time 7.53 seconds
Started Apr 30 03:03:35 PM PDT 24
Finished Apr 30 03:03:43 PM PDT 24
Peak memory 202084 kb
Host smart-04a871cb-3da9-4d48-b0d7-14e5a64eae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38320325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.38320325
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3420150915
Short name T286
Test name
Test status
Simulation time 219292502564 ps
CPU time 424.15 seconds
Started Apr 30 03:03:41 PM PDT 24
Finished Apr 30 03:10:46 PM PDT 24
Peak memory 202360 kb
Host smart-3190527b-60a3-4d2f-bc66-1b5175099bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420150915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3420150915
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2804619872
Short name T629
Test name
Test status
Simulation time 464167925 ps
CPU time 1.78 seconds
Started Apr 30 03:02:50 PM PDT 24
Finished Apr 30 03:02:53 PM PDT 24
Peak memory 201952 kb
Host smart-c4cd2f20-5247-474e-8039-eeb3a6e18a8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804619872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2804619872
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.654479225
Short name T304
Test name
Test status
Simulation time 183159712161 ps
CPU time 240.25 seconds
Started Apr 30 03:02:34 PM PDT 24
Finished Apr 30 03:06:34 PM PDT 24
Peak memory 202376 kb
Host smart-5daeb273-cc92-4a28-9382-30a584edd9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654479225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.654479225
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.2219882456
Short name T317
Test name
Test status
Simulation time 319028099638 ps
CPU time 471.53 seconds
Started Apr 30 03:02:36 PM PDT 24
Finished Apr 30 03:10:28 PM PDT 24
Peak memory 202316 kb
Host smart-7d4ae61f-ce53-45ef-a910-4c392bdb88fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219882456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.2219882456
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2090623330
Short name T95
Test name
Test status
Simulation time 163929905509 ps
CPU time 90.94 seconds
Started Apr 30 03:02:44 PM PDT 24
Finished Apr 30 03:04:15 PM PDT 24
Peak memory 202272 kb
Host smart-16d72154-1bdd-4190-8247-5ea02ac7f6a4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090623330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2090623330
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.710292772
Short name T204
Test name
Test status
Simulation time 166587567441 ps
CPU time 363.47 seconds
Started Apr 30 03:02:40 PM PDT 24
Finished Apr 30 03:08:44 PM PDT 24
Peak memory 202268 kb
Host smart-1bce4571-73f0-4b4f-b9da-1456a4387211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710292772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.710292772
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.146431802
Short name T596
Test name
Test status
Simulation time 323724624757 ps
CPU time 191.09 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:05:57 PM PDT 24
Peak memory 202296 kb
Host smart-b232758a-d57a-4146-b551-b571cb2f0d2e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=146431802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.146431802
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1251241968
Short name T167
Test name
Test status
Simulation time 549903403772 ps
CPU time 313.23 seconds
Started Apr 30 03:02:44 PM PDT 24
Finished Apr 30 03:07:58 PM PDT 24
Peak memory 202264 kb
Host smart-883c6d39-7c1c-4a59-b71d-294aaa74bfd0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251241968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1251241968
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2595513959
Short name T442
Test name
Test status
Simulation time 84079679635 ps
CPU time 391.5 seconds
Started Apr 30 03:02:42 PM PDT 24
Finished Apr 30 03:09:14 PM PDT 24
Peak memory 202688 kb
Host smart-19638b7c-4c0f-44f9-830c-4d1c7ccda90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595513959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2595513959
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.4217806740
Short name T469
Test name
Test status
Simulation time 22199530811 ps
CPU time 47.01 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:03:33 PM PDT 24
Peak memory 202088 kb
Host smart-ba39ef0d-f643-4ee8-b48f-de9dbd9eb4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217806740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4217806740
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2270185173
Short name T623
Test name
Test status
Simulation time 5430916558 ps
CPU time 14.77 seconds
Started Apr 30 03:02:39 PM PDT 24
Finished Apr 30 03:02:55 PM PDT 24
Peak memory 202140 kb
Host smart-1b787c5b-c671-46da-8642-ce20de1c8a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270185173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2270185173
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.2406925604
Short name T58
Test name
Test status
Simulation time 7232112073 ps
CPU time 17.82 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 218828 kb
Host smart-6713a2e9-e7fa-4e02-b929-7bb06e1c9ae0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406925604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.2406925604
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.394107036
Short name T761
Test name
Test status
Simulation time 6112770888 ps
CPU time 2.74 seconds
Started Apr 30 03:02:43 PM PDT 24
Finished Apr 30 03:02:47 PM PDT 24
Peak memory 202080 kb
Host smart-9501c387-c069-4d61-86ea-970a2b9dc9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394107036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.394107036
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.268927549
Short name T492
Test name
Test status
Simulation time 38939137659 ps
CPU time 97.91 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:04:25 PM PDT 24
Peak memory 202144 kb
Host smart-968e2856-05e3-48b1-89f5-56182d2ca53b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268927549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.268927549
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1792513341
Short name T425
Test name
Test status
Simulation time 460115879 ps
CPU time 1.64 seconds
Started Apr 30 03:03:41 PM PDT 24
Finished Apr 30 03:03:43 PM PDT 24
Peak memory 201952 kb
Host smart-1b44b9db-1eca-409b-bebd-08e0e7202c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792513341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1792513341
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3463373384
Short name T336
Test name
Test status
Simulation time 536405763845 ps
CPU time 567.39 seconds
Started Apr 30 03:03:41 PM PDT 24
Finished Apr 30 03:13:09 PM PDT 24
Peak memory 202280 kb
Host smart-3596b4cc-4cc1-433e-a5a7-a2bb9c4d9fca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463373384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3463373384
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.257607925
Short name T646
Test name
Test status
Simulation time 184752754480 ps
CPU time 108.05 seconds
Started Apr 30 03:03:43 PM PDT 24
Finished Apr 30 03:05:31 PM PDT 24
Peak memory 202288 kb
Host smart-d5d5ff7e-4f10-43ff-b40f-01c94bbaa0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257607925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.257607925
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1679874676
Short name T660
Test name
Test status
Simulation time 162590350616 ps
CPU time 107.71 seconds
Started Apr 30 03:03:44 PM PDT 24
Finished Apr 30 03:05:33 PM PDT 24
Peak memory 202276 kb
Host smart-99c3d5ad-9fc5-44ce-ac03-e6edd649004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679874676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1679874676
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3277151415
Short name T390
Test name
Test status
Simulation time 323845355828 ps
CPU time 704.46 seconds
Started Apr 30 03:03:44 PM PDT 24
Finished Apr 30 03:15:29 PM PDT 24
Peak memory 202232 kb
Host smart-5485f9d6-15b6-4af3-8b70-de47d78fda4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277151415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3277151415
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.570107046
Short name T578
Test name
Test status
Simulation time 157398471212 ps
CPU time 197.53 seconds
Started Apr 30 03:03:49 PM PDT 24
Finished Apr 30 03:07:07 PM PDT 24
Peak memory 202160 kb
Host smart-ad179d25-475b-4eb7-8fe5-9d37809561c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570107046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.570107046
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2649872194
Short name T185
Test name
Test status
Simulation time 326322312221 ps
CPU time 192.93 seconds
Started Apr 30 03:03:43 PM PDT 24
Finished Apr 30 03:06:57 PM PDT 24
Peak memory 202292 kb
Host smart-426627da-0ab8-416c-b10b-2bde5213a530
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649872194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2649872194
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2665687929
Short name T540
Test name
Test status
Simulation time 165944910789 ps
CPU time 101.7 seconds
Started Apr 30 03:03:49 PM PDT 24
Finished Apr 30 03:05:31 PM PDT 24
Peak memory 202100 kb
Host smart-d0d8f783-0be9-4afc-8eda-901624c0a451
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665687929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2665687929
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.2563160638
Short name T586
Test name
Test status
Simulation time 613403044839 ps
CPU time 351.38 seconds
Started Apr 30 03:03:48 PM PDT 24
Finished Apr 30 03:09:40 PM PDT 24
Peak memory 202268 kb
Host smart-465f301c-369f-4e42-ba98-bbb4552d2c98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563160638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.2563160638
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2192001077
Short name T212
Test name
Test status
Simulation time 97817557683 ps
CPU time 523.89 seconds
Started Apr 30 03:03:41 PM PDT 24
Finished Apr 30 03:12:26 PM PDT 24
Peak memory 202688 kb
Host smart-74880bb6-27d1-430e-8e05-5c5f18eaa560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192001077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2192001077
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3189289180
Short name T391
Test name
Test status
Simulation time 34570605097 ps
CPU time 82.77 seconds
Started Apr 30 03:03:43 PM PDT 24
Finished Apr 30 03:05:06 PM PDT 24
Peak memory 202092 kb
Host smart-fd057588-85c5-4ecb-a9e4-d4c6d1a1cb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189289180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3189289180
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1600842014
Short name T750
Test name
Test status
Simulation time 4726656976 ps
CPU time 6.49 seconds
Started Apr 30 03:03:44 PM PDT 24
Finished Apr 30 03:03:51 PM PDT 24
Peak memory 202068 kb
Host smart-459e8ddd-91f9-4ebf-9298-8722c1f17356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600842014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1600842014
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.2539743197
Short name T604
Test name
Test status
Simulation time 5793980911 ps
CPU time 14.54 seconds
Started Apr 30 03:03:42 PM PDT 24
Finished Apr 30 03:03:57 PM PDT 24
Peak memory 202092 kb
Host smart-49012f23-8baf-4125-b2e6-6cd2709d912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539743197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.2539743197
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1610064290
Short name T406
Test name
Test status
Simulation time 471255416 ps
CPU time 1.15 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:03:52 PM PDT 24
Peak memory 202016 kb
Host smart-c0db14fe-7e9a-47f6-8c80-542defe7385e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610064290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1610064290
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3648167722
Short name T244
Test name
Test status
Simulation time 172384979646 ps
CPU time 120.29 seconds
Started Apr 30 03:03:49 PM PDT 24
Finished Apr 30 03:05:50 PM PDT 24
Peak memory 202368 kb
Host smart-c6434f0e-e6b4-4e12-b9ad-4e85f539a15e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648167722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3648167722
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1323661771
Short name T603
Test name
Test status
Simulation time 331780689206 ps
CPU time 425.71 seconds
Started Apr 30 03:03:43 PM PDT 24
Finished Apr 30 03:10:50 PM PDT 24
Peak memory 202320 kb
Host smart-ffc90582-e896-4fc2-a2a4-bbd3c62a5097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323661771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1323661771
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2793920365
Short name T239
Test name
Test status
Simulation time 324657692802 ps
CPU time 376.6 seconds
Started Apr 30 03:03:42 PM PDT 24
Finished Apr 30 03:09:59 PM PDT 24
Peak memory 202324 kb
Host smart-732f6e69-c0c2-4142-ad23-ce1acc47f0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793920365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2793920365
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3824621030
Short name T389
Test name
Test status
Simulation time 327298801437 ps
CPU time 801.9 seconds
Started Apr 30 03:03:48 PM PDT 24
Finished Apr 30 03:17:11 PM PDT 24
Peak memory 202392 kb
Host smart-b8e1d734-27d2-40ac-a9a9-e024fa456460
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824621030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3824621030
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2843035232
Short name T226
Test name
Test status
Simulation time 336689567423 ps
CPU time 382.5 seconds
Started Apr 30 03:03:43 PM PDT 24
Finished Apr 30 03:10:06 PM PDT 24
Peak memory 202376 kb
Host smart-2a1bc8f2-9376-47b4-a43e-483376f1feb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843035232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2843035232
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2229038660
Short name T152
Test name
Test status
Simulation time 320965584098 ps
CPU time 175.59 seconds
Started Apr 30 03:03:48 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 202256 kb
Host smart-2ef76812-574c-457f-8a38-63e693b907c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229038660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2229038660
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.406711098
Short name T658
Test name
Test status
Simulation time 336080553211 ps
CPU time 186.27 seconds
Started Apr 30 03:03:42 PM PDT 24
Finished Apr 30 03:06:48 PM PDT 24
Peak memory 202340 kb
Host smart-75e42878-1215-4511-9868-c3b70b543613
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406711098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.406711098
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3638890538
Short name T401
Test name
Test status
Simulation time 383323374997 ps
CPU time 318.62 seconds
Started Apr 30 03:03:47 PM PDT 24
Finished Apr 30 03:09:07 PM PDT 24
Peak memory 202316 kb
Host smart-f0e1b2b5-ff13-4c40-9eeb-e4785bb66dfe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638890538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3638890538
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2606483832
Short name T435
Test name
Test status
Simulation time 83933678906 ps
CPU time 404.86 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:10:35 PM PDT 24
Peak memory 202652 kb
Host smart-a441928f-7784-4769-8223-a51c02a897bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606483832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2606483832
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.4114926203
Short name T580
Test name
Test status
Simulation time 35835200656 ps
CPU time 84.31 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:05:15 PM PDT 24
Peak memory 202132 kb
Host smart-32d84326-c2e0-42eb-a453-93ea85c5b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114926203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.4114926203
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3870067717
Short name T543
Test name
Test status
Simulation time 3752801094 ps
CPU time 2.83 seconds
Started Apr 30 03:03:41 PM PDT 24
Finished Apr 30 03:03:44 PM PDT 24
Peak memory 202084 kb
Host smart-1df37bcb-93b7-40fa-baf7-481dea79c43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870067717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3870067717
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1000971774
Short name T635
Test name
Test status
Simulation time 5744126555 ps
CPU time 6.96 seconds
Started Apr 30 03:03:48 PM PDT 24
Finished Apr 30 03:03:55 PM PDT 24
Peak memory 202160 kb
Host smart-5c633518-88ec-4548-b2eb-6b6282714e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000971774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1000971774
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3476556487
Short name T1
Test name
Test status
Simulation time 191474127043 ps
CPU time 199.81 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:07:11 PM PDT 24
Peak memory 202376 kb
Host smart-78756652-01da-4270-9f64-69c7850b4d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476556487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3476556487
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1166254369
Short name T17
Test name
Test status
Simulation time 114281518043 ps
CPU time 168.35 seconds
Started Apr 30 03:03:49 PM PDT 24
Finished Apr 30 03:06:38 PM PDT 24
Peak memory 211048 kb
Host smart-1c184399-86cf-4737-8259-3e2824ab0426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166254369 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1166254369
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.462493724
Short name T493
Test name
Test status
Simulation time 549938367 ps
CPU time 0.77 seconds
Started Apr 30 03:03:57 PM PDT 24
Finished Apr 30 03:03:59 PM PDT 24
Peak memory 201964 kb
Host smart-87b4f28a-6b7d-4e77-acbf-e876947eb995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462493724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.462493724
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3527381105
Short name T256
Test name
Test status
Simulation time 163853624997 ps
CPU time 186 seconds
Started Apr 30 03:03:52 PM PDT 24
Finished Apr 30 03:06:58 PM PDT 24
Peak memory 202280 kb
Host smart-1be930fd-216f-4ddd-b94a-09ce2e898faf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527381105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3527381105
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.4238828351
Short name T789
Test name
Test status
Simulation time 328731809249 ps
CPU time 190.9 seconds
Started Apr 30 03:03:49 PM PDT 24
Finished Apr 30 03:07:01 PM PDT 24
Peak memory 202300 kb
Host smart-2b947bf1-962b-49a9-b127-34288c9510bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238828351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.4238828351
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2217574503
Short name T655
Test name
Test status
Simulation time 170096919359 ps
CPU time 404.81 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:10:35 PM PDT 24
Peak memory 202316 kb
Host smart-953a641b-eb35-4a47-9201-2347ef1b4525
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217574503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2217574503
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2787765905
Short name T797
Test name
Test status
Simulation time 496071194804 ps
CPU time 295.86 seconds
Started Apr 30 03:03:49 PM PDT 24
Finished Apr 30 03:08:46 PM PDT 24
Peak memory 202332 kb
Host smart-d91c3eea-6421-42c6-93f3-651bca822f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787765905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2787765905
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1994798458
Short name T481
Test name
Test status
Simulation time 490127921218 ps
CPU time 231.8 seconds
Started Apr 30 03:03:52 PM PDT 24
Finished Apr 30 03:07:45 PM PDT 24
Peak memory 202232 kb
Host smart-d30df5b9-967f-4f07-bce4-a0a65b781d86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994798458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1994798458
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.4108665450
Short name T354
Test name
Test status
Simulation time 568587202381 ps
CPU time 1271.57 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:25:02 PM PDT 24
Peak memory 202396 kb
Host smart-79542770-bdf4-40bc-a1e7-84f8b1e58495
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108665450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.4108665450
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.109085127
Short name T369
Test name
Test status
Simulation time 195156019925 ps
CPU time 446.77 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:11:18 PM PDT 24
Peak memory 202328 kb
Host smart-088bc2ab-53f8-40d8-9cb5-108692fb57ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109085127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.109085127
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4117858199
Short name T362
Test name
Test status
Simulation time 100559330844 ps
CPU time 387.75 seconds
Started Apr 30 03:03:52 PM PDT 24
Finished Apr 30 03:10:21 PM PDT 24
Peak memory 202668 kb
Host smart-ed3ef8a8-7327-4c0c-b3c7-589cd94449db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117858199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4117858199
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2670891148
Short name T796
Test name
Test status
Simulation time 30780056465 ps
CPU time 18.87 seconds
Started Apr 30 03:03:54 PM PDT 24
Finished Apr 30 03:04:13 PM PDT 24
Peak memory 202088 kb
Host smart-0e9ffc27-9991-476c-9244-8764aef9cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670891148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2670891148
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3479795863
Short name T190
Test name
Test status
Simulation time 4637389005 ps
CPU time 3.59 seconds
Started Apr 30 03:03:49 PM PDT 24
Finished Apr 30 03:03:53 PM PDT 24
Peak memory 202056 kb
Host smart-e5cfdb6e-0371-4fa0-af6f-793bc60f4747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479795863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3479795863
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.523744259
Short name T632
Test name
Test status
Simulation time 5832365711 ps
CPU time 4.41 seconds
Started Apr 30 03:03:51 PM PDT 24
Finished Apr 30 03:03:57 PM PDT 24
Peak memory 202176 kb
Host smart-c2c58153-8442-4971-88e3-e989336442ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523744259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.523744259
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.625568137
Short name T617
Test name
Test status
Simulation time 356391209182 ps
CPU time 930.23 seconds
Started Apr 30 03:03:51 PM PDT 24
Finished Apr 30 03:19:22 PM PDT 24
Peak memory 213120 kb
Host smart-ec1770d5-ae35-44c5-b1b2-240f414d9245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625568137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
625568137
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1861371112
Short name T23
Test name
Test status
Simulation time 329171236881 ps
CPU time 133.55 seconds
Started Apr 30 03:03:50 PM PDT 24
Finished Apr 30 03:06:04 PM PDT 24
Peak memory 210660 kb
Host smart-44c29c05-0320-48af-9aa2-f1281dd20aa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861371112 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1861371112
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2419592268
Short name T432
Test name
Test status
Simulation time 444511822 ps
CPU time 1.68 seconds
Started Apr 30 03:04:09 PM PDT 24
Finished Apr 30 03:04:12 PM PDT 24
Peak memory 201960 kb
Host smart-9d5c60cf-5423-4589-825d-154562a5b9dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419592268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2419592268
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1515231606
Short name T348
Test name
Test status
Simulation time 546696358292 ps
CPU time 306.31 seconds
Started Apr 30 03:03:58 PM PDT 24
Finished Apr 30 03:09:05 PM PDT 24
Peak memory 202324 kb
Host smart-43ca672f-970e-4cd9-a3fa-9a91364f65ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515231606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1515231606
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.749504271
Short name T84
Test name
Test status
Simulation time 172422012411 ps
CPU time 368.74 seconds
Started Apr 30 03:04:00 PM PDT 24
Finished Apr 30 03:10:09 PM PDT 24
Peak memory 202248 kb
Host smart-726d2cde-e54a-4b81-a2af-3df577aacebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749504271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.749504271
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1475669726
Short name T562
Test name
Test status
Simulation time 330814652200 ps
CPU time 747.47 seconds
Started Apr 30 03:03:59 PM PDT 24
Finished Apr 30 03:16:28 PM PDT 24
Peak memory 202216 kb
Host smart-6d0d475a-1092-402a-b871-d580d47cca73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475669726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1475669726
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3299363701
Short name T283
Test name
Test status
Simulation time 180642813966 ps
CPU time 77.8 seconds
Started Apr 30 03:03:58 PM PDT 24
Finished Apr 30 03:05:17 PM PDT 24
Peak memory 202236 kb
Host smart-442f5b44-5ca9-40c9-ab41-61a80edb89f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299363701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3299363701
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.3035071893
Short name T666
Test name
Test status
Simulation time 393000708126 ps
CPU time 895.55 seconds
Started Apr 30 03:03:57 PM PDT 24
Finished Apr 30 03:18:53 PM PDT 24
Peak memory 202324 kb
Host smart-3e809274-d268-452a-9ebf-9d3f1a2439cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035071893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.3035071893
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.3826262977
Short name T649
Test name
Test status
Simulation time 88194169293 ps
CPU time 335.8 seconds
Started Apr 30 03:03:59 PM PDT 24
Finished Apr 30 03:09:36 PM PDT 24
Peak memory 202668 kb
Host smart-10292807-4438-4f42-a32d-8f748490c501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826262977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.3826262977
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3594978369
Short name T477
Test name
Test status
Simulation time 40633378388 ps
CPU time 90.06 seconds
Started Apr 30 03:04:00 PM PDT 24
Finished Apr 30 03:05:31 PM PDT 24
Peak memory 202104 kb
Host smart-6afe4924-b083-4ff3-a4cf-851431e3067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594978369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3594978369
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.140974463
Short name T502
Test name
Test status
Simulation time 4939291254 ps
CPU time 12.67 seconds
Started Apr 30 03:03:59 PM PDT 24
Finished Apr 30 03:04:12 PM PDT 24
Peak memory 202108 kb
Host smart-833331b9-6c78-4e1a-b460-0ab0555ac1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140974463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.140974463
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2197867496
Short name T572
Test name
Test status
Simulation time 5652905873 ps
CPU time 6.85 seconds
Started Apr 30 03:04:01 PM PDT 24
Finished Apr 30 03:04:08 PM PDT 24
Peak memory 202060 kb
Host smart-7b0aeac0-b8fc-4a26-937a-b3ddd75a56c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197867496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2197867496
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.4142651387
Short name T757
Test name
Test status
Simulation time 535716150566 ps
CPU time 1091.45 seconds
Started Apr 30 03:03:58 PM PDT 24
Finished Apr 30 03:22:10 PM PDT 24
Peak memory 202324 kb
Host smart-b06ed832-cef4-427d-ad34-8f4b0a3780f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142651387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.4142651387
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1178629574
Short name T318
Test name
Test status
Simulation time 57198220985 ps
CPU time 83.94 seconds
Started Apr 30 03:03:57 PM PDT 24
Finished Apr 30 03:05:22 PM PDT 24
Peak memory 202480 kb
Host smart-9c7f36c7-bbce-4723-8581-80ff676c4fc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178629574 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1178629574
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2319077603
Short name T781
Test name
Test status
Simulation time 434563055 ps
CPU time 1.64 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:04:08 PM PDT 24
Peak memory 202040 kb
Host smart-82623575-a36b-4db3-a777-0301a3603915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319077603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2319077603
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.797389459
Short name T728
Test name
Test status
Simulation time 161826253163 ps
CPU time 56.06 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:05:02 PM PDT 24
Peak memory 202332 kb
Host smart-1f3148aa-414f-47be-969f-75b1b146399f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797389459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.797389459
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.608993344
Short name T325
Test name
Test status
Simulation time 165043851959 ps
CPU time 191.64 seconds
Started Apr 30 03:04:09 PM PDT 24
Finished Apr 30 03:07:21 PM PDT 24
Peak memory 202312 kb
Host smart-dd8634e4-d611-4825-a35f-16b4b404c0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608993344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.608993344
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.849565320
Short name T335
Test name
Test status
Simulation time 500258013896 ps
CPU time 613.47 seconds
Started Apr 30 03:04:05 PM PDT 24
Finished Apr 30 03:14:19 PM PDT 24
Peak memory 202204 kb
Host smart-a3596642-4795-4325-b11e-abce9ef64052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849565320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.849565320
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2376176474
Short name T29
Test name
Test status
Simulation time 330995201112 ps
CPU time 388.84 seconds
Started Apr 30 03:04:10 PM PDT 24
Finished Apr 30 03:10:40 PM PDT 24
Peak memory 202244 kb
Host smart-138009ec-0cea-4bff-90db-6386d6d895ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376176474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2376176474
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.753067526
Short name T536
Test name
Test status
Simulation time 169444636620 ps
CPU time 201.54 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:07:28 PM PDT 24
Peak memory 202408 kb
Host smart-31139949-2272-4914-9c53-7d8feba15994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753067526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.753067526
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2494045994
Short name T565
Test name
Test status
Simulation time 494417637338 ps
CPU time 1059.9 seconds
Started Apr 30 03:04:09 PM PDT 24
Finished Apr 30 03:21:50 PM PDT 24
Peak memory 202244 kb
Host smart-3b4668a8-ec75-4c7b-9aa8-74bccf0f5cb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494045994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2494045994
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.131759279
Short name T293
Test name
Test status
Simulation time 178043858061 ps
CPU time 200.79 seconds
Started Apr 30 03:04:08 PM PDT 24
Finished Apr 30 03:07:30 PM PDT 24
Peak memory 202308 kb
Host smart-2eda382a-ba7e-4f76-8f4f-974c590065a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131759279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.131759279
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3513973781
Short name T495
Test name
Test status
Simulation time 407638008895 ps
CPU time 227.15 seconds
Started Apr 30 03:04:07 PM PDT 24
Finished Apr 30 03:07:55 PM PDT 24
Peak memory 202300 kb
Host smart-e70db014-b169-4dc8-9d08-36a0696618fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513973781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3513973781
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2248645543
Short name T759
Test name
Test status
Simulation time 23657004198 ps
CPU time 56.69 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:05:03 PM PDT 24
Peak memory 202156 kb
Host smart-63ce6c59-0f37-4487-9ab2-c84d63efa452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248645543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2248645543
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2760560405
Short name T576
Test name
Test status
Simulation time 2794717113 ps
CPU time 2.39 seconds
Started Apr 30 03:04:08 PM PDT 24
Finished Apr 30 03:04:11 PM PDT 24
Peak memory 202108 kb
Host smart-89149ef1-a019-40c7-ab93-04838302cd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760560405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2760560405
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.371765870
Short name T752
Test name
Test status
Simulation time 5774261459 ps
CPU time 4.76 seconds
Started Apr 30 03:04:08 PM PDT 24
Finished Apr 30 03:04:13 PM PDT 24
Peak memory 202112 kb
Host smart-7fae8c13-f631-4d05-9a4a-7fdf160739d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371765870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.371765870
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3153877813
Short name T319
Test name
Test status
Simulation time 233263428441 ps
CPU time 395.53 seconds
Started Apr 30 03:04:06 PM PDT 24
Finished Apr 30 03:10:42 PM PDT 24
Peak memory 202612 kb
Host smart-126047a9-1c2f-4e94-9d42-20cc0dfc61ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153877813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3153877813
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.618762634
Short name T352
Test name
Test status
Simulation time 90565361282 ps
CPU time 54 seconds
Started Apr 30 03:04:09 PM PDT 24
Finished Apr 30 03:05:04 PM PDT 24
Peak memory 210656 kb
Host smart-ef0c5bfb-7c69-4326-a9fb-9d2437ca70da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618762634 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.618762634
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1089284097
Short name T467
Test name
Test status
Simulation time 525015649 ps
CPU time 0.89 seconds
Started Apr 30 03:04:21 PM PDT 24
Finished Apr 30 03:04:23 PM PDT 24
Peak memory 201968 kb
Host smart-1a4d8477-15f5-4167-aede-154a94fee0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089284097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1089284097
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3173433390
Short name T763
Test name
Test status
Simulation time 512590175532 ps
CPU time 370.52 seconds
Started Apr 30 03:04:14 PM PDT 24
Finished Apr 30 03:10:25 PM PDT 24
Peak memory 202248 kb
Host smart-576ab03e-f100-4fec-811a-c174bd4a7cc9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173433390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3173433390
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.217173577
Short name T396
Test name
Test status
Simulation time 329968423407 ps
CPU time 191.42 seconds
Started Apr 30 03:04:08 PM PDT 24
Finished Apr 30 03:07:20 PM PDT 24
Peak memory 202308 kb
Host smart-689641e3-f94a-4db5-a01d-33125b322388
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217173577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.217173577
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1230647407
Short name T483
Test name
Test status
Simulation time 488093134859 ps
CPU time 328.12 seconds
Started Apr 30 03:04:07 PM PDT 24
Finished Apr 30 03:09:36 PM PDT 24
Peak memory 202280 kb
Host smart-1e035d63-0116-490c-8d72-d6f00071976b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230647407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1230647407
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.914878966
Short name T254
Test name
Test status
Simulation time 381448024588 ps
CPU time 212.06 seconds
Started Apr 30 03:04:21 PM PDT 24
Finished Apr 30 03:07:54 PM PDT 24
Peak memory 202340 kb
Host smart-f7d70f34-f88c-4aed-a61f-552255570ba6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914878966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_
wakeup.914878966
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.3013921139
Short name T720
Test name
Test status
Simulation time 194022714555 ps
CPU time 246.49 seconds
Started Apr 30 03:04:13 PM PDT 24
Finished Apr 30 03:08:20 PM PDT 24
Peak memory 202276 kb
Host smart-5b98e28d-843a-4bb5-be50-77e25915812e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013921139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.3013921139
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.453477642
Short name T178
Test name
Test status
Simulation time 80503770920 ps
CPU time 285.12 seconds
Started Apr 30 03:04:21 PM PDT 24
Finished Apr 30 03:09:07 PM PDT 24
Peak memory 202612 kb
Host smart-f625342a-d02b-431c-add4-012b3f112523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453477642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.453477642
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.4121815912
Short name T601
Test name
Test status
Simulation time 40387442639 ps
CPU time 24.81 seconds
Started Apr 30 03:04:14 PM PDT 24
Finished Apr 30 03:04:39 PM PDT 24
Peak memory 202128 kb
Host smart-1d605776-2118-493b-9a2b-b4d7febd6d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121815912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.4121815912
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3349668569
Short name T423
Test name
Test status
Simulation time 5147619203 ps
CPU time 12.42 seconds
Started Apr 30 03:04:14 PM PDT 24
Finished Apr 30 03:04:27 PM PDT 24
Peak memory 202060 kb
Host smart-128cc026-591b-4646-a61a-df710efecdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349668569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3349668569
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1841127903
Short name T778
Test name
Test status
Simulation time 6259052559 ps
CPU time 4.3 seconds
Started Apr 30 03:04:10 PM PDT 24
Finished Apr 30 03:04:15 PM PDT 24
Peak memory 202092 kb
Host smart-fa63e8c3-9cad-47a8-807e-7ccbcec93318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841127903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1841127903
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3429282887
Short name T299
Test name
Test status
Simulation time 351146561054 ps
CPU time 418.37 seconds
Started Apr 30 03:04:14 PM PDT 24
Finished Apr 30 03:11:13 PM PDT 24
Peak memory 202264 kb
Host smart-9c6f4c64-9626-4b84-9092-50f88cb68f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429282887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3429282887
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.886192882
Short name T21
Test name
Test status
Simulation time 141199316656 ps
CPU time 110.63 seconds
Started Apr 30 03:04:14 PM PDT 24
Finished Apr 30 03:06:05 PM PDT 24
Peak memory 210932 kb
Host smart-727a3bab-d2b1-4b75-89f2-0fc1d30a878f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886192882 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.886192882
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1675701401
Short name T180
Test name
Test status
Simulation time 477762794 ps
CPU time 1.78 seconds
Started Apr 30 03:04:19 PM PDT 24
Finished Apr 30 03:04:22 PM PDT 24
Peak memory 201952 kb
Host smart-8b683aca-0fb7-46ee-9d09-7f43c4be51c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675701401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1675701401
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1039184419
Short name T347
Test name
Test status
Simulation time 512721048547 ps
CPU time 373.45 seconds
Started Apr 30 03:04:15 PM PDT 24
Finished Apr 30 03:10:29 PM PDT 24
Peak memory 202324 kb
Host smart-f539eef4-cee2-4534-803e-05195b40e050
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039184419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1039184419
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.548953930
Short name T237
Test name
Test status
Simulation time 168738252704 ps
CPU time 107.58 seconds
Started Apr 30 03:04:20 PM PDT 24
Finished Apr 30 03:06:08 PM PDT 24
Peak memory 202264 kb
Host smart-5bffbffd-e4ce-49cb-b3a2-0bf3ec518812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548953930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.548953930
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.562745991
Short name T24
Test name
Test status
Simulation time 166861649080 ps
CPU time 189.39 seconds
Started Apr 30 03:04:16 PM PDT 24
Finished Apr 30 03:07:25 PM PDT 24
Peak memory 202364 kb
Host smart-6adac765-ef90-48aa-9d09-34deea51ab22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562745991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.562745991
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.864214681
Short name T607
Test name
Test status
Simulation time 494378197911 ps
CPU time 549.36 seconds
Started Apr 30 03:04:21 PM PDT 24
Finished Apr 30 03:13:31 PM PDT 24
Peak memory 202236 kb
Host smart-b4ecb256-d565-4b88-bfbb-31db84f3406b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=864214681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.864214681
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.4230611978
Short name T92
Test name
Test status
Simulation time 330206063485 ps
CPU time 189.88 seconds
Started Apr 30 03:04:14 PM PDT 24
Finished Apr 30 03:07:24 PM PDT 24
Peak memory 202400 kb
Host smart-2c20a947-a399-4b56-89b9-8a7f7907d428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230611978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.4230611978
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1505567627
Short name T697
Test name
Test status
Simulation time 480132456891 ps
CPU time 1082.56 seconds
Started Apr 30 03:04:13 PM PDT 24
Finished Apr 30 03:22:16 PM PDT 24
Peak memory 202312 kb
Host smart-f04116b0-ffce-4cdf-9697-1fec9edce557
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505567627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1505567627
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3465890656
Short name T742
Test name
Test status
Simulation time 186325436562 ps
CPU time 113.73 seconds
Started Apr 30 03:04:15 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 202272 kb
Host smart-e8c9f8ea-3b6d-4142-8197-ff52a4699139
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465890656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3465890656
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.148220853
Short name T560
Test name
Test status
Simulation time 580819033428 ps
CPU time 346.69 seconds
Started Apr 30 03:04:15 PM PDT 24
Finished Apr 30 03:10:03 PM PDT 24
Peak memory 202272 kb
Host smart-06f153dd-979a-4b54-84c9-ed7a7722d733
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148220853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.148220853
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3105830448
Short name T541
Test name
Test status
Simulation time 105903026555 ps
CPU time 457.99 seconds
Started Apr 30 03:04:23 PM PDT 24
Finished Apr 30 03:12:01 PM PDT 24
Peak memory 202632 kb
Host smart-c7a98cbf-af02-443e-8e59-04f0b12d5463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105830448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3105830448
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2187466743
Short name T701
Test name
Test status
Simulation time 42860739220 ps
CPU time 95.07 seconds
Started Apr 30 03:04:25 PM PDT 24
Finished Apr 30 03:06:00 PM PDT 24
Peak memory 202100 kb
Host smart-7f7c5adf-1e09-4a2d-b5db-ca09d85ebde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187466743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2187466743
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3819764646
Short name T176
Test name
Test status
Simulation time 3710072390 ps
CPU time 9.29 seconds
Started Apr 30 03:04:21 PM PDT 24
Finished Apr 30 03:04:31 PM PDT 24
Peak memory 202136 kb
Host smart-3aa22e3f-b370-4f86-8f35-6549cb5642d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819764646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3819764646
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.3649373383
Short name T498
Test name
Test status
Simulation time 5743851770 ps
CPU time 13.14 seconds
Started Apr 30 03:04:14 PM PDT 24
Finished Apr 30 03:04:28 PM PDT 24
Peak memory 202040 kb
Host smart-bc8b5e6b-2131-4253-80f5-8c3df400341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649373383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.3649373383
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2558949440
Short name T690
Test name
Test status
Simulation time 372014214222 ps
CPU time 450.17 seconds
Started Apr 30 03:04:19 PM PDT 24
Finished Apr 30 03:11:50 PM PDT 24
Peak memory 202292 kb
Host smart-695e2693-903e-401c-95ca-66c86a37cce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558949440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2558949440
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3718386630
Short name T786
Test name
Test status
Simulation time 339538959 ps
CPU time 0.78 seconds
Started Apr 30 03:04:29 PM PDT 24
Finished Apr 30 03:04:30 PM PDT 24
Peak memory 201972 kb
Host smart-7643fa12-39e0-4f3b-bed4-90dfe491e88c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718386630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3718386630
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1278166387
Short name T741
Test name
Test status
Simulation time 163459482930 ps
CPU time 205.91 seconds
Started Apr 30 03:04:21 PM PDT 24
Finished Apr 30 03:07:48 PM PDT 24
Peak memory 202240 kb
Host smart-f0d91627-ab10-4113-b02e-e90e72245153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278166387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1278166387
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2369189256
Short name T400
Test name
Test status
Simulation time 155949147392 ps
CPU time 364.46 seconds
Started Apr 30 03:04:20 PM PDT 24
Finished Apr 30 03:10:25 PM PDT 24
Peak memory 202176 kb
Host smart-d581b742-af7f-4117-aa19-f94c00bcd8fe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369189256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2369189256
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.237328584
Short name T699
Test name
Test status
Simulation time 322409788422 ps
CPU time 78.29 seconds
Started Apr 30 03:04:25 PM PDT 24
Finished Apr 30 03:05:44 PM PDT 24
Peak memory 202372 kb
Host smart-8d94c808-6a0f-44fb-b3f3-031a64969bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237328584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.237328584
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2147240709
Short name T484
Test name
Test status
Simulation time 330874513837 ps
CPU time 388.31 seconds
Started Apr 30 03:04:19 PM PDT 24
Finished Apr 30 03:10:48 PM PDT 24
Peak memory 202256 kb
Host smart-33e35bad-3f8b-47be-bc71-f0087e98d13b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147240709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2147240709
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2103134147
Short name T161
Test name
Test status
Simulation time 396980399518 ps
CPU time 83.4 seconds
Started Apr 30 03:04:24 PM PDT 24
Finished Apr 30 03:05:47 PM PDT 24
Peak memory 202340 kb
Host smart-7434440b-c9df-4550-919b-08cad05fa6ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103134147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2103134147
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.131825678
Short name T570
Test name
Test status
Simulation time 198542380864 ps
CPU time 110.28 seconds
Started Apr 30 03:04:20 PM PDT 24
Finished Apr 30 03:06:11 PM PDT 24
Peak memory 202332 kb
Host smart-1abfce53-0385-4cb5-9837-5fc2539e0d01
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131825678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.131825678
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3386114732
Short name T770
Test name
Test status
Simulation time 122545642668 ps
CPU time 554.96 seconds
Started Apr 30 03:04:28 PM PDT 24
Finished Apr 30 03:13:43 PM PDT 24
Peak memory 202636 kb
Host smart-52c1a1b6-3e4e-46d7-9906-7e342ae785ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386114732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3386114732
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2263465012
Short name T712
Test name
Test status
Simulation time 35929484002 ps
CPU time 84.39 seconds
Started Apr 30 03:04:28 PM PDT 24
Finished Apr 30 03:05:53 PM PDT 24
Peak memory 202136 kb
Host smart-49bc34a8-7c07-488f-9124-74180a5362ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263465012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2263465012
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1865390456
Short name T506
Test name
Test status
Simulation time 4340013554 ps
CPU time 5.59 seconds
Started Apr 30 03:04:22 PM PDT 24
Finished Apr 30 03:04:28 PM PDT 24
Peak memory 202108 kb
Host smart-d9bffd30-03ba-46c4-a0d1-5d9a891661db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865390456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1865390456
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1126809859
Short name T412
Test name
Test status
Simulation time 5678602406 ps
CPU time 14.34 seconds
Started Apr 30 03:04:20 PM PDT 24
Finished Apr 30 03:04:35 PM PDT 24
Peak memory 202116 kb
Host smart-20354ecf-192e-4ce5-8422-a88d7479de2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126809859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1126809859
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.3397256509
Short name T287
Test name
Test status
Simulation time 503264595321 ps
CPU time 1150.29 seconds
Started Apr 30 03:04:27 PM PDT 24
Finished Apr 30 03:23:38 PM PDT 24
Peak memory 202356 kb
Host smart-0c83dee5-7035-4fd5-930a-080af40a59a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397256509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.3397256509
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3224698923
Short name T37
Test name
Test status
Simulation time 61178904118 ps
CPU time 134.07 seconds
Started Apr 30 03:04:29 PM PDT 24
Finished Apr 30 03:06:44 PM PDT 24
Peak memory 210748 kb
Host smart-bb70ad77-05bb-4d13-a6f3-20deb995c394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224698923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3224698923
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3211227800
Short name T679
Test name
Test status
Simulation time 327848747 ps
CPU time 0.9 seconds
Started Apr 30 03:04:35 PM PDT 24
Finished Apr 30 03:04:36 PM PDT 24
Peak memory 201944 kb
Host smart-8f07dc06-2c5b-497d-a4cf-e5786975f0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211227800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3211227800
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2993240369
Short name T735
Test name
Test status
Simulation time 354273496261 ps
CPU time 837.47 seconds
Started Apr 30 03:04:27 PM PDT 24
Finished Apr 30 03:18:25 PM PDT 24
Peak memory 202244 kb
Host smart-6bf27389-d43f-4fee-b6b9-b9fbad159e1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993240369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2993240369
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4073899178
Short name T196
Test name
Test status
Simulation time 165956618913 ps
CPU time 413.31 seconds
Started Apr 30 03:04:27 PM PDT 24
Finished Apr 30 03:11:21 PM PDT 24
Peak memory 202300 kb
Host smart-b667ed32-48ec-4438-ac67-e44b2e8d1004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073899178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4073899178
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1015643091
Short name T696
Test name
Test status
Simulation time 496543987505 ps
CPU time 1239.6 seconds
Started Apr 30 03:04:30 PM PDT 24
Finished Apr 30 03:25:10 PM PDT 24
Peak memory 202304 kb
Host smart-2050d964-53d0-43d7-ad05-3ad079b302be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015643091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1015643091
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1227985248
Short name T278
Test name
Test status
Simulation time 159764297499 ps
CPU time 104.6 seconds
Started Apr 30 03:04:28 PM PDT 24
Finished Apr 30 03:06:13 PM PDT 24
Peak memory 202348 kb
Host smart-aee94809-96d5-44a9-aa3c-e20ca60f2a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227985248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1227985248
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1437172003
Short name T153
Test name
Test status
Simulation time 486943518304 ps
CPU time 1174.11 seconds
Started Apr 30 03:04:28 PM PDT 24
Finished Apr 30 03:24:03 PM PDT 24
Peak memory 202244 kb
Host smart-1c697bfc-a5ec-4222-ad01-7531139694a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437172003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1437172003
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3531440727
Short name T30
Test name
Test status
Simulation time 408204802258 ps
CPU time 453.03 seconds
Started Apr 30 03:04:29 PM PDT 24
Finished Apr 30 03:12:02 PM PDT 24
Peak memory 202224 kb
Host smart-97e90ace-1b5a-4ea8-a185-c9ce0906ca25
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531440727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3531440727
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2282031258
Short name T628
Test name
Test status
Simulation time 98580689105 ps
CPU time 375.07 seconds
Started Apr 30 03:04:37 PM PDT 24
Finished Apr 30 03:10:53 PM PDT 24
Peak memory 202712 kb
Host smart-bc9561d5-4b72-4873-b4c4-ab18ab29b0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282031258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2282031258
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1000035333
Short name T468
Test name
Test status
Simulation time 43783407593 ps
CPU time 47.8 seconds
Started Apr 30 03:04:36 PM PDT 24
Finished Apr 30 03:05:24 PM PDT 24
Peak memory 202108 kb
Host smart-73bd73b5-1d95-4fd1-b4e5-486848dda8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000035333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1000035333
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3300914407
Short name T404
Test name
Test status
Simulation time 3174690360 ps
CPU time 4.13 seconds
Started Apr 30 03:04:28 PM PDT 24
Finished Apr 30 03:04:33 PM PDT 24
Peak memory 201288 kb
Host smart-9ec0d00c-9391-494c-913c-ac5d12d5d2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300914407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3300914407
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4254513787
Short name T99
Test name
Test status
Simulation time 5866713601 ps
CPU time 6.09 seconds
Started Apr 30 03:04:29 PM PDT 24
Finished Apr 30 03:04:35 PM PDT 24
Peak memory 202076 kb
Host smart-437599af-2908-44b6-a668-85b6770fd570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254513787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4254513787
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3342874431
Short name T332
Test name
Test status
Simulation time 334142752269 ps
CPU time 191.25 seconds
Started Apr 30 03:04:36 PM PDT 24
Finished Apr 30 03:07:48 PM PDT 24
Peak memory 202252 kb
Host smart-31effaef-267d-4a9c-8781-935c8ce0167b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342874431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3342874431
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2155387030
Short name T782
Test name
Test status
Simulation time 117512949862 ps
CPU time 87.36 seconds
Started Apr 30 03:04:35 PM PDT 24
Finished Apr 30 03:06:03 PM PDT 24
Peak memory 211068 kb
Host smart-a8904c25-c761-4256-a865-52b2a45e4441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155387030 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2155387030
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.1127564469
Short name T413
Test name
Test status
Simulation time 508824507 ps
CPU time 0.87 seconds
Started Apr 30 03:04:41 PM PDT 24
Finished Apr 30 03:04:42 PM PDT 24
Peak memory 201920 kb
Host smart-92412a00-c01b-446b-9615-a6cd64ad8482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127564469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.1127564469
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3052857391
Short name T670
Test name
Test status
Simulation time 536141396904 ps
CPU time 223.64 seconds
Started Apr 30 03:04:37 PM PDT 24
Finished Apr 30 03:08:21 PM PDT 24
Peak memory 202316 kb
Host smart-b5e8df65-58ad-4434-8db2-40e30942a45d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052857391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3052857391
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1543499558
Short name T234
Test name
Test status
Simulation time 163186197577 ps
CPU time 29.25 seconds
Started Apr 30 03:04:36 PM PDT 24
Finished Apr 30 03:05:06 PM PDT 24
Peak memory 202196 kb
Host smart-800eb68a-2b2a-4b3d-b24b-6bffd2768f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543499558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1543499558
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1804216826
Short name T139
Test name
Test status
Simulation time 488563879649 ps
CPU time 267.09 seconds
Started Apr 30 03:04:36 PM PDT 24
Finished Apr 30 03:09:03 PM PDT 24
Peak memory 202284 kb
Host smart-6bbf4386-b102-4c80-92a1-5eac403ba81d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804216826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1804216826
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1879197066
Short name T337
Test name
Test status
Simulation time 162250470765 ps
CPU time 348.28 seconds
Started Apr 30 03:04:34 PM PDT 24
Finished Apr 30 03:10:23 PM PDT 24
Peak memory 202268 kb
Host smart-d5879b7d-0c86-42f8-983b-5d92363aed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879197066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1879197066
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.292453812
Short name T684
Test name
Test status
Simulation time 167903372412 ps
CPU time 386.11 seconds
Started Apr 30 03:04:35 PM PDT 24
Finished Apr 30 03:11:02 PM PDT 24
Peak memory 202196 kb
Host smart-64c5da8f-b039-4376-83db-14089a8b93ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=292453812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.292453812
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3310085074
Short name T355
Test name
Test status
Simulation time 173281061918 ps
CPU time 127.29 seconds
Started Apr 30 03:04:37 PM PDT 24
Finished Apr 30 03:06:45 PM PDT 24
Peak memory 202504 kb
Host smart-b86af108-70da-4d3a-ba2e-c4f591479544
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310085074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3310085074
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1251648770
Short name T721
Test name
Test status
Simulation time 595229422106 ps
CPU time 371.02 seconds
Started Apr 30 03:04:38 PM PDT 24
Finished Apr 30 03:10:49 PM PDT 24
Peak memory 202280 kb
Host smart-60e53feb-4f47-4162-abf7-beb1ec694e84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251648770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1251648770
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3859071490
Short name T46
Test name
Test status
Simulation time 117978427760 ps
CPU time 483.11 seconds
Started Apr 30 03:04:35 PM PDT 24
Finished Apr 30 03:12:39 PM PDT 24
Peak memory 202684 kb
Host smart-b4049db6-b601-4511-988b-f18d26e732d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859071490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3859071490
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1367121770
Short name T433
Test name
Test status
Simulation time 46228272361 ps
CPU time 116.89 seconds
Started Apr 30 03:04:36 PM PDT 24
Finished Apr 30 03:06:34 PM PDT 24
Peak memory 202136 kb
Host smart-ac944a01-322e-4429-8a8e-9679b1e0a80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367121770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1367121770
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.672732233
Short name T598
Test name
Test status
Simulation time 3763352880 ps
CPU time 2.65 seconds
Started Apr 30 03:04:35 PM PDT 24
Finished Apr 30 03:04:38 PM PDT 24
Peak memory 202104 kb
Host smart-2707a53e-2c84-43f3-aa48-468e787cffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672732233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.672732233
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3655491674
Short name T83
Test name
Test status
Simulation time 6015997664 ps
CPU time 4.47 seconds
Started Apr 30 03:04:38 PM PDT 24
Finished Apr 30 03:04:43 PM PDT 24
Peak memory 202176 kb
Host smart-470a4aaf-1efd-4464-80bb-00cade6f546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655491674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3655491674
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3059223770
Short name T6
Test name
Test status
Simulation time 12448908515 ps
CPU time 37.1 seconds
Started Apr 30 03:04:37 PM PDT 24
Finished Apr 30 03:05:15 PM PDT 24
Peak memory 202760 kb
Host smart-c6eab799-a285-4845-bbf4-1acba69058f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059223770 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3059223770
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2709127363
Short name T566
Test name
Test status
Simulation time 486370422 ps
CPU time 1.75 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:02:53 PM PDT 24
Peak memory 201956 kb
Host smart-cba8f72c-5d5f-42f8-85c9-03ed343d5d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709127363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2709127363
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3531745744
Short name T273
Test name
Test status
Simulation time 253845736303 ps
CPU time 72.13 seconds
Started Apr 30 03:02:47 PM PDT 24
Finished Apr 30 03:03:59 PM PDT 24
Peak memory 202312 kb
Host smart-25d6201e-ee7d-468c-bfca-ee8393e289b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531745744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3531745744
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2648783841
Short name T657
Test name
Test status
Simulation time 325371825893 ps
CPU time 346.36 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:08:32 PM PDT 24
Peak memory 202324 kb
Host smart-c7ad117b-b042-45f1-a406-f0fcdcc2a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648783841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2648783841
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1628949552
Short name T260
Test name
Test status
Simulation time 163798538008 ps
CPU time 96.18 seconds
Started Apr 30 03:02:44 PM PDT 24
Finished Apr 30 03:04:21 PM PDT 24
Peak memory 202320 kb
Host smart-f86338c2-746b-4b5f-aae8-a9b94e391150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628949552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1628949552
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.361347047
Short name T420
Test name
Test status
Simulation time 485978364553 ps
CPU time 286.96 seconds
Started Apr 30 03:02:41 PM PDT 24
Finished Apr 30 03:07:29 PM PDT 24
Peak memory 202284 kb
Host smart-c395f7ef-482d-4d41-a91d-a03718d85353
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=361347047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.361347047
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.4128751589
Short name T669
Test name
Test status
Simulation time 334456129993 ps
CPU time 212.4 seconds
Started Apr 30 03:02:50 PM PDT 24
Finished Apr 30 03:06:23 PM PDT 24
Peak memory 202380 kb
Host smart-fa235189-e2fc-4b68-ad5e-1542424bc626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128751589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.4128751589
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2248555017
Short name T644
Test name
Test status
Simulation time 495775668647 ps
CPU time 1051.86 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:20:26 PM PDT 24
Peak memory 202224 kb
Host smart-ffd2f787-0891-415b-9c82-46f465aada7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248555017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2248555017
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1443815476
Short name T141
Test name
Test status
Simulation time 556362081821 ps
CPU time 295.92 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:07:53 PM PDT 24
Peak memory 202296 kb
Host smart-f6514078-6bc1-4f92-a1c5-97f72bf2244f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443815476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1443815476
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2573381061
Short name T402
Test name
Test status
Simulation time 609161644946 ps
CPU time 1495.61 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:27:42 PM PDT 24
Peak memory 202224 kb
Host smart-c6d3d636-9546-4412-9d8f-616613a9c0fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573381061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2573381061
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.859778140
Short name T364
Test name
Test status
Simulation time 91654016133 ps
CPU time 356.52 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:08:43 PM PDT 24
Peak memory 202688 kb
Host smart-e899e66b-6d75-4f98-87ba-015f09f6d28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859778140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.859778140
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3292679451
Short name T561
Test name
Test status
Simulation time 45045445350 ps
CPU time 6.61 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:02:53 PM PDT 24
Peak memory 202084 kb
Host smart-6926a846-39e1-4880-97ed-f7bb1a8e308b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292679451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3292679451
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3265974286
Short name T622
Test name
Test status
Simulation time 3999042722 ps
CPU time 9.89 seconds
Started Apr 30 03:02:47 PM PDT 24
Finished Apr 30 03:02:57 PM PDT 24
Peak memory 202112 kb
Host smart-04b28752-d91c-452f-8d9f-6c7a6c01c2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265974286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3265974286
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2326911689
Short name T77
Test name
Test status
Simulation time 7570353463 ps
CPU time 17.85 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:03:12 PM PDT 24
Peak memory 218872 kb
Host smart-d46d3668-767a-44a0-b7af-4925990b7e91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326911689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2326911689
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.50940462
Short name T775
Test name
Test status
Simulation time 5847904433 ps
CPU time 4.17 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:02:55 PM PDT 24
Peak memory 202128 kb
Host smart-4f30b97f-115a-4744-aa04-219bf9c4242a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50940462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.50940462
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1298797540
Short name T672
Test name
Test status
Simulation time 165839125515 ps
CPU time 373.43 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:09:00 PM PDT 24
Peak memory 202352 kb
Host smart-f2d4063c-eb17-4ecc-954c-ecd194cd039c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298797540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1298797540
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2080681288
Short name T490
Test name
Test status
Simulation time 532355955 ps
CPU time 1.62 seconds
Started Apr 30 03:04:52 PM PDT 24
Finished Apr 30 03:04:54 PM PDT 24
Peak memory 202020 kb
Host smart-8d5fb980-cb97-4831-b1da-054b8a080c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080681288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2080681288
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2977925641
Short name T290
Test name
Test status
Simulation time 166110447325 ps
CPU time 106.7 seconds
Started Apr 30 03:04:43 PM PDT 24
Finished Apr 30 03:06:30 PM PDT 24
Peak memory 202288 kb
Host smart-c4c4170f-7d5c-4e9d-899c-9f23e01b953c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977925641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2977925641
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4062483881
Short name T338
Test name
Test status
Simulation time 198564453366 ps
CPU time 125.88 seconds
Started Apr 30 03:04:49 PM PDT 24
Finished Apr 30 03:06:55 PM PDT 24
Peak memory 202328 kb
Host smart-7256d74b-dd8a-46f8-93be-6d0a2284dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062483881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4062483881
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.3381909931
Short name T159
Test name
Test status
Simulation time 328005617416 ps
CPU time 231.96 seconds
Started Apr 30 03:04:43 PM PDT 24
Finished Apr 30 03:08:35 PM PDT 24
Peak memory 202324 kb
Host smart-20b317fc-403f-4f96-a48b-5a8945ffdcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381909931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.3381909931
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.964814569
Short name T371
Test name
Test status
Simulation time 327436727906 ps
CPU time 719.27 seconds
Started Apr 30 03:04:42 PM PDT 24
Finished Apr 30 03:16:42 PM PDT 24
Peak memory 202296 kb
Host smart-eeaabc58-afe7-4b42-b5c6-7e7032507572
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=964814569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.964814569
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3994816323
Short name T470
Test name
Test status
Simulation time 329232223203 ps
CPU time 349.06 seconds
Started Apr 30 03:04:41 PM PDT 24
Finished Apr 30 03:10:30 PM PDT 24
Peak memory 202396 kb
Host smart-d21d8df7-365a-4088-b35b-e0d0213df595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994816323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3994816323
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3915870364
Short name T722
Test name
Test status
Simulation time 484482121845 ps
CPU time 1173.68 seconds
Started Apr 30 03:04:41 PM PDT 24
Finished Apr 30 03:24:16 PM PDT 24
Peak memory 202232 kb
Host smart-15762c40-44cb-4201-9a36-e0c189910ab0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915870364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3915870364
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3610011601
Short name T306
Test name
Test status
Simulation time 369081508891 ps
CPU time 798.25 seconds
Started Apr 30 03:04:42 PM PDT 24
Finished Apr 30 03:18:01 PM PDT 24
Peak memory 202304 kb
Host smart-34dc205c-7fa8-4594-9d02-b0fd17dc7c10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610011601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3610011601
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3860070963
Short name T393
Test name
Test status
Simulation time 408089374844 ps
CPU time 832.1 seconds
Started Apr 30 03:04:43 PM PDT 24
Finished Apr 30 03:18:36 PM PDT 24
Peak memory 202268 kb
Host smart-7592f425-f379-4eb8-aacc-f0f7e806ab08
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860070963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3860070963
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.2509574050
Short name T733
Test name
Test status
Simulation time 93702625547 ps
CPU time 538.35 seconds
Started Apr 30 03:04:51 PM PDT 24
Finished Apr 30 03:13:50 PM PDT 24
Peak memory 202652 kb
Host smart-ca78debb-e74d-44a7-aff2-9e8a4f13b4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509574050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.2509574050
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3732337701
Short name T93
Test name
Test status
Simulation time 31954473281 ps
CPU time 71.85 seconds
Started Apr 30 03:04:50 PM PDT 24
Finished Apr 30 03:06:02 PM PDT 24
Peak memory 202084 kb
Host smart-6f62d666-bad2-4f05-a0e0-b8c9f35a7bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732337701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3732337701
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3353387238
Short name T466
Test name
Test status
Simulation time 5236612279 ps
CPU time 11.7 seconds
Started Apr 30 03:04:50 PM PDT 24
Finished Apr 30 03:05:02 PM PDT 24
Peak memory 202040 kb
Host smart-9028be8f-5d8c-4ae9-ad85-7601f0e7396e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353387238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3353387238
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.3980551359
Short name T774
Test name
Test status
Simulation time 5662780712 ps
CPU time 9.92 seconds
Started Apr 30 03:04:42 PM PDT 24
Finished Apr 30 03:04:53 PM PDT 24
Peak memory 202080 kb
Host smart-c9ceaea2-8f28-4687-af2f-8463b34cc568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980551359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.3980551359
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4078944974
Short name T343
Test name
Test status
Simulation time 349820324958 ps
CPU time 665.86 seconds
Started Apr 30 03:04:52 PM PDT 24
Finished Apr 30 03:15:58 PM PDT 24
Peak memory 213184 kb
Host smart-ddd7662c-def6-4ba7-8ca9-0dbeda3d1c0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078944974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4078944974
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2916819664
Short name T16
Test name
Test status
Simulation time 33237181181 ps
CPU time 71.87 seconds
Started Apr 30 03:04:49 PM PDT 24
Finished Apr 30 03:06:02 PM PDT 24
Peak memory 211068 kb
Host smart-04492e0f-23a1-45d6-8f3c-4193a2b0e32a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916819664 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2916819664
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2445417887
Short name T489
Test name
Test status
Simulation time 437682660 ps
CPU time 0.84 seconds
Started Apr 30 03:04:57 PM PDT 24
Finished Apr 30 03:04:58 PM PDT 24
Peak memory 201952 kb
Host smart-12af1fb4-76ab-4c79-9897-e55aabf4d15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445417887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2445417887
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1705755108
Short name T798
Test name
Test status
Simulation time 324251220190 ps
CPU time 410.71 seconds
Started Apr 30 03:04:50 PM PDT 24
Finished Apr 30 03:11:41 PM PDT 24
Peak memory 202364 kb
Host smart-7e051a67-2888-4821-8769-c2cae8423f02
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705755108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1705755108
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3450321850
Short name T563
Test name
Test status
Simulation time 159102276195 ps
CPU time 88.74 seconds
Started Apr 30 03:04:49 PM PDT 24
Finished Apr 30 03:06:18 PM PDT 24
Peak memory 202340 kb
Host smart-e3f43fad-faed-4ed2-a729-3480cc3e519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450321850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3450321850
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.545590056
Short name T602
Test name
Test status
Simulation time 323055221881 ps
CPU time 784.68 seconds
Started Apr 30 03:04:49 PM PDT 24
Finished Apr 30 03:17:55 PM PDT 24
Peak memory 202320 kb
Host smart-9c542a8e-a421-46df-bb6b-b9b86d75fb8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=545590056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.545590056
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.929945543
Short name T693
Test name
Test status
Simulation time 337705961834 ps
CPU time 726.57 seconds
Started Apr 30 03:04:50 PM PDT 24
Finished Apr 30 03:16:57 PM PDT 24
Peak memory 202216 kb
Host smart-7a5058d4-419b-415c-9cdf-b008036b2968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929945543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.929945543
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1440405505
Short name T138
Test name
Test status
Simulation time 163972668875 ps
CPU time 35.4 seconds
Started Apr 30 03:04:51 PM PDT 24
Finished Apr 30 03:05:27 PM PDT 24
Peak memory 202348 kb
Host smart-6fa63cba-7214-4e3c-8558-06d0a713ab34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440405505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1440405505
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.951756157
Short name T281
Test name
Test status
Simulation time 359260119943 ps
CPU time 392.94 seconds
Started Apr 30 03:04:52 PM PDT 24
Finished Apr 30 03:11:25 PM PDT 24
Peak memory 202388 kb
Host smart-2bf8e90f-dfb4-4165-9367-652153c457e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951756157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_
wakeup.951756157
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.3950395851
Short name T475
Test name
Test status
Simulation time 422143624879 ps
CPU time 1029.96 seconds
Started Apr 30 03:04:50 PM PDT 24
Finished Apr 30 03:22:00 PM PDT 24
Peak memory 202276 kb
Host smart-491cd551-e8e2-4efa-84d3-c4f7c4e8e12e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950395851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.3950395851
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.4139085482
Short name T373
Test name
Test status
Simulation time 124021602206 ps
CPU time 420.13 seconds
Started Apr 30 03:04:56 PM PDT 24
Finished Apr 30 03:11:56 PM PDT 24
Peak memory 202624 kb
Host smart-e60348fe-d628-4c0c-98ca-d878d45e0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139085482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.4139085482
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.986327290
Short name T618
Test name
Test status
Simulation time 45619520302 ps
CPU time 18.44 seconds
Started Apr 30 03:04:55 PM PDT 24
Finished Apr 30 03:05:14 PM PDT 24
Peak memory 202152 kb
Host smart-ba94cab1-09fc-4a26-a734-148284ebd40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986327290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.986327290
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3468912817
Short name T367
Test name
Test status
Simulation time 3341559399 ps
CPU time 2.67 seconds
Started Apr 30 03:04:55 PM PDT 24
Finished Apr 30 03:04:59 PM PDT 24
Peak memory 202084 kb
Host smart-22a05ec0-4013-4a7b-9897-c1ac5896e2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468912817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3468912817
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1089703981
Short name T375
Test name
Test status
Simulation time 6169309726 ps
CPU time 15.26 seconds
Started Apr 30 03:04:51 PM PDT 24
Finished Apr 30 03:05:07 PM PDT 24
Peak memory 202124 kb
Host smart-3859e4ff-e9a1-4bd8-933a-5576570397d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089703981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1089703981
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2476699432
Short name T324
Test name
Test status
Simulation time 550404593456 ps
CPU time 351.46 seconds
Started Apr 30 03:04:58 PM PDT 24
Finished Apr 30 03:10:49 PM PDT 24
Peak memory 202368 kb
Host smart-164cf33b-e1ef-45e0-be41-9d4ef8b1ffd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476699432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2476699432
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1924065506
Short name T81
Test name
Test status
Simulation time 72729879602 ps
CPU time 40.94 seconds
Started Apr 30 03:04:56 PM PDT 24
Finished Apr 30 03:05:37 PM PDT 24
Peak memory 211968 kb
Host smart-bc357a09-d6b1-4d9a-af65-682db9590140
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924065506 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1924065506
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2316297913
Short name T686
Test name
Test status
Simulation time 313372667 ps
CPU time 0.8 seconds
Started Apr 30 03:05:07 PM PDT 24
Finished Apr 30 03:05:08 PM PDT 24
Peak memory 202020 kb
Host smart-4457dc75-8899-4d29-b60a-9d9c7e321dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316297913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2316297913
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3778559878
Short name T638
Test name
Test status
Simulation time 329618581519 ps
CPU time 545.99 seconds
Started Apr 30 03:05:07 PM PDT 24
Finished Apr 30 03:14:13 PM PDT 24
Peak memory 202364 kb
Host smart-974e43fc-c941-4cd1-a1bd-99589a886f73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778559878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3778559878
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2234367090
Short name T353
Test name
Test status
Simulation time 162788733046 ps
CPU time 393.27 seconds
Started Apr 30 03:05:08 PM PDT 24
Finished Apr 30 03:11:42 PM PDT 24
Peak memory 202500 kb
Host smart-a3d4e386-2742-4171-8f57-c8d36d757e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234367090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2234367090
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1311093318
Short name T268
Test name
Test status
Simulation time 162625896571 ps
CPU time 384.26 seconds
Started Apr 30 03:04:57 PM PDT 24
Finished Apr 30 03:11:21 PM PDT 24
Peak memory 202368 kb
Host smart-3f3c7c9b-55fb-406a-b389-237a103c142e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311093318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1311093318
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4018832590
Short name T415
Test name
Test status
Simulation time 165223923158 ps
CPU time 86.82 seconds
Started Apr 30 03:04:56 PM PDT 24
Finished Apr 30 03:06:23 PM PDT 24
Peak memory 202264 kb
Host smart-8f82552b-6701-4aaf-b363-392f0377ea1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018832590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4018832590
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2145332199
Short name T673
Test name
Test status
Simulation time 161855463556 ps
CPU time 364.47 seconds
Started Apr 30 03:04:56 PM PDT 24
Finished Apr 30 03:11:01 PM PDT 24
Peak memory 202292 kb
Host smart-889c2ac1-3658-4809-8902-bd641640636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145332199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2145332199
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.690656359
Short name T452
Test name
Test status
Simulation time 166449378962 ps
CPU time 98.82 seconds
Started Apr 30 03:04:57 PM PDT 24
Finished Apr 30 03:06:36 PM PDT 24
Peak memory 202236 kb
Host smart-41d49292-3f74-46b3-91a4-ba16fc431142
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=690656359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.690656359
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1403674897
Short name T681
Test name
Test status
Simulation time 464169285393 ps
CPU time 75.74 seconds
Started Apr 30 03:05:05 PM PDT 24
Finished Apr 30 03:06:22 PM PDT 24
Peak memory 202240 kb
Host smart-d1543a33-70b9-4924-99cd-36ff52d12019
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403674897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1403674897
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.2336282271
Short name T459
Test name
Test status
Simulation time 384467323598 ps
CPU time 66.8 seconds
Started Apr 30 03:05:04 PM PDT 24
Finished Apr 30 03:06:12 PM PDT 24
Peak memory 202224 kb
Host smart-a6aa103c-db9a-422d-98b1-395b4736600d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336282271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.2336282271
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.383810613
Short name T218
Test name
Test status
Simulation time 81219171967 ps
CPU time 422.07 seconds
Started Apr 30 03:05:06 PM PDT 24
Finished Apr 30 03:12:08 PM PDT 24
Peak memory 202628 kb
Host smart-ecdfde13-0a27-484f-a4ff-66b02f2b76cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383810613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.383810613
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3111136105
Short name T86
Test name
Test status
Simulation time 43671171163 ps
CPU time 24.68 seconds
Started Apr 30 03:05:05 PM PDT 24
Finished Apr 30 03:05:30 PM PDT 24
Peak memory 202108 kb
Host smart-12969f24-8920-4779-84b4-676ccb9b5732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111136105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3111136105
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2318404702
Short name T608
Test name
Test status
Simulation time 3590112298 ps
CPU time 2.82 seconds
Started Apr 30 03:05:06 PM PDT 24
Finished Apr 30 03:05:10 PM PDT 24
Peak memory 202096 kb
Host smart-378c2792-e092-478e-85ac-237905d28ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318404702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2318404702
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2144704552
Short name T587
Test name
Test status
Simulation time 5645188436 ps
CPU time 13.51 seconds
Started Apr 30 03:04:57 PM PDT 24
Finished Apr 30 03:05:10 PM PDT 24
Peak memory 202060 kb
Host smart-f306db12-6d52-48fa-8ed7-887483516f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144704552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2144704552
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1598233894
Short name T206
Test name
Test status
Simulation time 281241506317 ps
CPU time 389.31 seconds
Started Apr 30 03:05:10 PM PDT 24
Finished Apr 30 03:11:40 PM PDT 24
Peak memory 212540 kb
Host smart-008b1583-4d3f-43f4-a46c-2c6e3dffa82d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598233894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1598233894
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3689462953
Short name T270
Test name
Test status
Simulation time 36773062135 ps
CPU time 25.11 seconds
Started Apr 30 03:05:06 PM PDT 24
Finished Apr 30 03:05:32 PM PDT 24
Peak memory 202432 kb
Host smart-49024ec2-5887-4469-aaec-a90431a58f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689462953 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3689462953
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1020342022
Short name T574
Test name
Test status
Simulation time 317201409 ps
CPU time 0.99 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:05:16 PM PDT 24
Peak memory 201884 kb
Host smart-f1c828ee-5522-452e-8327-f9ce446f0da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020342022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1020342022
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.320914005
Short name T296
Test name
Test status
Simulation time 543987828542 ps
CPU time 783.68 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:18:20 PM PDT 24
Peak memory 202288 kb
Host smart-c73e9198-1817-413f-8a94-ae93893edafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320914005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.320914005
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3697192163
Short name T620
Test name
Test status
Simulation time 162617468929 ps
CPU time 405.62 seconds
Started Apr 30 03:05:10 PM PDT 24
Finished Apr 30 03:11:56 PM PDT 24
Peak memory 202324 kb
Host smart-d08935b4-efbb-40c3-9da6-647aa711f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697192163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3697192163
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3702728339
Short name T636
Test name
Test status
Simulation time 321630378187 ps
CPU time 716.48 seconds
Started Apr 30 03:05:06 PM PDT 24
Finished Apr 30 03:17:04 PM PDT 24
Peak memory 202236 kb
Host smart-f19e7567-437e-4911-9d99-72e5341fd89c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702728339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3702728339
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.2159673278
Short name T482
Test name
Test status
Simulation time 169602609735 ps
CPU time 376.34 seconds
Started Apr 30 03:05:08 PM PDT 24
Finished Apr 30 03:11:25 PM PDT 24
Peak memory 202588 kb
Host smart-1334189c-af83-4cca-a605-ea0f1028fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159673278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.2159673278
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3470056439
Short name T421
Test name
Test status
Simulation time 160454495781 ps
CPU time 187.68 seconds
Started Apr 30 03:05:05 PM PDT 24
Finished Apr 30 03:08:13 PM PDT 24
Peak memory 202244 kb
Host smart-6360526a-c69d-4f99-b25b-dad85694b21b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470056439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3470056439
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3656467115
Short name T767
Test name
Test status
Simulation time 364316210960 ps
CPU time 827.07 seconds
Started Apr 30 03:05:16 PM PDT 24
Finished Apr 30 03:19:04 PM PDT 24
Peak memory 202228 kb
Host smart-7e9a01b3-69b3-4dbf-a148-68bc394e5607
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656467115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3656467115
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1134683568
Short name T501
Test name
Test status
Simulation time 396790351804 ps
CPU time 496.18 seconds
Started Apr 30 03:05:16 PM PDT 24
Finished Apr 30 03:13:33 PM PDT 24
Peak memory 202384 kb
Host smart-7591beef-ec08-4136-87d3-ea43acdb7f42
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134683568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1134683568
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.284725101
Short name T360
Test name
Test status
Simulation time 115737253254 ps
CPU time 402.37 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:11:58 PM PDT 24
Peak memory 202604 kb
Host smart-50590b35-d59e-425b-9446-233a527117de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284725101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.284725101
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.1854084987
Short name T443
Test name
Test status
Simulation time 25918053490 ps
CPU time 59.99 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:06:15 PM PDT 24
Peak memory 202080 kb
Host smart-32a61410-71eb-47c9-b059-a7489380071c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854084987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.1854084987
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.1022753750
Short name T790
Test name
Test status
Simulation time 4960576381 ps
CPU time 11.05 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:05:28 PM PDT 24
Peak memory 202168 kb
Host smart-3e6a80e2-4a93-4387-8e40-afaa4c6496e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022753750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.1022753750
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1050597269
Short name T753
Test name
Test status
Simulation time 5740624980 ps
CPU time 11.72 seconds
Started Apr 30 03:05:00 PM PDT 24
Finished Apr 30 03:05:12 PM PDT 24
Peak memory 202148 kb
Host smart-d9c985f0-36fd-4672-a5e3-2edf565b0269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050597269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1050597269
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.852949503
Short name T162
Test name
Test status
Simulation time 494081112159 ps
CPU time 310.08 seconds
Started Apr 30 03:05:16 PM PDT 24
Finished Apr 30 03:10:27 PM PDT 24
Peak memory 202284 kb
Host smart-c1fd1836-ba34-486e-bba2-c6fa9f799a22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852949503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
852949503
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3136297638
Short name T87
Test name
Test status
Simulation time 161171065328 ps
CPU time 175.17 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:08:11 PM PDT 24
Peak memory 211044 kb
Host smart-9fdf91fc-f46c-45f5-bd8a-58ed565440c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136297638 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3136297638
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1734870751
Short name T582
Test name
Test status
Simulation time 331224988 ps
CPU time 1.21 seconds
Started Apr 30 03:05:21 PM PDT 24
Finished Apr 30 03:05:22 PM PDT 24
Peak memory 201972 kb
Host smart-85ffc229-1bc8-4f54-b1d7-1e2cd4bf130b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734870751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1734870751
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.682835764
Short name T351
Test name
Test status
Simulation time 341502732341 ps
CPU time 137.01 seconds
Started Apr 30 03:05:18 PM PDT 24
Finished Apr 30 03:07:35 PM PDT 24
Peak memory 202424 kb
Host smart-c14987de-9b06-412e-b535-d480c8b2735a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682835764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.682835764
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.741250659
Short name T229
Test name
Test status
Simulation time 234198617928 ps
CPU time 556.13 seconds
Started Apr 30 03:05:22 PM PDT 24
Finished Apr 30 03:14:39 PM PDT 24
Peak memory 202264 kb
Host smart-cf975a86-4148-4594-8b13-656f0c13d36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741250659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.741250659
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2626866319
Short name T267
Test name
Test status
Simulation time 500996744856 ps
CPU time 976.34 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:21:33 PM PDT 24
Peak memory 202256 kb
Host smart-97976de2-7b99-4c69-831b-14827dead0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626866319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2626866319
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.2940891049
Short name T621
Test name
Test status
Simulation time 169665572306 ps
CPU time 84.1 seconds
Started Apr 30 03:05:14 PM PDT 24
Finished Apr 30 03:06:39 PM PDT 24
Peak memory 202196 kb
Host smart-f6fdc0cb-78b1-4496-88b0-22c61aec2873
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940891049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.2940891049
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2008209139
Short name T755
Test name
Test status
Simulation time 325843260809 ps
CPU time 697.7 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:16:54 PM PDT 24
Peak memory 202376 kb
Host smart-3b8e96ce-7178-4125-ad1d-fbfee58ef0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008209139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2008209139
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1113160351
Short name T626
Test name
Test status
Simulation time 481611393480 ps
CPU time 568.23 seconds
Started Apr 30 03:05:14 PM PDT 24
Finished Apr 30 03:14:42 PM PDT 24
Peak memory 202296 kb
Host smart-c3e0feda-c57c-4f36-9775-1759884c091e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113160351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1113160351
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2601388493
Short name T320
Test name
Test status
Simulation time 522739419492 ps
CPU time 1157.6 seconds
Started Apr 30 03:05:18 PM PDT 24
Finished Apr 30 03:24:36 PM PDT 24
Peak memory 202500 kb
Host smart-914edc9c-9c84-4fbc-9297-1115ade56166
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601388493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2601388493
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.787262801
Short name T173
Test name
Test status
Simulation time 415342307581 ps
CPU time 467.16 seconds
Started Apr 30 03:05:14 PM PDT 24
Finished Apr 30 03:13:02 PM PDT 24
Peak memory 202344 kb
Host smart-af5c0207-ab84-452f-8ad2-c652eee95d55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787262801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.787262801
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4216532216
Short name T713
Test name
Test status
Simulation time 58600513303 ps
CPU time 209.77 seconds
Started Apr 30 03:05:24 PM PDT 24
Finished Apr 30 03:08:54 PM PDT 24
Peak memory 202604 kb
Host smart-66a57ab2-02fd-461d-9d5b-480370e8b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216532216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4216532216
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.634324740
Short name T172
Test name
Test status
Simulation time 34324348949 ps
CPU time 79.35 seconds
Started Apr 30 03:05:24 PM PDT 24
Finished Apr 30 03:06:44 PM PDT 24
Peak memory 202156 kb
Host smart-7f698e7a-a3e8-4f43-b3b0-6f8cb913e00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634324740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.634324740
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.4102331534
Short name T499
Test name
Test status
Simulation time 4727467303 ps
CPU time 3.78 seconds
Started Apr 30 03:05:23 PM PDT 24
Finished Apr 30 03:05:27 PM PDT 24
Peak memory 202056 kb
Host smart-de287f68-0aed-4290-86d2-4f8f4df5dcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102331534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.4102331534
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2104575980
Short name T718
Test name
Test status
Simulation time 5784111005 ps
CPU time 15.52 seconds
Started Apr 30 03:05:15 PM PDT 24
Finished Apr 30 03:05:31 PM PDT 24
Peak memory 202060 kb
Host smart-6a55c71e-fe16-470b-8b1e-0060ba28c363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104575980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2104575980
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3778104103
Short name T5
Test name
Test status
Simulation time 288154139359 ps
CPU time 540.59 seconds
Started Apr 30 03:05:22 PM PDT 24
Finished Apr 30 03:14:23 PM PDT 24
Peak memory 202756 kb
Host smart-758ae50e-748f-4ba7-b8e1-db1cf5b9e9b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778104103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3778104103
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.281456725
Short name T89
Test name
Test status
Simulation time 76979420257 ps
CPU time 295.92 seconds
Started Apr 30 03:05:21 PM PDT 24
Finished Apr 30 03:10:17 PM PDT 24
Peak memory 211028 kb
Host smart-1227391a-7606-4c7b-adfa-b8637fad8578
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281456725 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.281456725
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1961322985
Short name T394
Test name
Test status
Simulation time 306516981 ps
CPU time 1.38 seconds
Started Apr 30 03:05:29 PM PDT 24
Finished Apr 30 03:05:30 PM PDT 24
Peak memory 201996 kb
Host smart-96d85b49-9629-4fa5-b2d2-d8ae04d870f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961322985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1961322985
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.256478334
Short name T298
Test name
Test status
Simulation time 502290434614 ps
CPU time 213.21 seconds
Started Apr 30 03:05:25 PM PDT 24
Finished Apr 30 03:08:59 PM PDT 24
Peak memory 202300 kb
Host smart-ba0240a6-4bc5-45d9-83df-af2b1e5cac18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256478334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.256478334
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2226259430
Short name T309
Test name
Test status
Simulation time 163349513089 ps
CPU time 384.21 seconds
Started Apr 30 03:05:24 PM PDT 24
Finished Apr 30 03:11:49 PM PDT 24
Peak memory 202236 kb
Host smart-49ceeaea-a4ca-4e69-b684-b0b5f2ea081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226259430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2226259430
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3316010634
Short name T388
Test name
Test status
Simulation time 159721872078 ps
CPU time 186.66 seconds
Started Apr 30 03:05:23 PM PDT 24
Finished Apr 30 03:08:30 PM PDT 24
Peak memory 202320 kb
Host smart-7d779d92-1e22-4602-a9fc-188afe1108d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316010634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3316010634
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3599231
Short name T149
Test name
Test status
Simulation time 324495099077 ps
CPU time 174.12 seconds
Started Apr 30 03:05:23 PM PDT 24
Finished Apr 30 03:08:18 PM PDT 24
Peak memory 202264 kb
Host smart-92876d25-a4e5-4c46-9c1b-45358cb38be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3599231
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2369017055
Short name T455
Test name
Test status
Simulation time 483919219613 ps
CPU time 1224.02 seconds
Started Apr 30 03:05:23 PM PDT 24
Finished Apr 30 03:25:47 PM PDT 24
Peak memory 202328 kb
Host smart-a31d4ec2-b4a8-47f1-9fe1-4446da863aa2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369017055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2369017055
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.3358009078
Short name T339
Test name
Test status
Simulation time 174980013900 ps
CPU time 47.67 seconds
Started Apr 30 03:05:20 PM PDT 24
Finished Apr 30 03:06:09 PM PDT 24
Peak memory 202300 kb
Host smart-342de9e5-1a05-4cf1-b33d-bc6892984d85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358009078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.3358009078
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3894004159
Short name T746
Test name
Test status
Simulation time 189758431720 ps
CPU time 437.92 seconds
Started Apr 30 03:05:23 PM PDT 24
Finished Apr 30 03:12:42 PM PDT 24
Peak memory 202332 kb
Host smart-c57118e9-1965-45bb-a2ad-e141fb5dfb71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894004159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3894004159
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2141163361
Short name T553
Test name
Test status
Simulation time 129276640241 ps
CPU time 475.06 seconds
Started Apr 30 03:05:27 PM PDT 24
Finished Apr 30 03:13:22 PM PDT 24
Peak memory 201844 kb
Host smart-5d25b311-5c82-400d-8594-9ecc28ea452c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141163361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2141163361
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3075110754
Short name T26
Test name
Test status
Simulation time 45808239702 ps
CPU time 25.63 seconds
Started Apr 30 03:05:28 PM PDT 24
Finished Apr 30 03:05:54 PM PDT 24
Peak memory 202112 kb
Host smart-df7b26d6-4542-4f55-996a-973ba9e17f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075110754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3075110754
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.175047261
Short name T729
Test name
Test status
Simulation time 4996463709 ps
CPU time 3.74 seconds
Started Apr 30 03:05:26 PM PDT 24
Finished Apr 30 03:05:31 PM PDT 24
Peak memory 202128 kb
Host smart-63081fc2-89ca-413f-ae0a-b4e5ddfd7f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175047261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.175047261
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3272097126
Short name T758
Test name
Test status
Simulation time 6031626986 ps
CPU time 7.49 seconds
Started Apr 30 03:05:24 PM PDT 24
Finished Apr 30 03:05:32 PM PDT 24
Peak memory 202180 kb
Host smart-f9620cb5-b4c0-45ac-9a75-7156eb655ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272097126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3272097126
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.3122719966
Short name T683
Test name
Test status
Simulation time 37850968735 ps
CPU time 21.99 seconds
Started Apr 30 03:05:29 PM PDT 24
Finished Apr 30 03:05:51 PM PDT 24
Peak memory 202120 kb
Host smart-419c52e6-c027-4407-841e-32cc281629f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122719966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.3122719966
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1297426290
Short name T269
Test name
Test status
Simulation time 85826901493 ps
CPU time 187.17 seconds
Started Apr 30 03:05:28 PM PDT 24
Finished Apr 30 03:08:35 PM PDT 24
Peak memory 211072 kb
Host smart-fa4b68b8-82e2-4f1e-a5f1-4433dc8b1c5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297426290 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1297426290
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2965661629
Short name T766
Test name
Test status
Simulation time 467897831 ps
CPU time 0.84 seconds
Started Apr 30 03:05:41 PM PDT 24
Finished Apr 30 03:05:43 PM PDT 24
Peak memory 201920 kb
Host smart-4e6dde17-b664-4b75-8b08-6afd3162168f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965661629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2965661629
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1855574780
Short name T232
Test name
Test status
Simulation time 167176402293 ps
CPU time 94.89 seconds
Started Apr 30 03:05:35 PM PDT 24
Finished Apr 30 03:07:11 PM PDT 24
Peak memory 202344 kb
Host smart-5b870aed-90eb-43eb-806c-8c38e1f39e81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855574780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1855574780
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3423212942
Short name T137
Test name
Test status
Simulation time 162945967008 ps
CPU time 384.32 seconds
Started Apr 30 03:05:42 PM PDT 24
Finished Apr 30 03:12:07 PM PDT 24
Peak memory 202304 kb
Host smart-1a0c8e6e-df8d-4663-976e-9803bcb51f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423212942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3423212942
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.2390641362
Short name T462
Test name
Test status
Simulation time 162074320164 ps
CPU time 199.96 seconds
Started Apr 30 03:05:33 PM PDT 24
Finished Apr 30 03:08:54 PM PDT 24
Peak memory 202220 kb
Host smart-782b23d9-2a98-41d6-af75-6911598a2694
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390641362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.2390641362
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3466644728
Short name T300
Test name
Test status
Simulation time 316806456776 ps
CPU time 340.4 seconds
Started Apr 30 03:05:26 PM PDT 24
Finished Apr 30 03:11:07 PM PDT 24
Peak memory 202356 kb
Host smart-c9f9a84a-ec22-4c16-aed9-0abc3f00c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466644728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3466644728
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2848281686
Short name T436
Test name
Test status
Simulation time 160417176390 ps
CPU time 333.78 seconds
Started Apr 30 03:05:34 PM PDT 24
Finished Apr 30 03:11:09 PM PDT 24
Peak memory 202304 kb
Host smart-1ef27dbd-89e3-4918-9af2-0c4e2be859d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848281686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2848281686
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.307498436
Short name T156
Test name
Test status
Simulation time 174654375660 ps
CPU time 215.58 seconds
Started Apr 30 03:05:34 PM PDT 24
Finished Apr 30 03:09:10 PM PDT 24
Peak memory 202260 kb
Host smart-d15cabcc-ced5-4e70-8aa0-fbe2d601b2ac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307498436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_
wakeup.307498436
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3917443270
Short name T503
Test name
Test status
Simulation time 410225975249 ps
CPU time 220.27 seconds
Started Apr 30 03:05:35 PM PDT 24
Finished Apr 30 03:09:16 PM PDT 24
Peak memory 202232 kb
Host smart-817e6a44-6561-4c47-a500-dc3187811703
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917443270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3917443270
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.250749281
Short name T211
Test name
Test status
Simulation time 85128719542 ps
CPU time 286.55 seconds
Started Apr 30 03:05:41 PM PDT 24
Finished Apr 30 03:10:28 PM PDT 24
Peak memory 202676 kb
Host smart-a7d6cdb3-e5ba-4f71-ba35-0cc4d0acc526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250749281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.250749281
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3796052118
Short name T110
Test name
Test status
Simulation time 26879573280 ps
CPU time 33.23 seconds
Started Apr 30 03:05:43 PM PDT 24
Finished Apr 30 03:06:17 PM PDT 24
Peak memory 202080 kb
Host smart-9ae12187-5dee-41f0-8893-254f1ff9b48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796052118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3796052118
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3067221421
Short name T170
Test name
Test status
Simulation time 4378044433 ps
CPU time 2.64 seconds
Started Apr 30 03:05:39 PM PDT 24
Finished Apr 30 03:05:42 PM PDT 24
Peak memory 202040 kb
Host smart-f598a646-d0e9-4b02-aee9-df1644217041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067221421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3067221421
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2819135255
Short name T4
Test name
Test status
Simulation time 5875462732 ps
CPU time 15.06 seconds
Started Apr 30 03:05:29 PM PDT 24
Finished Apr 30 03:05:45 PM PDT 24
Peak memory 202180 kb
Host smart-3f9a70f4-e3da-4252-934e-4f042b805939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819135255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2819135255
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.4012161845
Short name T274
Test name
Test status
Simulation time 169823987385 ps
CPU time 374.86 seconds
Started Apr 30 03:05:41 PM PDT 24
Finished Apr 30 03:11:57 PM PDT 24
Peak memory 202240 kb
Host smart-48433860-a23e-4daf-be9c-e1e22507834c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012161845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.4012161845
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.4059473968
Short name T54
Test name
Test status
Simulation time 71987812395 ps
CPU time 177.82 seconds
Started Apr 30 03:05:42 PM PDT 24
Finished Apr 30 03:08:41 PM PDT 24
Peak memory 212028 kb
Host smart-78766abc-957e-422f-bab5-0ccccd2ff6d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059473968 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.4059473968
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3860796975
Short name T66
Test name
Test status
Simulation time 526425261 ps
CPU time 1.86 seconds
Started Apr 30 03:05:47 PM PDT 24
Finished Apr 30 03:05:49 PM PDT 24
Peak memory 201988 kb
Host smart-f47d3b43-6c63-4ee4-897c-2a47fe82f874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860796975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3860796975
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.4214914095
Short name T491
Test name
Test status
Simulation time 165759154381 ps
CPU time 103.74 seconds
Started Apr 30 03:05:48 PM PDT 24
Finished Apr 30 03:07:32 PM PDT 24
Peak memory 202324 kb
Host smart-85a5e19e-0391-4a6d-b131-768511873005
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214914095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.4214914095
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1900377502
Short name T310
Test name
Test status
Simulation time 354440195970 ps
CPU time 84.59 seconds
Started Apr 30 03:05:48 PM PDT 24
Finished Apr 30 03:07:13 PM PDT 24
Peak memory 202268 kb
Host smart-8368d9a5-c8d8-42fd-945e-bd018c2e188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900377502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1900377502
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1810134613
Short name T624
Test name
Test status
Simulation time 163823319519 ps
CPU time 215.38 seconds
Started Apr 30 03:05:43 PM PDT 24
Finished Apr 30 03:09:19 PM PDT 24
Peak memory 202248 kb
Host smart-ec017ab5-4d7a-44f5-879f-d4de7131adfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810134613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1810134613
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4265885140
Short name T385
Test name
Test status
Simulation time 330370878496 ps
CPU time 195.5 seconds
Started Apr 30 03:05:41 PM PDT 24
Finished Apr 30 03:08:57 PM PDT 24
Peak memory 202216 kb
Host smart-953ceee1-cc58-4e96-8211-8ea8df651157
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265885140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4265885140
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3695013713
Short name T715
Test name
Test status
Simulation time 495120204491 ps
CPU time 555.43 seconds
Started Apr 30 03:05:43 PM PDT 24
Finished Apr 30 03:14:59 PM PDT 24
Peak memory 202388 kb
Host smart-436ebc04-d53c-4585-9bb9-ea39598500f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695013713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3695013713
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1186083869
Short name T723
Test name
Test status
Simulation time 332083179299 ps
CPU time 375.47 seconds
Started Apr 30 03:05:43 PM PDT 24
Finished Apr 30 03:11:59 PM PDT 24
Peak memory 202348 kb
Host smart-abf7c32b-d7c9-443b-83fc-ef5dec12195b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186083869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1186083869
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.101813453
Short name T711
Test name
Test status
Simulation time 423235293328 ps
CPU time 868.06 seconds
Started Apr 30 03:05:41 PM PDT 24
Finished Apr 30 03:20:10 PM PDT 24
Peak memory 202324 kb
Host smart-89725f55-4045-4856-97fb-5830bbdee674
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101813453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.101813453
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2220641712
Short name T748
Test name
Test status
Simulation time 210869511983 ps
CPU time 505.94 seconds
Started Apr 30 03:05:47 PM PDT 24
Finished Apr 30 03:14:13 PM PDT 24
Peak memory 202316 kb
Host smart-7a320099-99f9-4f9b-98cb-23f6cf6154d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220641712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2220641712
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4064716702
Short name T431
Test name
Test status
Simulation time 95304962114 ps
CPU time 509.59 seconds
Started Apr 30 03:05:49 PM PDT 24
Finished Apr 30 03:14:19 PM PDT 24
Peak memory 202644 kb
Host smart-58f14d55-e1ca-488e-a6ae-5e46b9e38256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064716702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4064716702
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2387003094
Short name T593
Test name
Test status
Simulation time 21893444236 ps
CPU time 47.01 seconds
Started Apr 30 03:05:48 PM PDT 24
Finished Apr 30 03:06:35 PM PDT 24
Peak memory 202180 kb
Host smart-a20124bc-621f-4156-8840-0f533898c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387003094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2387003094
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2943602660
Short name T103
Test name
Test status
Simulation time 4245096199 ps
CPU time 10.01 seconds
Started Apr 30 03:05:50 PM PDT 24
Finished Apr 30 03:06:01 PM PDT 24
Peak memory 202136 kb
Host smart-b45b3911-559f-49ce-8daa-3ebee1d70010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943602660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2943602660
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4009683965
Short name T744
Test name
Test status
Simulation time 5756504017 ps
CPU time 4.03 seconds
Started Apr 30 03:05:40 PM PDT 24
Finished Apr 30 03:05:45 PM PDT 24
Peak memory 202080 kb
Host smart-2cc9993f-06bd-4527-8155-43a7c352d60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009683965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4009683965
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.3048806133
Short name T261
Test name
Test status
Simulation time 169802912925 ps
CPU time 92.35 seconds
Started Apr 30 03:05:47 PM PDT 24
Finished Apr 30 03:07:20 PM PDT 24
Peak memory 202332 kb
Host smart-7a475ed1-8b4e-4673-8a00-bf6a1f242c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048806133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.3048806133
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2056813406
Short name T552
Test name
Test status
Simulation time 352408585 ps
CPU time 1.42 seconds
Started Apr 30 03:05:54 PM PDT 24
Finished Apr 30 03:05:56 PM PDT 24
Peak memory 201964 kb
Host smart-0d1500b9-a1f0-4f87-b000-5cc7e16eee3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056813406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2056813406
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.293177045
Short name T164
Test name
Test status
Simulation time 403504642517 ps
CPU time 115.88 seconds
Started Apr 30 03:05:54 PM PDT 24
Finished Apr 30 03:07:51 PM PDT 24
Peak memory 202252 kb
Host smart-340ccba3-e8fa-45cf-80ab-ab2e6c8ac9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293177045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.293177045
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.4278349318
Short name T184
Test name
Test status
Simulation time 169120201375 ps
CPU time 25.87 seconds
Started Apr 30 03:05:46 PM PDT 24
Finished Apr 30 03:06:13 PM PDT 24
Peak memory 202332 kb
Host smart-c85f3201-6d50-4e84-92f8-1a4d2986a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278349318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.4278349318
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1934212192
Short name T532
Test name
Test status
Simulation time 323556781260 ps
CPU time 178.57 seconds
Started Apr 30 03:05:47 PM PDT 24
Finished Apr 30 03:08:46 PM PDT 24
Peak memory 202296 kb
Host smart-de3b5bfa-005c-44df-b59b-fbe2deddb79e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934212192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1934212192
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.2632155951
Short name T613
Test name
Test status
Simulation time 335064488965 ps
CPU time 184.83 seconds
Started Apr 30 03:05:50 PM PDT 24
Finished Apr 30 03:08:55 PM PDT 24
Peak memory 202312 kb
Host smart-0cad784d-c7ea-4c9f-9506-397257ccaaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632155951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.2632155951
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3572496821
Short name T199
Test name
Test status
Simulation time 330705154450 ps
CPU time 200.4 seconds
Started Apr 30 03:05:47 PM PDT 24
Finished Apr 30 03:09:08 PM PDT 24
Peak memory 202172 kb
Host smart-571b3adb-e4fb-4631-904e-5a782993559f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572496821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3572496821
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1713327552
Short name T148
Test name
Test status
Simulation time 562452559313 ps
CPU time 312.05 seconds
Started Apr 30 03:05:50 PM PDT 24
Finished Apr 30 03:11:02 PM PDT 24
Peak memory 202372 kb
Host smart-d919658b-0f2f-4bef-ac24-209d76a652b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713327552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1713327552
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3383003743
Short name T411
Test name
Test status
Simulation time 209507116956 ps
CPU time 257.85 seconds
Started Apr 30 03:05:55 PM PDT 24
Finished Apr 30 03:10:13 PM PDT 24
Peak memory 202344 kb
Host smart-db6220d7-2597-49f5-ae9e-af150ccc7e3d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383003743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3383003743
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1868784436
Short name T94
Test name
Test status
Simulation time 85436918196 ps
CPU time 465.91 seconds
Started Apr 30 03:05:53 PM PDT 24
Finished Apr 30 03:13:39 PM PDT 24
Peak memory 202680 kb
Host smart-f4ab1b7a-38f1-458b-b2de-b3166ee45200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868784436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1868784436
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3816108392
Short name T730
Test name
Test status
Simulation time 32976609357 ps
CPU time 38.57 seconds
Started Apr 30 03:05:55 PM PDT 24
Finished Apr 30 03:06:34 PM PDT 24
Peak memory 202144 kb
Host smart-1296cfe2-c501-4326-9d85-69ab0d20cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816108392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3816108392
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1659892077
Short name T386
Test name
Test status
Simulation time 4954678555 ps
CPU time 7.95 seconds
Started Apr 30 03:05:55 PM PDT 24
Finished Apr 30 03:06:04 PM PDT 24
Peak memory 202108 kb
Host smart-06b6ba90-195a-49f4-ae2a-426191a3b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659892077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1659892077
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.2568811930
Short name T181
Test name
Test status
Simulation time 5753076016 ps
CPU time 3.05 seconds
Started Apr 30 03:05:47 PM PDT 24
Finished Apr 30 03:05:50 PM PDT 24
Peak memory 202064 kb
Host smart-9e7818d3-23d0-498f-8272-430d1f8dd3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568811930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.2568811930
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3583539103
Short name T647
Test name
Test status
Simulation time 492176750857 ps
CPU time 182.68 seconds
Started Apr 30 03:05:54 PM PDT 24
Finished Apr 30 03:08:58 PM PDT 24
Peak memory 202344 kb
Host smart-0badfb52-bdd1-4117-be67-75d2699c18c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583539103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3583539103
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3126166118
Short name T85
Test name
Test status
Simulation time 517800508 ps
CPU time 0.77 seconds
Started Apr 30 03:06:08 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 201964 kb
Host smart-f4f6ac89-4703-469a-9d26-225343101b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126166118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3126166118
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1469248539
Short name T258
Test name
Test status
Simulation time 204793111447 ps
CPU time 460.27 seconds
Started Apr 30 03:05:59 PM PDT 24
Finished Apr 30 03:13:40 PM PDT 24
Peak memory 202328 kb
Host smart-b53b4854-5a8e-4f8c-9fc4-29f5cac5dc6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469248539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1469248539
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3894027578
Short name T236
Test name
Test status
Simulation time 492928381593 ps
CPU time 299.16 seconds
Started Apr 30 03:06:01 PM PDT 24
Finished Apr 30 03:11:01 PM PDT 24
Peak memory 202352 kb
Host smart-63752564-8461-411f-bfeb-9b94978b0cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894027578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3894027578
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3723977324
Short name T235
Test name
Test status
Simulation time 492840079943 ps
CPU time 325.8 seconds
Started Apr 30 03:05:59 PM PDT 24
Finished Apr 30 03:11:25 PM PDT 24
Peak memory 202324 kb
Host smart-90d5daf6-0211-4fb6-a15e-7aadb73d4a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723977324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3723977324
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.457154628
Short name T463
Test name
Test status
Simulation time 490492781453 ps
CPU time 275.56 seconds
Started Apr 30 03:05:59 PM PDT 24
Finished Apr 30 03:10:35 PM PDT 24
Peak memory 202212 kb
Host smart-36bbec4f-7561-461f-9bd2-29ec80ac8d6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=457154628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.457154628
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3662092518
Short name T698
Test name
Test status
Simulation time 163873289061 ps
CPU time 207.47 seconds
Started Apr 30 03:05:53 PM PDT 24
Finished Apr 30 03:09:22 PM PDT 24
Peak memory 202416 kb
Host smart-8b5ac813-bc3e-4e6c-acfb-3f32da59c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662092518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3662092518
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.724321430
Short name T793
Test name
Test status
Simulation time 489296245434 ps
CPU time 609.84 seconds
Started Apr 30 03:05:54 PM PDT 24
Finished Apr 30 03:16:04 PM PDT 24
Peak memory 202160 kb
Host smart-47edc197-0ad6-4b1d-92d9-99d5e54601a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=724321430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixe
d.724321430
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.672808634
Short name T737
Test name
Test status
Simulation time 201947580435 ps
CPU time 115.28 seconds
Started Apr 30 03:06:00 PM PDT 24
Finished Apr 30 03:07:55 PM PDT 24
Peak memory 202428 kb
Host smart-dd0660b6-f693-493d-a9d9-ba260aa9bab9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672808634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.672808634
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1683841233
Short name T203
Test name
Test status
Simulation time 202178306505 ps
CPU time 447.7 seconds
Started Apr 30 03:06:01 PM PDT 24
Finished Apr 30 03:13:29 PM PDT 24
Peak memory 202296 kb
Host smart-b160b04e-dd53-4e08-8629-d3b73f29ca0e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683841233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1683841233
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1295768826
Short name T739
Test name
Test status
Simulation time 108163810889 ps
CPU time 562.51 seconds
Started Apr 30 03:06:00 PM PDT 24
Finished Apr 30 03:15:23 PM PDT 24
Peak memory 202636 kb
Host smart-690e8c22-cd5e-4068-9fcd-67102de94369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295768826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1295768826
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1130374208
Short name T500
Test name
Test status
Simulation time 31763659536 ps
CPU time 42.01 seconds
Started Apr 30 03:06:01 PM PDT 24
Finished Apr 30 03:06:43 PM PDT 24
Peak memory 202128 kb
Host smart-0ed7f8cc-cb7e-43bc-9365-c98540f88284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130374208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1130374208
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1914390222
Short name T768
Test name
Test status
Simulation time 2841064961 ps
CPU time 2.14 seconds
Started Apr 30 03:05:58 PM PDT 24
Finished Apr 30 03:06:01 PM PDT 24
Peak memory 202104 kb
Host smart-fd0171dc-f018-44e1-bc62-d9a404845612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914390222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1914390222
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3279764056
Short name T487
Test name
Test status
Simulation time 5963335171 ps
CPU time 4.59 seconds
Started Apr 30 03:05:54 PM PDT 24
Finished Apr 30 03:05:59 PM PDT 24
Peak memory 202112 kb
Host smart-b858a80f-70ab-4739-90e1-814a9986bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279764056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3279764056
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.653886779
Short name T648
Test name
Test status
Simulation time 552669947690 ps
CPU time 422.69 seconds
Started Apr 30 03:06:00 PM PDT 24
Finished Apr 30 03:13:03 PM PDT 24
Peak memory 211008 kb
Host smart-b267289b-9dfb-48a1-a8bc-f9a555b2312b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653886779 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.653886779
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1756334582
Short name T589
Test name
Test status
Simulation time 573756951 ps
CPU time 0.74 seconds
Started Apr 30 03:02:56 PM PDT 24
Finished Apr 30 03:02:57 PM PDT 24
Peak memory 201948 kb
Host smart-19e4094d-dabd-45da-8b4e-f0474d5139aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756334582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1756334582
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3415099291
Short name T597
Test name
Test status
Simulation time 323281812623 ps
CPU time 296.91 seconds
Started Apr 30 03:02:45 PM PDT 24
Finished Apr 30 03:07:42 PM PDT 24
Peak memory 202284 kb
Host smart-2984a094-6ac2-43bb-8c65-6040d8eb09ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415099291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3415099291
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2999118790
Short name T530
Test name
Test status
Simulation time 174833734807 ps
CPU time 135.72 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:05:12 PM PDT 24
Peak memory 202328 kb
Host smart-fa61b970-9761-46a2-ac0e-a2bcc848d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999118790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2999118790
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1054466497
Short name T259
Test name
Test status
Simulation time 493310716907 ps
CPU time 1178.73 seconds
Started Apr 30 03:02:48 PM PDT 24
Finished Apr 30 03:22:27 PM PDT 24
Peak memory 202332 kb
Host smart-2791c85c-2efa-422f-84f5-203279aedc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054466497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1054466497
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2960783118
Short name T476
Test name
Test status
Simulation time 160645835302 ps
CPU time 199.8 seconds
Started Apr 30 03:02:48 PM PDT 24
Finished Apr 30 03:06:08 PM PDT 24
Peak memory 202184 kb
Host smart-1f969bed-2768-4012-b75e-643a724276b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960783118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2960783118
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3992180236
Short name T662
Test name
Test status
Simulation time 163627343933 ps
CPU time 95.84 seconds
Started Apr 30 03:02:46 PM PDT 24
Finished Apr 30 03:04:23 PM PDT 24
Peak memory 202244 kb
Host smart-1e493199-0143-4bdd-bf20-6f2f05c86365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992180236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3992180236
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3907145492
Short name T548
Test name
Test status
Simulation time 166519535983 ps
CPU time 36.05 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:03:28 PM PDT 24
Peak memory 202268 kb
Host smart-8c5c7110-785d-4bdf-8be8-4073421a9b12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907145492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3907145492
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1132927850
Short name T249
Test name
Test status
Simulation time 402335784237 ps
CPU time 783.49 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:16:02 PM PDT 24
Peak memory 202320 kb
Host smart-ba87429b-a1b8-481a-beac-14028cc599c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132927850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1132927850
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.3894837128
Short name T416
Test name
Test status
Simulation time 206524537142 ps
CPU time 257.04 seconds
Started Apr 30 03:02:52 PM PDT 24
Finished Apr 30 03:07:09 PM PDT 24
Peak memory 202308 kb
Host smart-ca43803c-e9b0-4ce0-843c-59669288a318
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894837128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.3894837128
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.323784589
Short name T417
Test name
Test status
Simulation time 126776453390 ps
CPU time 481.68 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:10:53 PM PDT 24
Peak memory 202700 kb
Host smart-eadc2b73-c131-40f9-9bfb-9a9c6c537dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323784589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.323784589
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.4212996163
Short name T453
Test name
Test status
Simulation time 36497030986 ps
CPU time 43.55 seconds
Started Apr 30 03:02:56 PM PDT 24
Finished Apr 30 03:03:40 PM PDT 24
Peak memory 202136 kb
Host smart-75e2454b-8df0-4637-aa07-2a87dbdf0bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212996163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.4212996163
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.952615448
Short name T155
Test name
Test status
Simulation time 3087711752 ps
CPU time 8.29 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:03:04 PM PDT 24
Peak memory 202008 kb
Host smart-1619c954-d2c2-4d8e-8cc7-1d93f73c687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952615448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.952615448
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1953564083
Short name T652
Test name
Test status
Simulation time 6034366289 ps
CPU time 7.75 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 202112 kb
Host smart-663b20d4-88e8-42da-aa78-97c9e8fcb5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953564083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1953564083
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1684759523
Short name T35
Test name
Test status
Simulation time 176043500376 ps
CPU time 192.3 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:06:10 PM PDT 24
Peak memory 202232 kb
Host smart-1087b74b-2124-4982-97dd-fb7317e9535b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684759523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1684759523
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3436688342
Short name T19
Test name
Test status
Simulation time 40506246489 ps
CPU time 22.3 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:03:16 PM PDT 24
Peak memory 210720 kb
Host smart-b41581eb-105f-4813-b344-63424b2a8fbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436688342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3436688342
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3238024907
Short name T716
Test name
Test status
Simulation time 291042971 ps
CPU time 1.26 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:03:04 PM PDT 24
Peak memory 201856 kb
Host smart-9c041c47-6128-4dc2-a2d1-35d28c21c50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238024907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3238024907
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.4028666744
Short name T554
Test name
Test status
Simulation time 158909002393 ps
CPU time 194.69 seconds
Started Apr 30 03:03:03 PM PDT 24
Finished Apr 30 03:06:19 PM PDT 24
Peak memory 202292 kb
Host smart-63208b26-e39b-4d6b-a765-624b41894a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028666744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.4028666744
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.473304925
Short name T179
Test name
Test status
Simulation time 164234316898 ps
CPU time 363.6 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:08:59 PM PDT 24
Peak memory 202240 kb
Host smart-900111c3-2e72-4253-bac4-a968b9266b83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=473304925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.473304925
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1291016861
Short name T614
Test name
Test status
Simulation time 162445983250 ps
CPU time 46.48 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:03:41 PM PDT 24
Peak memory 202268 kb
Host smart-110dc320-2bc0-4716-b715-366e042f1510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291016861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1291016861
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1866350346
Short name T485
Test name
Test status
Simulation time 486141261418 ps
CPU time 1082.89 seconds
Started Apr 30 03:02:49 PM PDT 24
Finished Apr 30 03:20:52 PM PDT 24
Peak memory 202368 kb
Host smart-ca6b18fe-8de8-4da6-8d09-bbbc77722e21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866350346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1866350346
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2460487894
Short name T246
Test name
Test status
Simulation time 176964890943 ps
CPU time 48.6 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:03:50 PM PDT 24
Peak memory 202396 kb
Host smart-4b8b9d0c-fae6-49b6-8d15-08d3422dd034
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460487894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2460487894
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2622426081
Short name T534
Test name
Test status
Simulation time 396017574617 ps
CPU time 492.12 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:11:08 PM PDT 24
Peak memory 202272 kb
Host smart-934372c3-fbb7-4d70-a942-566010d1eaa0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622426081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2622426081
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.744402188
Short name T217
Test name
Test status
Simulation time 79326094203 ps
CPU time 277.72 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:07:36 PM PDT 24
Peak memory 202648 kb
Host smart-74c26a3f-88f4-4958-b5cf-347135817e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744402188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.744402188
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3730627854
Short name T546
Test name
Test status
Simulation time 25182238027 ps
CPU time 59.31 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:04:03 PM PDT 24
Peak memory 202144 kb
Host smart-33402bbd-9588-4f2a-aa2d-e2acf5f20fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730627854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3730627854
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.2999160285
Short name T376
Test name
Test status
Simulation time 4287205248 ps
CPU time 10.84 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:03:07 PM PDT 24
Peak memory 202072 kb
Host smart-4763d036-b496-405f-ae15-7af3d945c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999160285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.2999160285
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2479262339
Short name T478
Test name
Test status
Simulation time 6059426192 ps
CPU time 15.42 seconds
Started Apr 30 03:02:47 PM PDT 24
Finished Apr 30 03:03:02 PM PDT 24
Peak memory 202144 kb
Host smart-9cac2b2d-b1bd-4d27-bf23-615526c81862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479262339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2479262339
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3680663102
Short name T44
Test name
Test status
Simulation time 142950060879 ps
CPU time 370.52 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:09:02 PM PDT 24
Peak memory 210768 kb
Host smart-4f1c7112-abb2-48c7-9a25-2c9a393e8e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680663102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3680663102
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2748609372
Short name T709
Test name
Test status
Simulation time 113519307598 ps
CPU time 65.31 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:04:04 PM PDT 24
Peak memory 211004 kb
Host smart-30386536-72b8-4c19-a60e-4c1ddae59016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748609372 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2748609372
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4013701969
Short name T719
Test name
Test status
Simulation time 419448188 ps
CPU time 1.58 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:02:55 PM PDT 24
Peak memory 202000 kb
Host smart-0b0c2dee-1aa9-4620-ab31-2e5c895096e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013701969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4013701969
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.480481183
Short name T182
Test name
Test status
Simulation time 344943370634 ps
CPU time 379.29 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:09:23 PM PDT 24
Peak memory 202292 kb
Host smart-427ebc29-3e12-4089-a648-56d73b1cdaaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480481183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.480481183
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3554080699
Short name T240
Test name
Test status
Simulation time 162582630387 ps
CPU time 29.84 seconds
Started Apr 30 03:02:56 PM PDT 24
Finished Apr 30 03:03:27 PM PDT 24
Peak memory 202288 kb
Host smart-265f6cba-eca5-47a7-b0c1-e77298ec7054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554080699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3554080699
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3450330437
Short name T526
Test name
Test status
Simulation time 491258319468 ps
CPU time 282.86 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:07:39 PM PDT 24
Peak memory 202296 kb
Host smart-1e48b51e-baa2-4b58-8b84-cb96e86428bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450330437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3450330437
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3282616265
Short name T559
Test name
Test status
Simulation time 160848532295 ps
CPU time 186.14 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:06:06 PM PDT 24
Peak memory 202380 kb
Host smart-4795e6b3-05f9-4d1a-9273-4e42fcd86406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282616265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3282616265
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1228726797
Short name T409
Test name
Test status
Simulation time 487674718080 ps
CPU time 558.51 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:12:20 PM PDT 24
Peak memory 202248 kb
Host smart-65ec23cd-fc47-4984-b014-dba74ce5c10e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228726797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1228726797
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.4239658867
Short name T630
Test name
Test status
Simulation time 175531273306 ps
CPU time 100.69 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:04:39 PM PDT 24
Peak memory 202344 kb
Host smart-d8f8d1dc-4780-4c8c-b220-107e30d832e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239658867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.4239658867
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.2217584751
Short name T151
Test name
Test status
Simulation time 205748460402 ps
CPU time 485.45 seconds
Started Apr 30 03:02:56 PM PDT 24
Finished Apr 30 03:11:02 PM PDT 24
Peak memory 202304 kb
Host smart-9b162d1c-4c83-4187-b441-3b0c9d65176c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217584751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.2217584751
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3681302126
Short name T528
Test name
Test status
Simulation time 114687218136 ps
CPU time 364.65 seconds
Started Apr 30 03:02:49 PM PDT 24
Finished Apr 30 03:08:54 PM PDT 24
Peak memory 202648 kb
Host smart-20b5dc47-68d1-47a5-8d49-1a4b0e108e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681302126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3681302126
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3019747637
Short name T441
Test name
Test status
Simulation time 30820506333 ps
CPU time 75.77 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:04:14 PM PDT 24
Peak memory 202140 kb
Host smart-e6278b67-e465-4477-b281-ccd0b9361774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019747637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3019747637
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3199637867
Short name T426
Test name
Test status
Simulation time 3207987396 ps
CPU time 2.45 seconds
Started Apr 30 03:02:54 PM PDT 24
Finished Apr 30 03:02:57 PM PDT 24
Peak memory 202088 kb
Host smart-2084c3f2-c6ab-4e8f-8cdf-d43558aac371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199637867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3199637867
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1716793125
Short name T418
Test name
Test status
Simulation time 6078303623 ps
CPU time 4.2 seconds
Started Apr 30 03:03:00 PM PDT 24
Finished Apr 30 03:03:05 PM PDT 24
Peak memory 202132 kb
Host smart-14d32d82-e6ac-49d9-8339-8b1233e446a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716793125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1716793125
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2425910378
Short name T27
Test name
Test status
Simulation time 363062686563 ps
CPU time 229.29 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:06:48 PM PDT 24
Peak memory 202336 kb
Host smart-c78519e1-41aa-4358-b5da-f2796a8db377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425910378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2425910378
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2103345026
Short name T22
Test name
Test status
Simulation time 363261252907 ps
CPU time 223.36 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:06:35 PM PDT 24
Peak memory 210976 kb
Host smart-99c37d03-ed3b-49a5-be0d-8bb125b90ff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103345026 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2103345026
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4033073979
Short name T437
Test name
Test status
Simulation time 439289196 ps
CPU time 1.12 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:03:00 PM PDT 24
Peak memory 201936 kb
Host smart-a7309b27-56fa-446b-9923-730482aaf2c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033073979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4033073979
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.2159287918
Short name T303
Test name
Test status
Simulation time 167433056190 ps
CPU time 24.93 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:03:22 PM PDT 24
Peak memory 202228 kb
Host smart-e6fcf570-7a3c-4bb6-9f28-bca457b57faa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159287918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.2159287918
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.176121514
Short name T291
Test name
Test status
Simulation time 191104971515 ps
CPU time 462.14 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:10:36 PM PDT 24
Peak memory 202356 kb
Host smart-4467502d-6348-4695-85ae-7d69d4d6f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176121514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.176121514
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3059923449
Short name T331
Test name
Test status
Simulation time 170493169011 ps
CPU time 213.34 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:06:35 PM PDT 24
Peak memory 202300 kb
Host smart-b474a7da-507e-4ce4-8df9-132b2d3a0fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059923449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3059923449
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1388410216
Short name T457
Test name
Test status
Simulation time 487286488006 ps
CPU time 1166.78 seconds
Started Apr 30 03:02:50 PM PDT 24
Finished Apr 30 03:22:18 PM PDT 24
Peak memory 202232 kb
Host smart-a42115e2-5522-423b-a59e-0f83781fcb1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388410216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1388410216
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1070612525
Short name T222
Test name
Test status
Simulation time 328594944705 ps
CPU time 205.45 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:06:17 PM PDT 24
Peak memory 202388 kb
Host smart-bc726d57-2397-4b2d-a5c4-8b5a74ff4741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070612525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1070612525
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2055150564
Short name T377
Test name
Test status
Simulation time 164115084140 ps
CPU time 181.9 seconds
Started Apr 30 03:03:04 PM PDT 24
Finished Apr 30 03:06:07 PM PDT 24
Peak memory 202280 kb
Host smart-3765a155-6c6a-4d9a-8143-3b2e4beac189
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055150564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2055150564
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.379039668
Short name T564
Test name
Test status
Simulation time 635159282421 ps
CPU time 386.16 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:09:26 PM PDT 24
Peak memory 202372 kb
Host smart-84119ff6-7cc6-4d57-a6c1-8870da9d7852
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379039668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.379039668
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3798981464
Short name T480
Test name
Test status
Simulation time 596301431134 ps
CPU time 1395.46 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:26:09 PM PDT 24
Peak memory 202340 kb
Host smart-fd6aebb3-6918-402b-b71e-1dccaf91dbe5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798981464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3798981464
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.884198415
Short name T198
Test name
Test status
Simulation time 134494590765 ps
CPU time 594.05 seconds
Started Apr 30 03:02:57 PM PDT 24
Finished Apr 30 03:12:52 PM PDT 24
Peak memory 202636 kb
Host smart-111a169c-ed96-4ea7-bd0b-25cf454c0956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884198415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.884198415
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3457669349
Short name T606
Test name
Test status
Simulation time 30824013716 ps
CPU time 66.94 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:04:06 PM PDT 24
Peak memory 202120 kb
Host smart-1e63a087-0eb6-4b52-bbab-cdb490cafdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457669349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3457669349
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.719553934
Short name T508
Test name
Test status
Simulation time 3993515061 ps
CPU time 3.41 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:03:03 PM PDT 24
Peak memory 202148 kb
Host smart-874cf7cd-9d73-4176-9c66-7577e99d3348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719553934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.719553934
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3470348514
Short name T444
Test name
Test status
Simulation time 5999242809 ps
CPU time 4.03 seconds
Started Apr 30 03:03:16 PM PDT 24
Finished Apr 30 03:03:21 PM PDT 24
Peak memory 202080 kb
Host smart-ea11d268-1694-453e-9366-33766b88da0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470348514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3470348514
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1448255532
Short name T197
Test name
Test status
Simulation time 4778305363 ps
CPU time 2.55 seconds
Started Apr 30 03:02:51 PM PDT 24
Finished Apr 30 03:02:54 PM PDT 24
Peak memory 202152 kb
Host smart-384faad8-941d-45be-b3d8-d387af9493ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448255532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1448255532
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2116443255
Short name T387
Test name
Test status
Simulation time 471394491 ps
CPU time 0.93 seconds
Started Apr 30 03:02:58 PM PDT 24
Finished Apr 30 03:03:00 PM PDT 24
Peak memory 201936 kb
Host smart-13beaba5-9caf-45b0-b78f-9d5006610701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116443255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2116443255
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2062375715
Short name T251
Test name
Test status
Simulation time 171812192172 ps
CPU time 285.33 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:07:47 PM PDT 24
Peak memory 202300 kb
Host smart-197325de-22d1-45eb-956d-f1f59438c654
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062375715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2062375715
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.1134805992
Short name T640
Test name
Test status
Simulation time 166398295205 ps
CPU time 362.89 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:08:57 PM PDT 24
Peak memory 202272 kb
Host smart-1d8e2c21-4bd5-4a85-a8f2-88f4586eb462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134805992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.1134805992
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1879111062
Short name T158
Test name
Test status
Simulation time 332712853317 ps
CPU time 785.91 seconds
Started Apr 30 03:03:01 PM PDT 24
Finished Apr 30 03:16:09 PM PDT 24
Peak memory 202116 kb
Host smart-37be945a-f9e0-4a49-a10e-049e2ba6b3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879111062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1879111062
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2286844876
Short name T519
Test name
Test status
Simulation time 327387080771 ps
CPU time 179.86 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:05:59 PM PDT 24
Peak memory 202284 kb
Host smart-12f353aa-333f-4da5-a421-aba257a308c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286844876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2286844876
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.4081172838
Short name T202
Test name
Test status
Simulation time 329303981028 ps
CPU time 738.65 seconds
Started Apr 30 03:02:59 PM PDT 24
Finished Apr 30 03:15:19 PM PDT 24
Peak memory 202260 kb
Host smart-0b7b529b-34c5-4d5e-b1eb-7e178677f490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081172838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.4081172838
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2114457473
Short name T537
Test name
Test status
Simulation time 161692529665 ps
CPU time 100.48 seconds
Started Apr 30 03:02:47 PM PDT 24
Finished Apr 30 03:04:28 PM PDT 24
Peak memory 202256 kb
Host smart-d6677873-7b12-4652-84e1-762096dc8fa8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114457473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2114457473
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.285606874
Short name T326
Test name
Test status
Simulation time 594911964946 ps
CPU time 371.64 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:09:06 PM PDT 24
Peak memory 202272 kb
Host smart-ae757a82-0bec-4fcc-924d-4d9761047a7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285606874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.285606874
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.331256704
Short name T542
Test name
Test status
Simulation time 618345554447 ps
CPU time 267.88 seconds
Started Apr 30 03:02:55 PM PDT 24
Finished Apr 30 03:07:24 PM PDT 24
Peak memory 201456 kb
Host smart-a6b88cf0-14eb-4bc5-8c4a-83ee6e7d31d2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331256704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.331256704
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.4016323212
Short name T372
Test name
Test status
Simulation time 76438136798 ps
CPU time 268.29 seconds
Started Apr 30 03:02:50 PM PDT 24
Finished Apr 30 03:07:19 PM PDT 24
Peak memory 202660 kb
Host smart-aa624a73-ebcd-42c4-8169-119f44829438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016323212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.4016323212
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.424763482
Short name T374
Test name
Test status
Simulation time 34099866523 ps
CPU time 76.67 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:04:10 PM PDT 24
Peak memory 202124 kb
Host smart-5d4f987d-adcf-4b70-9b4d-78d3a9ca1c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424763482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.424763482
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2287584035
Short name T568
Test name
Test status
Simulation time 5305446652 ps
CPU time 13.63 seconds
Started Apr 30 03:03:02 PM PDT 24
Finished Apr 30 03:03:17 PM PDT 24
Peak memory 202104 kb
Host smart-c09ffaaf-11df-422e-a2a6-28a7fc462aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287584035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2287584035
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.908424461
Short name T710
Test name
Test status
Simulation time 5852427245 ps
CPU time 15.57 seconds
Started Apr 30 03:02:53 PM PDT 24
Finished Apr 30 03:03:10 PM PDT 24
Peak memory 202124 kb
Host smart-ba9f4680-1ac2-4167-b3dc-5a7e2023bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908424461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.908424461
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.3858712181
Short name T262
Test name
Test status
Simulation time 217327622638 ps
CPU time 440.68 seconds
Started Apr 30 03:02:50 PM PDT 24
Finished Apr 30 03:10:11 PM PDT 24
Peak memory 202272 kb
Host smart-d1177eb0-20bd-49ba-89fb-62628eadc5a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858712181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
3858712181
Directory /workspace/9.adc_ctrl_stress_all/latest
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