Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6991	1			T3	45		T5	40		T7	20
testmodes[AdcCtrlTestmodeNormal]	5455	1			T1	2		T3	54		T5	1
testmodes[AdcCtrlTestmodeLowpower]	5415	1			T2	2		T3	56		T4	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3945	1			T3	15		T5	39		T7	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1723	1			T3	12		T36	16		T51	20
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1203	1			T3	17		T36	7		T51	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1734	1			T3	15		T5	1		T36	15
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2058	1			T1	1		T3	24		T9	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1331	1			T3	15		T36	14		T48	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1201	1			T3	15		T36	8		T51	20
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1328	1			T3	18		T9	1		T36	12
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2640	1			T2	1		T3	23		T4	2