Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22642

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3410

1

T9

39

T11

14

T47

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20087

1

T3

155

T5

41

T7

20

auto[1]

5965

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	11	1			T146	1		T192	2		T153	1
values[1]	676	1			T11	14		T48	32		T133	16
values[2]	3099	1			T1	2		T2	31		T4	37
values[3]	738	1			T43	2		T15	30		T16	8
values[4]	798	1			T47	22		T48	24		T50	14
values[5]	689	1			T11	2		T49	24		T50	7
values[6]	729	1			T9	15		T49	7		T50	9
values[7]	625	1			T40	13		T35	9		T82	1
values[8]	610	1			T9	26		T49	1		T43	1
values[9]	1195	1			T5	1		T9	13		T11	12
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	864	1			T48	32		T25	17		T84	7
values[1]	3039	1			T1	2		T2	31		T4	37
values[2]	803	1			T48	24		T43	2		T15	30
values[3]	770	1			T47	22		T49	24		T50	14
values[4]	748	1			T9	15		T11	2		T50	7
values[5]	621	1			T49	7		T50	9		T34	17
values[6]	634	1			T9	26		T40	13		T35	9
values[7]	624	1			T47	16		T49	1		T136	19
values[8]	678	1			T5	1		T82	6		T84	3
values[9]	372	1			T9	13		T11	12		T136	17
minimum	16899	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T48	16		T25	11		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T193	1		T180	1		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1731	1			T1	2		T2	31		T4	37
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T126	15		T194	14		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T85	10		T131	12		T195	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T48	14		T43	1		T15	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T24	15		T15	12		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T47	13		T49	18		T50	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	11		T50	5		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T17	3		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T49	1		T34	11		T14	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T50	5		T43	1		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T40	13		T35	4		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	20		T35	3		T119	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T136	3		T137	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T47	5		T49	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T5	1		T82	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T196	3		T197	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T198	3		T199	1		T200	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T9	2		T11	5		T136	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16762	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T48	16		T25	6		T84	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T146	12		T201	4		T202	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T10	20		T11	5		T12	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T194	10		T203	12		T168	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T85	2		T131	11		T195	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	10		T43	1		T15	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T24	12		T15	10		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T47	9		T49	6		T50	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	4		T50	2		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T17	4		T124	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	6		T34	6		T14	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T50	4		T121	9		T122	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	2		T119	13		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	6		T119	8		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T136	16		T120	10		T204	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	11		T119	11		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T82	5		T84	2		T168	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T196	4		T205	1		T206	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T200	7		T207	2		T208	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	11		T11	7		T136	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T34	1		T35	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T209	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T146	1		T192	2		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T11	9		T48	16		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T193	1		T180	1		T146	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1749	1			T1	2		T2	31		T4	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T127	11		T194	14		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T131	12		T196	9		T147	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T43	1		T15	17		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T24	3		T85	10		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T47	13		T48	14		T50	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T50	5		T14	2		T24	31
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	1		T49	18		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	11		T49	1		T34	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T50	5		T43	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T40	13		T35	4		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T35	3		T137	1		T119	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T43	1		T136	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	20		T49	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T5	1		T82	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	2		T11	5		T47	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T209	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	5		T48	16		T133	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T146	12		T201	4		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T10	20		T12	9		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T194	10		T203	12		T210	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T131	11		T196	9		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T43	1		T15	13		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T24	2		T85	2		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	9		T48	10		T50	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	2		T14	1		T24	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T49	6		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	4		T49	6		T34	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	4		T121	9		T122	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T35	2		T85	13		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T119	8		T123	1		T205	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	16		T119	13		T120	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	6		T120	6		T195	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T82	5		T84	2		T168	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T9	11		T11	7		T47	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T48	17		T25	12		T84	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T193	1		T180	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T1	2		T2	2		T4	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T126	1		T194	11		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T85	3		T131	12		T195	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	11		T43	2		T15	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T24	14		T15	13		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T47	10		T49	7		T50	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	5		T50	3		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	2		T17	5		T124	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T49	7		T34	10		T14	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T50	5		T43	1		T121	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	1		T35	5		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	7		T35	2		T119	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	17		T137	1		T120	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	12		T49	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T82	6		T84	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T196	5		T197	1		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T198	1		T199	1		T200	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	12		T11	8		T136	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T48	15		T25	5		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T127	10		T146	15		T201	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1394	1			T2	29		T4	34		T6	47
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T126	14		T194	13		T203	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T85	9		T131	11		T195	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	13		T15	14		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T24	13		T15	9		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T47	12		T49	17		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	10		T50	4		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	2		T135	12		T125	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T34	7		T14	9		T85	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T50	4		T122	8		T128	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T40	12		T35	1		T119	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T9	19		T35	1		T119	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T136	2		T204	19		T212	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T47	4		T119	4		T195	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T126	12		T127	18		T168	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T196	2		T213	11		T206	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T198	2		T200	9		T207	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	1		T11	4		T136	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	9	39	81.25	9

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum , values[0]]	*	--	--	4
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T209	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T146	1		T192	2		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	6		T48	17		T133	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T193	1		T180	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T1	2		T2	2		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T127	1		T194	11		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T131	12		T196	10		T147	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	2		T15	16		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T24	3		T85	3		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T47	10		T48	11		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T50	3		T14	2		T24	30
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	2		T49	7		T37	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	5		T49	7		T34	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	5		T43	1		T121	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T40	1		T35	5		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	2		T137	1		T119	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	1		T136	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	7		T49	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T5	1		T82	6		T84	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T9	12		T11	8		T47	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	8		T48	15		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T146	15		T201	4		T173	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1399	1			T2	29		T4	34		T6	47
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T127	10		T194	13		T203	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T131	11		T196	8		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	14		T16	2		T126	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T24	2		T85	9		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T47	12		T48	13		T50	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	4		T14	1		T24	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T49	17		T37	1		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	10		T34	7		T14	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T50	4		T122	8		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T40	12		T35	1		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T35	1		T119	1		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T136	2		T119	13		T204	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	19		T195	12		T211	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T126	12		T127	18		T198	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	1		T11	4		T47	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22677

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3375

1

T11

16

T47

22

T48

56

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19887

1

T3

155

T5

41

T7

20

auto[1]

6165

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41	1			T180	1		T215	19		T90	10
values[1]	485	1			T47	16		T48	32		T49	24
values[2]	767	1			T48	24		T84	7		T37	1
values[3]	786	1			T5	1		T9	26		T47	22
values[4]	2962	1			T1	2		T2	31		T4	37
values[5]	648	1			T9	15		T24	22		T122	28
values[6]	564	1			T49	7		T50	16		T211	18
values[7]	616	1			T11	2		T49	1		T82	6
values[8]	995	1			T11	14		T50	14		T14	29
values[9]	1306	1			T9	13		T11	12		T34	17
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	759	1			T47	16		T48	32		T49	24
values[1]	660	1			T48	24		T24	5		T37	1
values[2]	714	1			T5	1		T9	26		T47	22
values[3]	3009	1			T1	2		T2	31		T4	37
values[4]	670	1			T9	15		T24	22		T122	28
values[5]	663	1			T50	16		T82	6		T124	15
values[6]	561	1			T11	2		T49	8		T14	29
values[7]	1025	1			T9	13		T11	26		T50	14
values[8]	856	1			T34	17		T40	13		T43	3
values[9]	253	1			T134	6		T160	23		T130	1
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T47	5		T49	18		T14	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T48	16		T120	1		T122	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T24	3		T37	1		T133	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	14		T136	3		T119	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T9	20		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	13		T84	1		T131	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T1	2		T2	31		T4	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T35	4		T43	1		T15	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	11		T24	12		T122	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T132	1		T46	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T50	10		T82	1		T124	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T128	13		T138	1		T216	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T49	2		T14	14		T16	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	1		T214	11		T198	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T9	2		T11	5		T50	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T11	9		T35	3		T85	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T34	11		T43	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	13		T43	1		T82	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T134	6		T217	17		T218	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T160	12		T130	1		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	11		T49	6		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	16		T120	6		T122	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T24	2		T133	15		T119	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	10		T136	16		T119	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	6		T160	3		T219	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T47	9		T84	6		T131	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	879	1			T10	20		T12	9		T13	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	2		T15	13		T119	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	4		T24	10		T122	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T46	4		T139	1		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	6		T82	5		T124	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T216	11		T140	8		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T49	6		T14	15		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	1		T222	1		T205	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T9	11		T11	7		T50	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	5		T85	2		T136	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T34	6		T43	1		T84	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T136	8		T124	10		T196	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T218	4		T223	10		T224	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T160	11		T124	14		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T215	12		T90	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T180	1		T225	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T47	5		T49	18		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T48	16		T120	1		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	1		T133	3		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	14		T84	1		T136	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T9	20		T24	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T47	13		T119	14		T131	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T1	2		T2	31		T4	37
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T35	4		T43	1		T15	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	11		T24	12		T122	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T132	1		T46	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	1		T50	10		T211	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T128	13		T138	2		T216	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	1		T82	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T85	10		T214	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T50	7		T14	14		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	9		T136	18		T143	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	390	1			T9	2		T11	5		T34	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T40	13		T35	3		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T215	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T225	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T47	11		T49	6		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T48	16		T120	6		T131	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T133	2		T119	8		T146	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T48	10		T84	6		T136	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	6		T24	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T47	9		T119	13		T131	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	879	1			T10	20		T12	9		T13	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T35	2		T15	13		T119	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	4		T24	10		T122	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T46	4		T139	1		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T49	6		T50	6		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T216	11		T140	8		T200	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T82	5		T16	2		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	1		T85	2		T204	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T50	7		T14	15		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	5		T136	20		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T9	11		T11	7		T34	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T136	8		T160	11		T124	24
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4