Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22800

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3252

1

T5

1

T9

26

T11

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20022

1

T3

155

T5

40

T7

20

auto[1]

6030

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	283	1			T43	1		T24	5		T133	16
values[0]	9	1			T193	1		T235	8		-	-
values[1]	774	1			T50	14		T35	3		T14	29
values[2]	650	1			T11	2		T49	7		T84	3
values[3]	669	1			T34	17		T24	37		T82	6
values[4]	608	1			T49	25		T43	1		T136	17
values[5]	792	1			T35	6		T24	22		T25	17
values[6]	657	1			T47	16		T40	13		T137	2
values[7]	689	1			T5	1		T9	15		T48	24
values[8]	805	1			T9	26		T47	22		T48	32
values[9]	3234	1			T1	2		T2	31		T4	37
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	750	1			T49	7		T50	14		T35	3
values[1]	641	1			T11	2		T82	6		T15	22
values[2]	654	1			T49	1		T34	17		T43	1
values[3]	616	1			T49	24		T35	6		T15	30
values[4]	804	1			T24	22		T25	17		T84	7
values[5]	752	1			T5	1		T9	15		T47	16
values[6]	3000	1			T1	2		T2	31		T4	37
values[7]	804	1			T9	26		T11	26		T47	22
values[8]	814	1			T9	13		T14	3		T24	5
values[9]	141	1			T43	1		T119	26		T285	1
minimum	17076	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T49	1		T84	1		T133	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T50	7		T35	3		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	12		T195	13		T132	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T11	1		T82	1		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T34	11		T130	1		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	1		T43	1		T24	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	18		T35	4		T15	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T143	14		T125	9		T194	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T25	11		T84	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T24	12		T136	18		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	11		T47	5		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T126	13		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1760	1			T1	2		T2	31		T4	37
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	30		T85	10		T195	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	9		T47	13		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	20		T11	5		T50	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	2		T14	2		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T120	1		T17	3		T131	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T119	2		T20	8		T226	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T43	1		T119	5		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16823	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T193	1		T257	1		T243	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	6		T84	2		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T50	7		T122	19		T196	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T15	10		T195	14		T132	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	1		T82	5		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T34	6		T131	8		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T24	18		T17	5		T131	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	6		T35	2		T15	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T143	13		T194	10		T229	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T25	6		T84	6		T211	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	10		T136	20		T121	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	4		T47	11		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T123	1		T124	14		T222	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T10	20		T12	9		T13	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T48	26		T85	2		T195	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	5		T47	9		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	6		T11	7		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	11		T14	1		T24	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T120	10		T17	4		T131	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T119	8		T20	4		T234	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T119	11		T286	13		T287	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	1		T35	2		T14	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T243	2		T288	1		T289	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T24	3		T133	3		T135	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T43	1		T119	5		T120	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T235	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T193	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	14		T133	3		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T50	7		T35	3		T122	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	1		T84	1		T15	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T37	6		T119	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T34	11		T137	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T24	19		T82	1		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T49	18		T136	9		T134	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T49	1		T43	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T35	4		T25	11		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	12		T136	18		T121	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	5		T40	13		T137	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T126	13		T123	1		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T9	11		T266	5		T214	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T48	14		T85	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T47	13		T50	5		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	20		T48	16		T50	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1747	1			T1	2		T2	31		T4	37
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T11	5		T17	3		T180	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T24	2		T133	13		T290	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T119	11		T120	10		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T235	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T14	15		T133	2		T145	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T50	7		T122	19		T196	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T49	6		T84	2		T15	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	1		T37	1		T119	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	6		T147	10		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T24	18		T82	5		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T49	6		T136	8		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T143	13		T196	9		T194	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T35	2		T25	6		T84	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	10		T136	20		T121	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T47	11		T160	11		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T123	1		T124	14		T196	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	4		T18	3		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	10		T85	2		T195	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T47	9		T50	4		T43	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	6		T48	16		T50	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T9	11		T10	20		T11	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	7		T17	4		T131	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T49	7		T84	3		T133	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T50	8		T35	2		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T15	13		T195	15		T132	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	2		T82	6		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T34	10		T130	1		T131	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T49	1		T43	1		T24	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T49	7		T35	5		T15	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T143	14		T125	1		T194	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T25	12		T84	7		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T24	11		T136	21		T121	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T9	5		T47	12		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	1		T126	1		T123	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T1	2		T2	2		T4	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T48	28		T85	3		T195	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T11	6		T47	10		T43	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	7		T11	8		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T9	12		T14	2		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T120	11		T17	5		T131	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T119	9		T20	9		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T43	1		T119	12		T285	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16988	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T193	1		T257	1		T243	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T133	2		T127	10		T145	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	6		T35	1		T122	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T15	9		T195	12		T132	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T37	1		T119	13		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T34	7		T131	11		T146	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T24	18		T17	1		T131	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T49	17		T35	1		T15	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T143	13		T125	8		T194	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T25	5		T211	10		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T24	11		T136	17		T196	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	10		T47	4		T40	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T126	12		T128	11		T221	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T2	29		T4	34		T6	47
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T48	28		T85	9		T195	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	8		T47	12		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	19		T11	4		T50	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T14	1		T24	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T17	2		T131	11		T127	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T119	1		T20	3		T226	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T119	4		T287	9		T291	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T14	9		T234	5		T231	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T231	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T24	3		T133	14		T135	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T43	1		T119	12		T120	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T235	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T193	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	20		T133	3		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	8		T35	2		T122	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T49	7		T84	3		T15	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	2		T37	6		T119	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T34	10		T137	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T24	19		T82	6		T17	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	7		T136	9		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T49	1		T43	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T35	5		T25	12		T84	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T24	11		T136	21		T121	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	12		T40	1		T137	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T126	1		T123	2		T124	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	5		T266	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T48	11		T85	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T47	10		T50	5		T43	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	7		T48	17		T50	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T1	2		T2	2		T4	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	8		T17	5		T180	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T24	2		T133	2		T135	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T119	4		T198	8		T135	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	9		T133	2		T127	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T50	6		T35	1		T122	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T15	9		T195	12		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T37	1		T119	13		T122	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	7		T146	3		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T24	18		T17	1		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T49	17		T136	8		T134	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T143	13		T125	8		T196	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T35	1		T25	5		T15	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T24	11		T136	17		T292	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	4		T40	12		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T126	12		T128	11		T196	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	10		T266	4		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T48	13		T85	9		T195	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T47	12		T50	4		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	19		T48	15		T50	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T2	29		T4	34		T6	47
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	4		T17	2		T131	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47