Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22615

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3437

1

T9

39

T11

14

T47

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20075

1

T3

155

T5

41

T7

20

auto[1]

5977

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	278	1			T5	1		T11	12		T136	17
values[0]	16	1			T146	1		T153	1		T254	7
values[1]	686	1			T11	14		T48	32		T133	16
values[2]	3058	1			T1	2		T2	31		T4	37
values[3]	826	1			T48	24		T43	2		T15	30
values[4]	759	1			T47	22		T49	24		T50	14
values[5]	684	1			T11	2		T14	3		T24	59
values[6]	703	1			T9	15		T49	7		T50	16
values[7]	656	1			T40	13		T35	9		T82	1
values[8]	580	1			T9	26		T49	1		T43	1
values[9]	924	1			T9	13		T47	16		T82	6
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	748	1			T11	14		T25	17		T84	7
values[1]	3043	1			T1	2		T2	31		T4	37
values[2]	791	1			T48	24		T43	2		T15	30
values[3]	737	1			T47	22		T49	24		T50	14
values[4]	739	1			T9	15		T11	2		T50	9
values[5]	659	1			T49	7		T50	7		T43	1
values[6]	632	1			T9	26		T40	13		T35	9
values[7]	616	1			T47	16		T49	1		T136	19
values[8]	861	1			T5	1		T9	13		T82	6
values[9]	193	1			T11	12		T198	3		T19	7
minimum	17033	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T11	9		T25	11		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T193	1		T180	1		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1723	1			T1	2		T2	31		T4	37
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T194	14		T148	12		T203	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T131	12		T195	12		T124	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T48	14		T43	1		T15	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T24	15		T85	10		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T47	13		T49	18		T50	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	11		T34	11		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	1		T50	5		T17	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T49	1		T50	5		T14	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T43	1		T121	1		T122	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T40	13		T35	4		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	20		T35	3		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T136	3		T137	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T47	5		T49	1		T119	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	1		T82	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	2		T136	9		T196	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T198	3		T19	6		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T11	5		T290	9		T293	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16807	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T192	2		T173	12		T153	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	5		T25	6		T84	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T146	12		T201	4		T162	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T10	20		T12	9		T13	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T194	10		T148	10		T203	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T131	11		T195	13		T124	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T48	10		T43	1		T15	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T24	12		T85	2		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	9		T49	6		T50	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	4		T34	6		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T50	4		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	6		T50	2		T14	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T121	9		T122	19		T147	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	2		T85	13		T119	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	6		T119	8		T123	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T136	16		T120	10		T204	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T47	11		T119	11		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T82	5		T84	2		T168	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	11		T136	8		T196	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T19	1		T200	7		T207	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T11	7		T290	9		T293	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	16		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T173	10		T284	11		T294	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T5	1		T198	3		T19	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T11	5		T136	9		T206	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T254	1		T209	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T146	1		T153	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	9		T48	16		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T180	1		T127	11		T146	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1743	1			T1	2		T2	31		T4	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T193	1		T194	14		T203	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T131	12		T195	12		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T48	14		T43	1		T15	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T24	3		T85	10		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T47	13		T49	18		T50	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T14	2		T24	31		T15	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	1		T18	6		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	11		T49	1		T50	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T50	5		T43	1		T121	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T40	13		T35	4		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T35	3		T137	1		T119	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	1		T136	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	20		T49	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T82	1		T84	1		T126	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	2		T47	5		T119	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T19	1		T259	12		T200	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T11	7		T136	8		T206	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T254	6		T209	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	5		T48	16		T133	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T146	12		T201	4		T202	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T10	20		T12	9		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T194	10		T203	12		T149	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T131	11		T195	13		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	10		T43	1		T15	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T24	2		T85	2		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T47	9		T49	6		T50	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T24	28		T15	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T18	3		T124	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	4		T49	6		T50	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	4		T121	9		T122	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T35	2		T85	13		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T119	8		T123	1		T205	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	16		T119	13		T120	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T9	6		T120	6		T195	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T82	5		T84	2		T168	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T9	11		T47	11		T119	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	6		T25	12		T84	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T193	1		T180	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T1	2		T2	2		T4	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T194	11		T148	11		T203	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T131	12		T195	14		T124	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	11		T43	2		T15	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T24	14		T85	3		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T47	10		T49	7		T50	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	5		T34	10		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	2		T50	5		T17	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T49	7		T50	3		T14	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T43	1		T121	10		T122	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T40	1		T35	5		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	7		T35	2		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T136	17		T137	1		T120	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	12		T49	1		T119	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T82	6		T84	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T9	12		T136	9		T196	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T198	1		T19	7		T199	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T11	8		T290	10		T293	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16948	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T192	2		T173	11		T153	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	8		T25	5		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T127	10		T146	15		T201	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1386	1			T2	29		T4	34		T6	47
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T194	13		T148	11		T203	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T131	11		T195	11		T128	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	13		T15	14		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T24	13		T85	9		T133	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	12		T49	17		T50	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	10		T34	7		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T50	4		T17	2		T135	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T50	4		T14	9		T134	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T122	8		T128	12		T147	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T40	12		T35	1		T85	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	19		T35	1		T119	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T136	2		T204	19		T212	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T47	4		T119	4		T195	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T126	12		T127	18		T168	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	1		T136	8		T196	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T198	2		T200	9		T207	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T11	4		T290	8		T293	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T48	15		T237	5		T253	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T173	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T5	1		T198	1		T19	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T11	8		T136	9		T206	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T254	7		T209	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T146	1		T153	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	6		T48	17		T133	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T180	1		T127	1		T146	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T1	2		T2	2		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T193	1		T194	11		T203	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T131	12		T195	14		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	11		T43	2		T15	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T24	3		T85	3		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T47	10		T49	7		T50	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T14	2		T24	30		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	2		T18	7		T124	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	5		T49	7		T50	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T50	5		T43	1		T121	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T40	1		T35	5		T82	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T35	2		T137	1		T119	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T43	1		T136	17		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T9	7		T49	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T82	6		T84	3		T126	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T9	12		T47	12		T119	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T198	2		T200	9		T218	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T11	4		T136	8		T206	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	8		T48	15		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T127	10		T146	15		T201	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T2	29		T4	34		T6	47
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T194	13		T203	12		T172	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T131	11		T195	11		T128	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	13		T15	14		T16	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T24	2		T85	9		T133	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T47	12		T49	17		T50	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	1		T24	29		T15	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T18	2		T125	8		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	10		T50	4		T34	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T50	4		T122	8		T17	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T40	12		T35	1		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	1		T119	1		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T136	2		T119	13		T204	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	19		T195	12		T211	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T126	12		T127	18		T168	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	1		T47	4		T119	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47