Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22526

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3526

1

T5

1

T9

39

T11

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19870

1

T3

150

T5

41

T7

20

auto[1]

6182

1

T1

2

T2

31

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	434	1			T3	5		T36	9		T51	3
values[0]	50	1			T265	13		T295	12		T296	25
values[1]	569	1			T34	17		T43	2		T37	6
values[2]	3025	1			T1	2		T2	31		T4	37
values[3]	595	1			T11	14		T47	16		T50	14
values[4]	711	1			T43	1		T24	27		T133	5
values[5]	841	1			T11	12		T50	16		T40	13
values[6]	719	1			T48	32		T35	3		T25	17
values[7]	605	1			T9	15		T11	2		T49	24
values[8]	679	1			T9	26		T47	22		T49	1
values[9]	1351	1			T5	1		T48	24		T49	7
minimum	16473	1			T3	150		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	778	1			T43	2		T15	22		T85	19
values[1]	2933	1			T1	2		T2	31		T4	37
values[2]	649	1			T11	14		T43	1		T24	22
values[3]	904	1			T50	14		T40	13		T14	29
values[4]	662	1			T11	12		T50	16		T82	6
values[5]	642	1			T48	32		T35	3		T14	3
values[6]	645	1			T9	15		T11	2		T47	22
values[7]	713	1			T9	26		T49	25		T35	6
values[8]	897	1			T5	1		T48	24		T49	7
values[9]	323	1			T136	17		T122	28		T130	1
minimum	16906	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T43	1		T85	6		T198	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T15	12		T37	5		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T1	2		T2	31		T4	37
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	2		T127	19		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T119	5		T16	6		T266	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	9		T43	1		T24	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T50	7		T40	13		T14	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T24	3		T137	2		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	5		T136	3		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	10		T82	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	16		T35	3		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T25	11		T15	17		T122	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	11		T11	1		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	13		T24	19		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T49	1		T37	1		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	20		T49	18		T35	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	1		T167	10		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T5	1		T48	14		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T136	9		T122	9		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T130	1		T238	9		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T34	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	1		T85	13		T211	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T15	10		T37	1		T120	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	909	1			T10	20		T12	9		T13	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	11		T124	14		T237	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T119	11		T16	2		T195	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	5		T24	10		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	7		T14	15		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T24	2		T146	12		T124	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T11	7		T136	16		T120	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T50	6		T82	5		T290	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T48	16		T14	1		T119	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T25	6		T15	13		T122	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	4		T11	1		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	9		T24	18		T131	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T133	13		T160	11		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	6		T49	6		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	6		T167	11		T160	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T48	10		T136	20		T17	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T136	8		T122	19		T123	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T238	8		T298	7		T189	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T34	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	422	1			T3	5		T36	9		T51	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T296	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T265	8		T295	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T43	1		T120	1		T206	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T34	11		T37	5		T120	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1710	1			T1	2		T2	31		T4	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	2		T15	12		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T47	5		T50	7		T119	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	9		T126	13		T127	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T133	3		T239	7		T211	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T43	1		T24	15		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T11	5		T40	13		T14	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T50	10		T82	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T48	16		T35	3		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T25	11		T15	17		T131	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	11		T11	1		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T49	18		T121	1		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T49	1		T37	1		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	20		T47	13		T35	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T49	1		T133	3		T136	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T5	1		T48	14		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16350	1			T3	150		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T216	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T296	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T265	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T43	1		T120	6		T206	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T34	6		T37	1		T120	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T10	20		T12	9		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	11		T15	10		T124	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T47	11		T50	7		T119	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T11	5		T148	2		T202	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T133	2		T239	6		T211	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T24	12		T146	12		T124	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T11	7		T14	15		T84	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T50	6		T82	5		T227	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T48	16		T136	16		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T25	6		T15	13		T131	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	4		T11	1		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T49	6		T121	9		T122	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T160	11		T147	10		T297	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	6		T47	9		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T49	6		T133	13		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T48	10		T136	20		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T43	2		T85	14		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T15	13		T37	5		T120	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T1	2		T2	2		T4	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	12		T127	1		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T119	12		T16	6		T266	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	6		T43	1		T24	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T50	8		T40	1		T14	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T24	3		T137	2		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	8		T136	17		T120	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T50	8		T82	6		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	17		T35	2		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	12		T15	16		T122	20
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T9	5		T11	2		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T47	10		T24	19		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T49	1		T37	1		T133	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T9	7		T49	7		T35	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	7		T167	12		T160	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T5	1		T48	11		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T136	9		T122	20		T232	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T130	1		T238	9		T297	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16889	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T34	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T85	5		T198	2		T211	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T15	9		T37	1		T17	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T2	29		T4	34		T6	47
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	1		T127	18		T237	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T119	4		T16	2		T266	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	8		T24	11		T126	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T50	6		T40	12		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T24	2		T126	14		T146	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T11	4		T136	2		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T50	8		T21	3		T174	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	15		T35	1		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T25	5		T15	14		T122	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T9	10		T143	13		T132	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T47	12		T24	18		T131	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T133	2		T160	11		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T9	19		T49	17		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T167	9		T160	2		T128	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T48	13		T136	17		T134	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T136	8		T122	8		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T238	8		T298	11		T189	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T34	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	421	1			T3	5		T36	9		T51	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T296	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T265	11		T295	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T43	2		T120	7		T206	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T34	10		T37	5		T120	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T1	2		T2	2		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	12		T15	13		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T47	12		T50	8		T119	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T11	6		T126	1		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T133	3		T239	7		T211	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T43	1		T24	14		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T11	8		T40	1		T14	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T50	8		T82	6		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	17		T35	2		T82	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T25	12		T15	16		T131	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	5		T11	2		T14	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T49	7		T121	10		T122	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T49	1		T37	1		T160	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T9	7		T47	10		T35	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T49	7		T133	14		T136	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	455	1			T5	1		T48	11		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T3	150		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T216	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T296	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T265	2		T295	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T206	4		T210	3		T253	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	7		T37	1		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T2	29		T4	34		T6	47
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T9	1		T15	9		T237	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	4		T50	6		T119	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T11	8		T126	12		T127	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T133	2		T239	6		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T24	13		T146	15		T248	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	4		T40	12		T14	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T50	8		T126	14		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T48	15		T35	1		T136	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T25	5		T15	14		T131	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	10		T14	1		T119	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T49	17		T122	10		T212	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T160	11		T147	9		T217	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	19		T47	12		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T133	2		T136	8		T122	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T48	13		T136	17		T134	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47