Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22526

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3526

1

T5

1

T9

26

T11

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19983

1

T3

150

T5

41

T7

20

auto[1]

6069

1

T1

2

T2

31

T3

5

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	722	1			T3	5		T36	9		T51	3
values[0]	25	1			T265	13		T295	12		-	-
values[1]	564	1			T34	17		T43	2		T37	6
values[2]	3052	1			T1	2		T2	31		T4	37
values[3]	584	1			T11	14		T119	16		T16	8
values[4]	749	1			T50	14		T43	1		T24	27
values[5]	878	1			T11	12		T50	16		T40	13
values[6]	597	1			T48	32		T35	3		T25	17
values[7]	593	1			T9	15		T11	2		T14	3
values[8]	759	1			T9	26		T47	22		T49	25
values[9]	1056	1			T5	1		T48	24		T49	7
minimum	16473	1			T3	150		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	665	1			T34	17		T43	2		T85	19
values[1]	2950	1			T1	2		T2	31		T4	37
values[2]	604	1			T11	14		T43	1		T119	16
values[3]	915	1			T50	14		T40	13		T14	29
values[4]	724	1			T11	12		T50	16		T25	17
values[5]	606	1			T48	32		T35	3		T14	3
values[6]	653	1			T9	15		T11	2		T47	22
values[7]	658	1			T9	26		T49	1		T35	6
values[8]	942	1			T5	1		T48	24		T49	7
values[9]	293	1			T122	28		T130	1		T123	2
minimum	17042	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T34	11		T43	1		T85	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T17	6		T198	3		T204	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1660	1			T1	2		T2	31		T4	37
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T15	12		T127	19		T198	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	9		T119	5		T16	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T43	1		T124	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T50	7		T40	13		T14	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T24	15		T137	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	5		T120	1		T195	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T50	10		T25	11		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T48	16		T35	3		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T82	1		T15	17		T119	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	11		T193	1		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	1		T47	13		T49	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T49	1		T37	1		T133	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	20		T35	4		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T49	1		T136	27		T167	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T5	1		T48	14		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T123	1		T128	13		T147	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T122	9		T130	1		T222	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16799	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T37	5		T120	1		T265	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T34	6		T43	1		T85	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T17	5		T204	11		T124	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T9	11		T10	20		T12	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T15	10		T237	4		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	5		T119	11		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T124	14		T202	7		T210	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T50	7		T14	15		T84	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T24	12		T146	12		T227	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	7		T120	6		T195	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T50	6		T25	6		T82	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	16		T14	1		T119	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T15	13		T119	8		T122	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	4		T143	13		T132	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	1		T47	9		T49	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T133	13		T147	10		T141	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	6		T35	2		T84	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	6		T136	28		T167	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T48	10		T17	4		T131	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T123	1		T147	9		T222	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T122	19		T222	12		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T37	1		T120	10		T265	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	513	1			T3	5		T36	9		T51	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T130	1		T216	13		T240	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T295	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T265	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T34	11		T43	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T37	5		T120	1		T17	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1685	1			T1	2		T2	31		T4	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T15	12		T198	18		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	9		T119	5		T16	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T127	19		T132	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T50	7		T133	3		T211	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T43	1		T24	15		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T11	5		T40	13		T14	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T50	10		T82	1		T136	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	16		T35	3		T119	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	11		T82	1		T15	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	11		T14	2		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T11	1		T119	2		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	1		T37	1		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T9	20		T47	13		T49	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T49	1		T133	3		T136	27
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	1		T48	14		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16350	1			T3	150		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T167	11		T147	9		T46	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T216	11		T263	8		T300	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T265	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	6		T43	1		T120	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T37	1		T120	10		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T9	11		T10	20		T12	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T15	10		T237	4		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	5		T119	11		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T202	7		T210	4		T290	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	7		T133	2		T211	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T24	12		T146	12		T124	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	7		T14	15		T84	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T50	6		T82	5		T136	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T48	16		T119	13		T139	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T25	6		T15	13		T131	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	4		T14	1		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	1		T119	8		T121	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	15		T147	10		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	6		T47	9		T49	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	6		T133	13		T136	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T48	10		T122	19		T17	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T34	10		T43	2		T85	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T17	10		T198	1		T204	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	2		T2	2		T4	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T15	13		T127	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T11	6		T119	12		T16	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T43	1		T124	15		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T50	8		T40	1		T14	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T24	14		T137	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	8		T120	7		T195	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T50	8		T25	12		T82	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T48	17		T35	2		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T82	1		T15	16		T119	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	5		T193	1		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	2		T47	10		T49	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T49	1		T37	1		T133	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T9	7		T35	5		T84	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T49	7		T136	30		T167	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T5	1		T48	11		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T123	2		T128	1		T147	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T122	20		T130	1		T222	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16908	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T37	5		T120	11		T265	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T34	7		T85	5		T211	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T17	1		T198	2		T204	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	29		T4	34		T6	47
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T15	9		T127	18		T198	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	8		T119	4		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T210	2		T290	8		T301	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T50	6		T40	12		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T24	13		T146	15		T227	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	4		T195	12		T292	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T50	8		T25	5		T136	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	15		T35	1		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T15	14		T119	1		T122	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	10		T143	13		T132	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T47	12		T49	17		T24	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T133	2		T147	9		T220	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	19		T35	1		T160	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T136	25		T167	9		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T48	13		T134	5		T17	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T128	12		T147	10		T205	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T122	8		T222	13		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T253	12		T295	11		T247	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T37	1		T265	2		T302	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	509	1			T3	5		T36	9		T51	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T130	1		T216	12		T240	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T295	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T265	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T34	10		T43	2		T120	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T37	5		T120	11		T17	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T1	2		T2	2		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T15	13		T198	2		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	6		T119	12		T16	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T127	1		T132	1		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T50	8		T133	3		T211	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T43	1		T24	14		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T11	8		T40	1		T14	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T50	8		T82	6		T136	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T48	17		T35	2		T119	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T25	12		T82	1		T15	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	5		T14	2		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	2		T119	9		T121	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T49	1		T37	1		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T9	7		T47	10		T49	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T49	7		T133	14		T136	30
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T5	1		T48	11		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16473	1			T3	150		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T167	9		T128	11		T147	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T216	12		T263	2		T300	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T295	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T265	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T34	7		T206	4		T210	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	1		T17	1		T204	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T2	29		T4	34		T6	47
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T15	9		T198	16		T237	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T11	8		T119	4		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T127	18		T210	2		T290	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T50	6		T133	2		T211	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T24	13		T146	15		T201	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T11	4		T40	12		T14	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T50	8		T136	2		T127	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T48	15		T35	1		T119	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	5		T15	14		T131	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	10		T14	1		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T119	1		T122	10		T248	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T132	14		T147	9		T220	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	19		T47	12		T49	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T133	2		T136	25		T160	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T48	13		T134	5		T122	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47