Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22889

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3163

1

T5

1

T9

13

T11

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19816

1

T3

155

T5

40

T7

20

auto[1]

6236

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	299	1			T24	37		T82	6		T85	19
values[0]	23	1			T19	7		T295	8		T244	8
values[1]	603	1			T11	14		T14	3		T84	7
values[2]	601	1			T47	22		T50	7		T193	1
values[3]	611	1			T48	32		T82	1		T15	22
values[4]	713	1			T11	2		T24	22		T136	19
values[5]	765	1			T9	26		T48	24		T35	6
values[6]	475	1			T43	2		T120	11		T160	23
values[7]	815	1			T5	1		T11	12		T40	13
values[8]	3254	1			T1	2		T2	31		T4	37
values[9]	1011	1			T9	15		T47	16		T49	31
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	532	1			T14	3		T84	7		T136	55
values[1]	607	1			T47	22		T50	7		T193	1
values[2]	619	1			T48	32		T82	1		T15	22
values[3]	746	1			T9	26		T11	2		T35	6
values[4]	743	1			T48	24		T43	2		T133	16
values[5]	600	1			T5	1		T11	12		T40	13
values[6]	3158	1			T1	2		T2	31		T4	37
values[7]	808	1			T49	1		T34	17		T134	6
values[8]	988	1			T9	15		T47	16		T49	24
values[9]	170	1			T49	7		T24	37		T84	3
minimum	17081	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	2		T84	1		T126	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T136	27		T134	1		T126	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	13		T193	1		T198	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T50	5		T122	9		T160	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	12		T17	6		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	16		T82	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	20		T136	3		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	1		T35	4		T24	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T43	1		T130	1		T146	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T48	14		T133	3		T121	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	13		T85	10		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	1		T11	5		T127	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1793	1			T1	2		T2	31		T4	37
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	2		T25	11		T15	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T34	11		T134	6		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T49	1		T122	11		T135	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T9	11		T49	18		T50	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	5		T50	5		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T49	1		T84	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T24	19		T131	10		T221	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16802	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T11	9		T133	3		T19	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	1		T84	6		T205	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T136	28		T132	15		T233	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T47	9		T230	4		T171	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T50	2		T122	19		T160	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T15	10		T17	5		T145	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T48	16		T239	6		T18	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	6		T136	16		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	1		T35	2		T24	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	1		T146	12		T196	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T48	10		T133	13		T121	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T85	2		T120	10		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	7		T123	1		T124	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T10	20		T12	9		T13	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	11		T25	6		T15	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	6		T233	11		T206	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T122	19		T46	4		T202	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	4		T49	6		T50	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T47	11		T50	4		T82	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T49	6		T84	2		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T24	18		T131	7		T221	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T11	5		T133	2		T19	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T16	6		T197	2		T139	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T24	19		T82	1		T85	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T244	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T19	6		T295	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	2		T84	1		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	9		T133	3		T136	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T47	13		T193	1		T198	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T50	5		T134	1		T122	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	12		T232	1		T198	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T48	16		T82	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T136	3		T17	9		T131	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	1		T24	12		T146	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T9	20		T130	1		T146	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	14		T35	4		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T43	1		T120	1		T160	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T131	12		T211	9		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T40	13		T14	14		T24	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T11	5		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1810	1			T1	2		T2	31		T4	37
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	2		T49	1		T122	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T9	11		T49	19		T50	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T47	5		T50	5		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T16	2		T139	1		T141	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T24	18		T82	5		T85	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T244	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T19	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	1		T84	6		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	5		T133	2		T136	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T47	9		T230	4		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T50	2		T122	19		T160	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T15	10		T145	6		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	16		T239	6		T18	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	16		T17	9		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	1		T24	10		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	6		T146	12		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	10		T35	2		T133	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T43	1		T120	10		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T131	11		T211	9		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T14	15		T24	2		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	7		T25	6		T15	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1020	1			T10	20		T12	9		T13	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	11		T122	19		T196	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T9	4		T49	12		T50	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	11		T50	4		T143	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	2		T84	7		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T136	30		T134	1		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T47	10		T193	1		T198	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T50	3		T122	20		T160	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T15	13		T17	10		T232	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T48	17		T82	1		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	7		T136	17		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	2		T35	5		T24	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T43	2		T130	1		T146	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	11		T133	14		T121	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T40	1		T85	3		T120	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	1		T11	8		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T1	2		T2	2		T4	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	12		T25	12		T15	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T34	10		T134	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T49	1		T122	20		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T9	5		T49	7		T50	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T47	12		T50	5		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T49	7		T84	3		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T24	19		T131	8		T221	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16934	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T11	6		T133	3		T19	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	1		T126	12		T212	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T136	25		T126	14		T132	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T47	12		T198	10		T230	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T50	4		T122	8		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T15	9		T17	1		T145	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T48	15		T127	18		T239	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	19		T136	2		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T35	1		T24	11		T146	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T146	15		T196	2		T248	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T48	13		T133	2		T131	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T40	12		T85	9		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	4		T127	9		T148	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1441	1			T2	29		T4	34		T6	47
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T9	1		T25	5		T15	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T34	7		T134	5		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T122	10		T135	12		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T9	10		T49	17		T50	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T47	4		T50	4		T85	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T218	3		T303	2		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T24	18		T131	9		T221	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T37	1		T139	3		T205	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T11	8		T133	2		T162	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T16	6		T197	2		T139	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T24	19		T82	6		T85	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T244	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T19	7		T295	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	2		T84	7		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	6		T133	3		T136	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	10		T193	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T50	3		T134	1		T122	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T15	13		T232	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T48	17		T82	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T136	17		T17	15		T131	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	2		T24	11		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	7		T130	1		T146	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	11		T35	5		T133	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T43	2		T120	11		T160	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T131	12		T211	10		T147	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	1		T14	20		T24	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T11	8		T25	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1379	1			T1	2		T2	2		T4	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T9	12		T49	1		T122	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T9	5		T49	14		T50	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T47	12		T50	5		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T16	2		T304	4		T218	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T24	18		T85	5		T131	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T295	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	1		T37	1		T126	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	8		T133	2		T136	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T47	12		T198	2		T230	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T50	4		T122	8		T160	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T15	9		T198	8		T145	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T48	15		T127	18		T239	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	2		T17	3		T131	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T24	11		T146	3		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	19		T146	15		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T48	13		T35	1		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T160	11		T127	10		T196	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T131	11		T211	8		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T40	12		T14	9		T24	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	4		T25	5		T15	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T2	29		T4	34		T6	47
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T122	10		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T9	10		T49	17		T50	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T47	4		T50	4		T143	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47