Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22421

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3631

1

T5

1

T9

28

T11

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20251

1

T3

155

T5

41

T7

20

auto[1]

5801

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	258	1			T43	1		T134	1		T137	1
values[0]	49	1			T193	1		T259	13		T247	9
values[1]	852	1			T48	24		T50	14		T35	6
values[2]	690	1			T14	29		T82	6		T16	8
values[3]	776	1			T49	24		T34	17		T82	1
values[4]	721	1			T9	15		T47	16		T35	3
values[5]	2971	1			T1	2		T2	31		T4	37
values[6]	697	1			T47	22		T49	7		T40	13
values[7]	677	1			T11	2		T25	17		T136	38
values[8]	529	1			T11	14		T37	1		T134	6
values[9]	950	1			T5	1		T9	13		T11	12
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	858	1			T48	24		T50	14		T35	6
values[1]	687	1			T14	29		T82	6		T85	19
values[2]	831	1			T49	24		T34	17		T35	3
values[3]	3004	1			T1	2		T2	31		T4	37
values[4]	605	1			T9	26		T50	7		T43	3
values[5]	694	1			T47	22		T49	7		T40	13
values[6]	726	1			T11	2		T25	17		T120	7
values[7]	532	1			T9	13		T11	14		T15	30
values[8]	843	1			T5	1		T11	12		T48	32
values[9]	167	1			T132	30		T197	1		T252	4
minimum	17105	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T50	7		T24	19		T119	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T48	14		T35	4		T24	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T82	1		T222	1		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	14		T85	6		T121	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T49	18		T34	11		T35	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T133	3		T195	13		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1721	1			T1	2		T2	31		T4	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	11		T50	5		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	20		T43	2		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T50	5		T24	3		T15	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	13		T124	1		T212	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T47	13		T49	1		T136	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	1		T122	11		T147	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T25	11		T120	1		T131	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	17		T37	1		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T9	2		T11	9		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	5		T48	16		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T37	5		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T132	15		T197	1		T263	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T252	2		T162	11		T310	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16800	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T127	19		T223	1		T284	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T50	7		T24	18		T119	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T48	10		T35	2		T24	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T82	5		T222	1		T139	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T14	15		T85	13		T121	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	6		T34	6		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T133	13		T195	14		T145	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T10	20		T12	9		T13	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	4		T50	4		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	6		T43	1		T222	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T50	2		T24	2		T15	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T124	14		T206	2		T19	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T47	9		T49	6		T136	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	1		T122	19		T147	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T25	6		T120	6		T131	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T15	13		T262	10		T292	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T9	11		T11	5		T160	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	7		T48	16		T84	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	1		T119	11		T123	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T132	15		T263	11		T244	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T252	2		T162	11		T307	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T223	10		T284	3		T247	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T43	1		T197	1		T237	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T134	1		T137	1		T119	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T259	1		T89	10		T311	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T193	1		T247	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T50	7		T24	19		T119	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T48	14		T35	4		T24	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T82	1		T16	6		T46	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T14	14		T17	6		T195	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T49	18		T34	11		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T85	6		T133	3		T121	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T47	5		T35	3		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T9	11		T130	1		T131	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1729	1			T1	2		T2	31		T4	37
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T50	10		T24	3		T15	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T40	13		T124	1		T212	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	13		T49	1		T198	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	1		T122	11		T147	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	11		T136	18		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T37	1		T134	6		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	9		T120	1		T160	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T11	5		T48	16		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T5	1		T9	2		T37	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T237	7		T229	11		T234	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T119	11		T211	9		T162	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T259	12		T89	2		T311	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T247	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T50	7		T24	18		T119	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T48	10		T35	2		T24	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T82	5		T16	2		T46	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T14	15		T17	5		T195	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	6		T34	6		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T85	13		T133	13		T121	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T47	11		T14	1		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	4		T131	8		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	915	1			T9	6		T10	20		T12	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T50	6		T24	2		T15	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T124	14		T206	2		T285	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T47	9		T49	6		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	1		T122	19		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T25	6		T136	20		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T147	10		T262	10		T20	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T11	5		T120	6		T160	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	7		T48	16		T84	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	11		T37	1		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	8		T24	19		T119	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T48	11		T35	5		T24	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T82	6		T222	2		T138	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	20		T85	14		T121	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T49	7		T34	10		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T133	14		T195	15		T145	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1243	1			T1	2		T2	2		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T9	5		T50	5		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	7		T43	3		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T50	3		T24	3		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T40	1		T124	15		T212	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T47	10		T49	7		T136	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	2		T122	20		T147	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T25	12		T120	7		T131	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	16		T37	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	12		T11	6		T160	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T11	8		T48	17		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	1		T37	5		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T132	16		T197	1		T263	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T252	4		T162	12		T310	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16985	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T127	1		T223	11		T284	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	6		T24	18		T119	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T48	13		T35	1		T24	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T221	4		T210	2		T253	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	9		T85	5		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T49	17		T34	7		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	2		T195	12		T145	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T2	29		T4	34		T6	47
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T9	10		T50	4		T131	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	19		T135	12		T140	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T50	4		T24	2		T15	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T40	12		T212	7		T206	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T47	12		T136	17		T198	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T122	10		T147	19		T162	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	5		T131	11		T196	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	14		T134	5		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T9	1		T11	8		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	4		T48	15		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	1		T119	4		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T132	14		T263	10		T250	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T162	10		T310	12		T312	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T313	9		T314	2		T315	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T127	18		T247	4		T261	22

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T43	1		T197	1		T237	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T134	1		T137	1		T119	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T259	13		T89	9		T311	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T193	1		T247	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T50	8		T24	19		T119	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T48	11		T35	5		T24	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T82	6		T16	6		T46	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T14	20		T17	10		T195	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T49	7		T34	10		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T85	14		T133	14		T121	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	12		T35	2		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	5		T130	1		T131	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T1	2		T2	2		T4	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T50	8		T24	3		T15	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T40	1		T124	15		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T47	10		T49	7		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	2		T122	20		T147	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T25	12		T136	21		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T37	1		T134	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	6		T120	7		T160	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T11	8		T48	17		T84	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T9	12		T37	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T237	5		T229	10		T234	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T119	4		T211	8		T162	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T89	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T247	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T50	6		T24	18		T119	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T48	13		T35	1		T24	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T16	2		T46	1		T221	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T14	9		T17	1		T195	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T49	17		T34	7		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T85	5		T133	2		T195	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T47	4		T35	1		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T9	10		T131	11		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T2	29		T4	34		T6	47
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T50	8		T24	2		T15	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	12		T212	7		T206	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	12		T198	2		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T122	10		T147	10		T162	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T25	5		T136	17		T131	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T134	5		T126	14		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	8		T160	2		T127	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	4		T48	15		T15	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	1		T37	1		T266	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47