Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T47	12		T49	7		T14	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T48	17		T120	7		T122	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T24	3		T37	1		T133	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T48	11		T136	17		T119	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T9	7		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T47	10		T84	7		T131	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T1	2		T2	2		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T35	5		T43	1		T15	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	5		T24	11		T122	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T132	1		T46	5		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T50	8		T82	6		T124	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T128	1		T138	1		T216	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	8		T14	20		T16	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	2		T214	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	12		T11	8		T50	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	6		T35	2		T85	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T34	10		T43	2		T84	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	1		T43	1		T82	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T134	1		T217	1		T218	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T160	12		T130	1		T124	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	4		T49	17		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	15		T122	10		T131	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T24	2		T133	4		T119	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T48	13		T136	2		T119	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	19		T160	2		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	12		T131	9		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T2	29		T4	34		T6	47
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T35	1		T15	14		T119	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	10		T24	11		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T46	1		T220	12		T226	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	8		T227	7		T168	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T128	12		T216	12		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T14	9		T16	2		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T214	10		T198	8		T162	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T9	1		T11	4		T50	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	8		T35	1		T85	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T34	7		T15	9		T85	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	12		T136	8		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T134	5		T217	16		T218	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T160	11		T148	6		T228	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T215	12		T90	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T180	1		T225	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T47	12		T49	7		T14	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	17		T120	7		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T37	1		T133	3		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T48	11		T84	7		T136	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T9	7		T24	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T47	10		T119	14		T131	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T1	2		T2	2		T4	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T35	5		T43	1		T15	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	5		T24	11		T122	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T132	1		T46	5		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T49	7		T50	8		T211	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T128	1		T138	2		T216	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	1		T82	6		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	2		T85	3		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T50	8		T14	20		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	6		T136	21		T143	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	392	1			T9	12		T11	8		T34	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	380	1			T40	1		T35	2		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T215	7		T90	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T47	4		T49	17		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T48	15		T131	11		T198	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T133	2		T119	1		T146	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T48	13		T136	2		T122	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	19		T24	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T47	12		T119	13		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	29		T4	34		T6	47
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T35	1		T15	14		T119	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	10		T24	11		T122	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T46	1		T220	12		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T50	8		T211	8		T168	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T128	12		T216	12		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T16	2		T18	2		T147	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T85	9		T214	10		T204	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T50	6		T14	9		T126	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	8		T136	17		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T9	1		T11	4		T34	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T40	12		T35	1		T136	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47