Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22827

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3225

1

T5

1

T9

26

T11

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20059

1

T3

155

T5

41

T7

20

auto[1]

5993

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T169	14		-	-		-	-
values[0]	62	1			T230	16		T199	1		T231	14
values[1]	723	1			T50	14		T35	3		T14	29
values[2]	662	1			T11	2		T49	7		T15	22
values[3]	659	1			T24	37		T82	6		T137	1
values[4]	538	1			T49	25		T34	17		T43	1
values[5]	875	1			T35	6		T24	22		T25	17
values[6]	658	1			T47	16		T40	13		T137	1
values[7]	694	1			T5	1		T9	15		T48	24
values[8]	777	1			T9	26		T11	12		T47	22
values[9]	3508	1			T1	2		T2	31		T4	37
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	939	1			T49	7		T50	14		T35	3
values[1]	634	1			T11	2		T82	6		T15	22
values[2]	591	1			T49	1		T34	17		T43	1
values[3]	668	1			T49	24		T35	6		T25	17
values[4]	800	1			T24	22		T84	7		T136	38
values[5]	788	1			T5	1		T9	15		T47	16
values[6]	3027	1			T1	2		T2	31		T4	37
values[7]	754	1			T9	26		T11	26		T47	22
values[8]	730	1			T9	13		T14	3		T24	5
values[9]	209	1			T43	1		T119	26		T120	11
minimum	16912	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T49	1		T14	14		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T50	7		T35	3		T193	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T15	12		T195	13		T132	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T11	1		T82	1		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	11		T130	1		T131	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T49	1		T43	1		T24	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T49	18		T35	4		T25	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T143	14		T194	14		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T130	1		T232	1		T211	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T24	12		T84	1		T136	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T9	11		T47	5		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T126	13		T123	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1755	1			T1	2		T2	31		T4	37
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	30		T50	5		T85	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T11	9		T47	13		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	20		T11	5		T50	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	2		T14	2		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T127	19		T198	9		T128	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T119	2		T20	8		T226	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T43	1		T119	5		T120	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16774	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T49	6		T14	15		T84	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T50	7		T122	19		T196	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T15	10		T195	14		T132	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	1		T82	5		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	6		T131	15		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T24	18		T17	5		T196	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	6		T35	2		T25	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T143	13		T194	10		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T211	9		T124	14		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	10		T84	6		T136	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	4		T47	11		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T123	1		T124	14		T222	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T10	20		T12	9		T13	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T48	26		T50	4		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	5		T47	9		T43	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	6		T11	7		T50	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	11		T14	1		T24	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T46	1		T222	1		T233	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T119	8		T20	4		T234	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T119	11		T120	10		T205	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	1		T35	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T169	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T230	12		T199	1		T235	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T231	6		T215	12		T236	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	14		T84	1		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T50	7		T35	3		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T49	1		T15	12		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T37	5		T119	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T137	1		T131	10		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T24	19		T82	1		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T49	18		T34	11		T136	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T49	1		T43	1		T125	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T35	4		T25	11		T15	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T24	12		T84	1		T136	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T47	5		T40	13		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T126	13		T124	1		T128	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T9	11		T214	11		T198	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	1		T48	14		T85	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T47	13		T43	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	20		T11	5		T48	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1877	1			T1	2		T2	31		T4	37
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T43	1		T119	5		T120	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T169	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T230	4		T235	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T231	8		T215	7		T236	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	15		T84	2		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T50	7		T122	19		T196	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T49	6		T15	10		T195	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	1		T37	1		T119	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T131	7		T147	10		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T24	18		T82	5		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T49	6		T34	6		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T196	9		T194	10		T229	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T35	2		T25	6		T15	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T24	10		T84	6		T136	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	11		T160	11		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T124	14		T196	18		T222	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	4		T18	3		T147	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T48	10		T85	2		T136	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T47	9		T43	1		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	6		T11	7		T48	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T9	11		T10	20		T11	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T119	11		T120	10		T131	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T49	7		T14	20		T84	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T50	8		T35	2		T193	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	13		T195	15		T132	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	2		T82	6		T37	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	10		T130	1		T131	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T49	1		T43	1		T24	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T49	7		T35	5		T25	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T143	14		T194	11		T139	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T130	1		T232	1		T211	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T24	11		T84	7		T136	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	5		T47	12		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	1		T126	1		T123	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	2		T2	2		T4	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	28		T50	5		T85	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	6		T47	10		T43	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	7		T11	8		T50	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T9	12		T14	2		T24	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T127	1		T198	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T119	9		T20	9		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T43	1		T119	12		T120	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T14	9		T133	2		T127	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T50	6		T35	1		T122	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	9		T195	12		T132	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T37	1		T119	13		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	7		T131	20		T146	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T24	18		T17	1		T198	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T49	17		T35	1		T25	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T143	13		T194	13		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T211	10		T148	6		T238	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T24	11		T136	17		T128	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	10		T47	4		T40	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T126	12		T221	4		T183	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T2	29		T4	34		T6	47
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	28		T50	4		T85	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	8		T47	12		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	19		T11	4		T50	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	1		T14	1		T24	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T127	18		T198	8		T128	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T119	1		T20	3		T226	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T119	4		T205	19		T22	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T231	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T169	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T230	12		T199	1		T235	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T231	9		T215	12		T236	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T14	20		T84	3		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T50	8		T35	2		T193	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T49	7		T15	13		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	2		T37	5		T119	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T137	1		T131	8		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T24	19		T82	6		T17	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T49	7		T34	10		T136	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T49	1		T43	1		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T35	5		T25	12		T15	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T24	11		T84	7		T136	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T47	12		T40	1		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T126	1		T124	15		T128	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	5		T214	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T48	11		T85	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	10		T43	2		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	7		T11	8		T48	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T1	2		T2	2		T4	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T43	1		T119	12		T120	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T169	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T230	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T231	5		T215	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	9		T133	2		T127	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T50	6		T35	1		T122	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	9		T195	12		T132	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T37	1		T119	13		T122	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T131	9		T146	3		T147	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T24	18		T17	1		T198	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T49	17		T34	7		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T125	8		T196	8		T194	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T35	1		T25	5		T15	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T24	11		T136	17		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	4		T40	12		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T126	12		T128	11		T196	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	10		T214	10		T198	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	13		T85	9		T136	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T47	12		T16	2		T212	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	19		T11	4		T48	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T2	29		T4	34		T6	47
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T119	4		T131	11		T126	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47