Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22891

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3161

1

T5

1

T9

13

T11

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19655

1

T3

155

T5

40

T7

20

auto[1]

6397

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	16	1			T82	6		T221	10		-	-
values[0]	42	1			T139	7		T19	7		T22	1
values[1]	613	1			T11	14		T14	3		T84	7
values[2]	546	1			T47	22		T50	7		T134	1
values[3]	642	1			T48	32		T82	1		T130	1
values[4]	755	1			T11	2		T24	22		T15	22
values[5]	679	1			T9	26		T48	24		T35	6
values[6]	530	1			T11	12		T40	13		T43	2
values[7]	875	1			T5	1		T14	29		T25	17
values[8]	3108	1			T1	2		T2	31		T4	37
values[9]	1364	1			T9	15		T47	16		T49	31
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	713	1			T11	14		T47	22		T14	3
values[1]	661	1			T50	7		T82	1		T193	1
values[2]	563	1			T48	32		T130	1		T17	11
values[3]	792	1			T9	26		T11	2		T24	22
values[4]	695	1			T48	24		T35	6		T43	2
values[5]	648	1			T5	1		T11	12		T40	13
values[6]	3102	1			T1	2		T2	31		T4	37
values[7]	801	1			T49	25		T34	17		T37	1
values[8]	997	1			T9	15		T47	16		T50	23
values[9]	190	1			T49	7		T84	3		T197	1
minimum	16890	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T47	13		T14	2		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	9		T133	3		T136	27
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T193	1		T232	1		T198	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T50	5		T82	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T17	6		T128	10		T125	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	16		T130	1		T239	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T9	20		T15	12		T17	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T24	12		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T43	1		T136	3		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T48	14		T35	4		T133	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T40	13		T85	10		T167	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T11	5		T15	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1766	1			T1	2		T2	31		T4	37
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	2		T14	14		T25	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T49	18		T34	11		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T49	1		T37	1		T122	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T9	11		T50	7		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T47	5		T50	5		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T49	1		T84	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T221	5		T240	1		T172	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T241	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	9		T14	1		T84	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	5		T133	2		T136	28
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T230	4		T171	12		T242	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T50	2		T122	19		T160	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T17	5		T222	12		T205	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T48	16		T239	6		T18	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	6		T15	10		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T24	10		T147	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T43	1		T136	16		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	10		T35	2		T133	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T85	2		T167	11		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	7		T15	13		T123	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T10	20		T12	9		T13	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T9	11		T14	15		T25	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T49	6		T34	6		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	19		T46	4		T243	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	4		T50	7		T119	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T47	11		T50	4		T24	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T49	6		T84	2		T141	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T221	5		T228	9		T163	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T241	7		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T82	1		T221	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T139	4		T244	1		T245	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T19	6		T22	1		T246	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	2		T84	1		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	9		T133	3		T136	27
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T47	13		T198	3		T230	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T50	5		T134	1		T122	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	6		T232	1		T198	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	16		T82	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T15	12		T136	3		T17	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T24	12		T146	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	20		T130	1		T146	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T48	14		T35	4		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T40	13		T43	1		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	5		T131	12		T211	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T85	10		T167	10		T204	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T14	14		T25	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1779	1			T1	2		T2	31		T4	37
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T9	2		T49	1		T122	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	418	1			T9	11		T49	19		T50	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T47	5		T50	5		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T82	5		T221	5		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T139	3		T244	7		T245	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T19	1		T246	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T14	1		T84	6		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	5		T133	2		T136	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T47	9		T230	4		T171	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T50	2		T122	19		T160	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T17	5		T145	6		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T48	16		T239	6		T18	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T15	10		T136	16		T17	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	1		T24	10		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	6		T146	12		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	10		T35	2		T133	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T43	1		T24	2		T120	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T11	7		T131	11		T211	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T85	2		T167	11		T204	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T14	15		T25	6		T15	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T10	20		T12	9		T13	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	11		T122	19		T196	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T9	4		T49	12		T50	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T47	11		T50	4		T24	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T47	10		T14	2		T84	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	6		T133	3		T136	30
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T193	1		T232	1		T198	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T50	3		T82	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T17	10		T128	1		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T48	17		T130	1		T239	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T9	7		T15	13		T17	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	2		T24	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T43	2		T136	17		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T48	11		T35	5		T133	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T40	1		T85	3		T167	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T11	8		T15	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T1	2		T2	2		T4	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	12		T14	20		T25	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T49	7		T34	10		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T49	1		T37	1		T122	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T9	5		T50	8		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T47	12		T50	5		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T49	7		T84	3		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T221	6		T240	1		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T241	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	12		T14	1		T37	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	8		T133	2		T136	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T198	10		T230	4		T171	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T50	4		T122	8		T160	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T17	1		T128	9		T125	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T48	15		T239	6		T18	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T9	19		T15	9		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T24	11		T146	3		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T136	2		T146	15		T196	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T48	13		T35	1		T133	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	12		T85	9		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	4		T15	14		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1420	1			T2	29		T4	34		T6	47
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	1		T14	9		T25	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	17		T34	7		T134	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T122	10		T135	12		T46	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	10		T50	6		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T47	4		T50	4		T24	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T153	16		T218	3		T247	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T221	4		T172	5		T228	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T82	6		T221	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T139	4		T244	8		T245	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T19	7		T22	1		T246	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	2		T84	7		T37	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	6		T133	3		T136	30
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T47	10		T198	1		T230	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T50	3		T134	1		T122	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T17	10		T232	1		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T48	17		T82	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T15	13		T136	17		T17	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	2		T24	11		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	7		T130	1		T146	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T48	11		T35	5		T133	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T40	1		T43	2		T24	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	8		T131	12		T211	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T85	3		T167	12		T204	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T14	20		T25	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	2		T2	2		T4	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	12		T49	1		T122	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	453	1			T9	5		T49	14		T50	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T47	12		T50	5		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T221	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T139	3		T245	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T14	1		T37	1		T126	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	8		T133	2		T136	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	12		T198	2		T230	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T50	4		T122	8		T160	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T17	1		T198	8		T145	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T48	15		T127	18		T239	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	9		T136	2		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T24	11		T146	3		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	19		T146	15		T248	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T48	13		T35	1		T133	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	12		T24	2		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T11	4		T131	11		T211	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T85	9		T167	9		T204	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T14	9		T25	5		T15	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T2	29		T4	34		T6	47
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	1		T122	10		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T9	10		T49	17		T50	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T47	4		T50	4		T24	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47