Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20109

1

T3

155

T5

41

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

5943

1

T1

2

T2

31

T4

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20074

1

T3

155

T5

40

T7

20

auto[1]

5978

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T163	11		T249	1		T250	14
values[0]	30	1			T46	6		T251	17		T209	7
values[1]	573	1			T43	2		T24	5		T134	6
values[2]	702	1			T34	17		T43	1		T82	7
values[3]	772	1			T49	7		T43	1		T37	7
values[4]	673	1			T5	1		T9	28		T40	13
values[5]	797	1			T9	26		T49	24		T50	9
values[6]	701	1			T11	14		T48	32		T14	3
values[7]	653	1			T11	14		T47	16		T48	24
values[8]	740	1			T50	7		T14	29		T24	22
values[9]	3503	1			T1	2		T2	31		T4	37
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	838	1			T43	2		T24	5		T136	38
values[1]	2941	1			T1	2		T2	31		T4	37
values[2]	789	1			T5	1		T49	7		T43	1
values[3]	734	1			T9	28		T49	24		T40	13
values[4]	729	1			T9	26		T50	9		T15	22
values[5]	742	1			T11	14		T47	16		T48	32
values[6]	587	1			T11	14		T49	1		T50	14
values[7]	726	1			T48	24		T50	7		T160	23
values[8]	896	1			T47	22		T35	3		T84	3
values[9]	188	1			T35	6		T128	13		T252	4
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	18		T119	14		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T43	1		T24	3		T134	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T43	1		T82	1		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1704	1			T1	2		T2	31		T4	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T49	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T43	1		T85	10		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	13		T49	18		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T40	13		T24	19		T25	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	5		T137	1		T119	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	20		T15	12		T193	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T47	5		T48	16		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T11	6		T15	17		T136	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	9		T49	1		T50	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T160	3		T16	6		T127	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	14		T50	5		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T248	6		T222	1		T203	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T47	13		T84	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T35	3		T85	6		T119	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T35	4		T252	2		T183	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T128	13		T253	13		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T136	20		T119	13		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T43	1		T24	2		T17	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T82	5		T195	14		T124	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	939	1			T10	20		T12	9		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T49	6		T37	1		T220	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T85	2		T133	2		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T9	15		T49	6		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T24	18		T25	6		T17	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T50	4		T119	11		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	6		T15	10		T120	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	11		T48	16		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	8		T15	13		T136	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	5		T50	7		T14	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T160	3		T16	2		T243	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	10		T50	2		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T222	1		T203	12		T220	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T47	9		T84	2		T195	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T85	13		T119	8		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T35	2		T252	2		T183	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T253	5		T254	10		T246	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T163	1		T249	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T250	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T209	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T46	2		T251	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T119	14		T180	1		T198	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	1		T24	3		T134	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T43	1		T82	2		T136	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T34	11		T127	11		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	1		T37	6		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T43	1		T133	3		T126	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T9	13		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	13		T25	11		T85	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T49	18		T50	5		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T9	20		T24	19		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	16		T14	2		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	6		T15	29		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	9		T47	5		T48	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	9		T127	19		T147	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T50	5		T14	14		T24	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T160	3		T16	6		T248	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T47	13		T35	4		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1853	1			T1	2		T2	31		T4	37
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T163	10		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T250	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T209	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T46	4		T251	16		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T119	13		T46	1		T222	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T43	1		T24	2		T17	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T82	5		T136	20		T195	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	6		T124	14		T202	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T49	6		T37	1		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T133	2		T227	2		T210	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	15		T143	13		T205	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T25	6		T85	2		T167	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	6		T50	4		T84	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	6		T24	18		T120	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	16		T14	1		T120	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	8		T15	23		T120	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	5		T47	11		T48	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T136	8		T147	9		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	2		T14	15		T24	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T160	3		T16	2		T222	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T47	9		T35	2		T84	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1052	1			T10	20		T12	9		T13	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T136	21		T119	14		T180	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T43	2		T24	3		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T43	1		T82	6		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1284	1			T1	2		T2	2		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T49	7		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T43	1		T85	3		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	17		T49	7		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T40	1		T24	19		T25	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T50	5		T137	1		T119	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	7		T15	13		T193	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T47	12		T48	17		T14	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	10		T15	16		T136	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	6		T49	1		T50	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T160	4		T16	6		T127	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T48	11		T50	3		T160	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T248	1		T222	2		T203	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T47	10		T84	3		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T35	2		T85	14		T119	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T35	5		T252	4		T183	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T128	1		T253	6		T254	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T136	17		T119	13		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T24	2		T134	5		T17	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T198	14		T195	12		T255	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1359	1			T2	29		T4	34		T6	47
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	1		T198	2		T125	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T85	9		T133	2		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	11		T49	17		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T40	12		T24	18		T25	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	4		T119	4		T211	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	19		T15	9		T122	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T47	4		T48	15		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	4		T15	14		T136	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	8		T50	6		T14	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T160	2		T16	2		T127	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T48	13		T50	4		T160	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T248	5		T203	12		T220	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T47	12		T195	11		T128	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T35	1		T85	5		T119	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T35	1		T183	14		T245	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T128	12		T253	12		T256	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T163	11		T249	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T250	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T209	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T46	5		T251	17		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T119	14		T180	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T43	2		T24	3		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T43	1		T82	7		T136	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	10		T127	1		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T49	7		T37	6		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T43	1		T133	3		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	1		T9	17		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	1		T25	12		T85	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T49	7		T50	5		T84	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T9	7		T24	19		T120	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T48	17		T14	2		T120	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	10		T15	29		T193	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	6		T47	12		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T136	9		T127	1		T147	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T50	3		T14	20		T24	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T160	4		T16	6		T248	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T47	10		T35	5		T84	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1422	1			T1	2		T2	2		T4	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T46	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T119	13		T198	14		T46	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T24	2		T134	5		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T136	17		T195	12		T255	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T34	7		T127	10		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	1		T220	12		T200	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	2		T126	14		T135	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	11		T143	13		T198	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T40	12		T25	5		T85	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T49	17		T50	4		T133	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	19		T24	18		T122	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T48	15		T14	1		T239	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	4		T15	23		T122	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	8		T47	4		T48	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T136	8		T127	18		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	4		T14	9		T24	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T160	2		T16	2		T248	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T47	12		T35	1		T198	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1483	1			T2	29		T4	34		T6	47

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47