Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22505

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3547

1

T5

1

T9

54

T11

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20303

1

T3

155

T5

41

T7

20

auto[1]

5749

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T257	1		T209	5		T258	1
values[0]	35	1			T193	1		T259	13		T247	9
values[1]	888	1			T48	24		T50	14		T35	6
values[2]	703	1			T14	29		T82	6		T85	19
values[3]	772	1			T49	24		T34	17		T82	1
values[4]	724	1			T9	15		T47	16		T35	3
values[5]	2917	1			T1	2		T2	31		T4	37
values[6]	751	1			T47	22		T49	7		T131	23
values[7]	664	1			T11	2		T40	13		T25	17
values[8]	490	1			T37	1		T134	6		T137	1
values[9]	1219	1			T5	1		T9	13		T11	26
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	935	1			T48	24		T50	14		T35	6
values[1]	752	1			T14	29		T82	6		T121	10
values[2]	853	1			T49	24		T34	17		T35	3
values[3]	3028	1			T1	2		T2	31		T4	37
values[4]	594	1			T9	26		T50	7		T43	3
values[5]	723	1			T47	22		T49	7		T40	13
values[6]	701	1			T11	2		T25	17		T120	7
values[7]	551	1			T9	13		T11	14		T15	30
values[8]	760	1			T5	1		T11	12		T48	32
values[9]	235	1			T198	9		T211	18		T132	30
minimum	16920	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T50	7		T24	19		T133	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T48	14		T35	4		T24	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T82	1		T16	6		T128	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T14	14		T121	1		T122	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T49	18		T34	11		T35	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T133	3		T195	13		T211	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1713	1			T1	2		T2	31		T4	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	11		T50	5		T131	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T43	1		T127	11		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	20		T50	5		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T47	13		T49	1		T40	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T136	18		T120	1		T198	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	1		T122	11		T147	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T25	11		T120	1		T131	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T15	17		T37	1		T134	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	2		T11	9		T160	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T48	16		T43	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T5	1		T11	5		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T132	15		T135	13		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T198	9		T211	9		T260	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16760	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T261	23		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T50	7		T24	18		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T48	10		T35	2		T24	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T82	5		T16	2		T139	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T14	15		T121	9		T122	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	6		T34	6		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T133	13		T195	14		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	927	1			T10	20		T12	9		T13	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	4		T50	4		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T43	1		T222	1		T149	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T9	6		T50	2		T24	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T47	9		T49	6		T124	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T136	20		T120	6		T18	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	1		T122	19		T147	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T25	6		T120	6		T131	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	13		T148	2		T262	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T9	11		T11	5		T160	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T48	16		T84	6		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	7		T123	1		T216	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T132	15		T237	7		T263	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T211	9		T260	8		T252	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T261	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T257	1		T209	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T259	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T193	1		T247	5		T89	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T50	7		T24	19		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T48	14		T35	4		T24	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T82	1		T85	6		T16	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T14	14		T17	6		T195	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T49	18		T34	11		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T133	3		T121	1		T195	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	5		T35	3		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T9	11		T131	12		T211	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1704	1			T1	2		T2	31		T4	37
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	20		T50	10		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T47	13		T49	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T131	12		T18	6		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	1		T40	13		T122	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T25	11		T136	18		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	1		T134	6		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T120	1		T160	3		T127	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T48	16		T43	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	1		T9	2		T11	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T209	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T259	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T247	4		T89	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T50	7		T24	18		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T48	10		T35	2		T24	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T82	5		T85	13		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T14	15		T17	5		T195	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	6		T34	6		T17	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T133	13		T121	9		T195	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T47	11		T14	1		T84	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	4		T131	8		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T10	20		T12	9		T13	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	6		T50	6		T24	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T47	9		T49	6		T124	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T131	11		T18	3		T265	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T11	1		T122	19		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T25	6		T136	20		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T147	10		T262	10		T20	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T120	6		T160	3		T233	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T48	16		T84	6		T15	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	11		T11	12		T123	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T50	8		T24	19		T133	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T48	11		T35	5		T24	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T82	6		T16	6		T128	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T14	20		T121	10		T122	20
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T49	7		T34	10		T35	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T133	14		T195	15		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T1	2		T2	2		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	5		T50	5		T131	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T43	2		T127	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	7		T50	3		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	10		T49	7		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T136	21		T120	7		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	2		T122	20		T147	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T25	12		T120	7		T131	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	16		T37	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T9	12		T11	6		T160	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T48	17		T43	1		T84	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T11	8		T134	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T132	16		T135	1		T197	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T198	1		T211	10		T260	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16884	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T261	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	6		T24	18		T133	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T48	13		T35	1		T24	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T16	2		T128	12		T221	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	9		T122	8		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	17		T34	7		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T133	2		T195	12		T211	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1366	1			T2	29		T4	34		T6	47
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	10		T50	4		T131	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T127	10		T135	12		T140	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	19		T50	4		T24	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T47	12		T40	12		T212	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	17		T198	2		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T122	10		T147	19		T162	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	5		T131	11		T196	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T15	14		T134	5		T126	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T9	1		T11	8		T160	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T48	15		T37	1		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T11	4		T216	8		T217	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T132	14		T135	12		T237	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T198	8		T211	8		T162	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T261	22		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T258	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T257	1		T209	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T259	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T193	1		T247	5		T89	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T50	8		T24	19		T133	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T48	11		T35	5		T24	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T82	6		T85	14		T16	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	20		T17	10		T195	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T49	7		T34	10		T82	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T133	14		T121	10		T195	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T47	12		T35	2		T14	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	5		T131	9		T211	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1248	1			T1	2		T2	2		T4	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	7		T50	8		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T47	10		T49	7		T124	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T131	12		T18	7		T264	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	2		T40	1		T122	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T25	12		T136	21		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T37	1		T134	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T120	7		T160	4		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	445	1			T48	17		T43	1		T84	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T5	1		T9	12		T11	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T247	4		T89	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T50	6		T24	18		T133	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T48	13		T35	1		T24	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T85	5		T16	2		T194	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T14	9		T17	1		T195	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T49	17		T34	7		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T133	2		T195	12		T145	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T47	4		T35	1		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	10		T131	11		T211	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T2	29		T4	34		T6	47
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	19		T50	8		T24	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T47	12		T212	7		T206	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T131	11		T18	2		T265	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T40	12		T122	10		T147	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T25	5		T136	17		T196	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T134	5		T126	14		T147	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T160	2		T127	9		T128	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T48	15		T15	14		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	1		T11	12		T266	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47