Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22651

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3401

1

T11

16

T47

22

T48

56

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19878

1

T3

155

T5

41

T7

20

auto[1]

6174

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	211	1			T84	3		T134	1		T123	2
values[0]	2	1			T180	1		T267	1		-	-
values[1]	525	1			T47	16		T48	32		T14	3
values[2]	751	1			T48	24		T49	24		T37	1
values[3]	794	1			T5	1		T9	26		T47	22
values[4]	2988	1			T1	2		T2	31		T4	37
values[5]	585	1			T9	15		T24	22		T122	28
values[6]	721	1			T49	7		T50	16		T211	18
values[7]	442	1			T11	2		T49	1		T82	6
values[8]	1016	1			T11	14		T50	14		T14	29
values[9]	1135	1			T9	13		T11	12		T34	17
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	600	1			T47	16		T49	24		T14	3
values[1]	642	1			T5	1		T48	24		T24	5
values[2]	752	1			T9	26		T47	22		T84	7
values[3]	2962	1			T1	2		T2	31		T4	37
values[4]	659	1			T9	15		T24	22		T122	28
values[5]	726	1			T49	7		T50	16		T82	6
values[6]	503	1			T11	2		T49	1		T16	8
values[7]	1025	1			T9	13		T11	26		T50	14
values[8]	891	1			T34	17		T40	13		T35	3
values[9]	238	1			T134	6		T160	23		T130	1
minimum	17054	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T47	5		T49	18		T14	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T120	1		T122	11		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T5	1		T24	3		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T48	14		T136	3		T119	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	20		T193	1		T160	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T47	13		T84	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T1	2		T2	31		T4	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T35	4		T43	1		T15	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	11		T24	12		T122	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T132	1		T46	2		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T49	1		T50	10		T82	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T128	13		T138	1		T216	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T49	1		T16	6		T18	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	1		T214	11		T198	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T9	2		T11	5		T50	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T11	9		T85	10		T136	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T34	11		T43	1		T84	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T40	13		T35	3		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T134	6		T217	17		T223	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T160	12		T130	1		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16813	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T48	16		T131	12		T198	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T47	11		T49	6		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T120	6		T122	19		T195	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T24	2		T133	2		T119	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T48	10		T136	16		T119	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	6		T160	3		T219	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	9		T84	6		T131	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	892	1			T10	20		T12	9		T13	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T35	2		T15	13		T119	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	4		T24	10		T122	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T46	4		T139	1		T220	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T49	6		T50	6		T82	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T216	11		T140	8		T221	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T16	2		T18	3		T147	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T11	1		T222	1		T205	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T9	11		T11	7		T50	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	5		T85	2		T136	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T34	6		T43	1		T84	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T136	8		T124	10		T196	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T223	10		T268	5		T224	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T160	11		T124	14		T148	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T48	16		T131	11		T216	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T84	1		T134	1		T123	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T124	2		T135	13		T259	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T267	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	5		T14	2		T25	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	16		T120	1		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T49	18		T37	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T48	14		T136	3		T122	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T9	20		T24	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T47	13		T84	1		T119	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T1	2		T2	31		T4	37
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	4		T43	1		T15	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	11		T24	12		T122	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T132	1		T46	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	1		T50	10		T211	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T128	13		T138	2		T216	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T49	1		T82	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T11	1		T214	11		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T50	7		T14	14		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T11	9		T85	10		T136	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T9	2		T11	5		T34	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T40	13		T35	3		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T84	2		T123	1		T222	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T124	24		T259	12		T174	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	11		T14	1		T25	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T48	16		T120	6		T131	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	6		T133	2		T119	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	10		T136	16		T122	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	6		T24	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T47	9		T84	6		T119	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T10	20		T12	9		T13	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	2		T15	13		T119	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	4		T24	10		T122	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T46	4		T139	1		T220	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T49	6		T50	6		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T216	11		T140	8		T200	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T82	5		T16	2		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T11	1		T222	1		T205	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T50	7		T14	15		T120	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	5		T85	2		T136	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	11		T11	7		T34	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T136	8		T160	11		T196	22
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T47	12		T49	7		T14	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T120	7		T122	20		T180	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T24	3		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T48	11		T136	17		T119	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	7		T193	1		T160	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T47	10		T84	7		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T1	2		T2	2		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	5		T43	1		T15	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	5		T24	11		T122	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T132	1		T46	5		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T49	7		T50	8		T82	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T128	1		T138	1		T216	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T49	1		T16	6		T18	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	2		T214	1		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T9	12		T11	8		T50	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	6		T85	3		T136	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T34	10		T43	2		T84	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T40	1		T35	2		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T134	1		T217	1		T223	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T160	12		T130	1		T124	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16922	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T48	17		T131	12		T198	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	4		T49	17		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T122	10		T127	9		T195	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T24	2		T133	2		T119	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T48	13		T136	2		T119	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	19		T160	2		T127	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	12		T131	9		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T2	29		T4	34		T6	47
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	1		T15	14		T119	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	10		T24	11		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T46	1		T220	12		T226	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T50	8		T227	7		T168	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T128	12		T216	12		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T16	2		T18	2		T147	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T214	10		T198	8		T162	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T9	1		T11	4		T50	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T11	8		T85	9		T136	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T34	7		T15	9		T85	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T40	12		T35	1		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T134	5		T217	16		T269	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T160	11		T148	6		T228	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T25	5		T146	3		T192	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T48	15		T131	11		T198	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T84	3		T134	1		T123	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T124	26		T135	1		T259	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T267	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T180	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	12		T14	2		T25	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T48	17		T120	7		T131	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T49	7		T37	1		T133	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T48	11		T136	17		T122	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	1		T9	7		T24	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T47	10		T84	7		T119	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T1	2		T2	2		T4	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T35	5		T43	1		T15	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T9	5		T24	11		T122	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T132	1		T46	5		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T49	7		T50	8		T211	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T128	1		T138	2		T216	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T49	1		T82	6		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	2		T214	1		T197	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T50	8		T14	20		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T11	6		T85	3		T136	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T9	12		T11	8		T34	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T40	1		T35	2		T43	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T222	13		T237	2		T217	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T135	12		T174	9		T270	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T47	4		T14	1		T25	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T48	15		T131	11		T127	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T49	17		T133	2		T119	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T48	13		T136	2		T122	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	19		T24	2		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T47	12		T119	13		T131	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	29		T4	34		T6	47
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T35	1		T15	14		T119	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	10		T24	11		T122	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T46	1		T220	12		T229	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T50	8		T211	8		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T128	12		T216	12		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T16	2		T18	2		T147	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T214	10		T221	11		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T50	6		T14	9		T126	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	8		T85	9		T136	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T9	1		T11	4		T34	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T40	12		T35	1		T136	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47