Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20043

1

T3

155

T5

41

T7

20

auto[ADC_CTRL_FILTER_COND_OUT]

6009

1

T1

2

T2

31

T4

37

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20050

1

T3

155

T5

40

T7

20

auto[1]

6002

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	250	1			T119	10		T195	25		T196	40
values[0]	45	1			T46	6		T251	17		T234	22
values[1]	548	1			T43	2		T24	5		T134	6
values[2]	690	1			T34	17		T43	1		T82	6
values[3]	835	1			T49	7		T43	1		T82	1
values[4]	682	1			T5	1		T9	28		T25	17
values[5]	682	1			T9	26		T49	24		T50	9
values[6]	779	1			T11	14		T48	32		T14	3
values[7]	698	1			T11	14		T47	16		T48	24
values[8]	632	1			T50	7		T14	29		T136	19
values[9]	3329	1			T1	2		T2	31		T4	37
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	618	1			T43	2		T136	38		T134	6
values[1]	2976	1			T1	2		T2	31		T4	37
values[2]	774	1			T5	1		T49	7		T43	1
values[3]	708	1			T9	28		T49	24		T40	13
values[4]	756	1			T9	26		T50	9		T24	37
values[5]	752	1			T11	14		T47	16		T48	32
values[6]	696	1			T11	14		T48	24		T49	1
values[7]	572	1			T50	7		T160	23		T214	11
values[8]	926	1			T47	22		T35	3		T84	3
values[9]	193	1			T35	6		T195	25		T128	13
minimum	17081	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T136	18		T180	1		T198	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T43	1		T134	6		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T43	1		T82	1		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1764	1			T1	2		T2	31		T4	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T49	1		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T43	1		T85	10		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	13		T49	18		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T40	13		T25	11		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T50	5		T137	1		T119	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	20		T24	19		T15	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	5		T48	16		T84	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	6		T14	2		T15	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	9		T48	14		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T16	6		T127	19		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T50	5		T160	12		T214	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T248	6		T222	1		T203	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T47	13		T84	1		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T35	3		T85	6		T119	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T35	4		T195	12		T252	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T128	13		T254	1		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16818	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T24	3		T17	3		T168	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T136	20		T222	1		T205	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T43	1		T18	3		T46	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T82	5		T195	14		T124	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	962	1			T10	20		T12	9		T13	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T49	6		T37	1		T220	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T85	2		T133	2		T167	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	15		T49	6		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T25	6		T17	5		T131	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T50	4		T119	11		T120	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	6		T24	18		T15	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T47	11		T48	16		T84	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	8		T14	1		T15	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	5		T48	10		T50	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T16	2		T243	2		T260	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T50	2		T160	11		T204	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T222	1		T203	12		T220	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T47	9		T84	2		T196	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T85	13		T119	8		T121	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T35	2		T195	13		T252	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T254	10		T246	8		T256	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T34	1		T35	2		T14	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T24	2		T17	4		T168	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T195	12		T196	3		T118	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T119	2		T196	15		T253	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T46	2		T251	1		T234	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T119	14		T180	1		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T43	1		T24	3		T134	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T43	1		T82	1		T136	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T34	11		T127	11		T124	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T49	1		T82	1		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T43	1		T85	10		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T9	13		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T25	11		T122	9		T17	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T49	18		T50	5		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	20		T40	13		T24	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	16		T84	1		T133	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T11	6		T14	2		T15	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	9		T47	5		T48	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T136	9		T127	19		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	5		T14	14		T136	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T16	6		T248	6		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T47	13		T35	4		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1812	1			T1	2		T2	31		T4	37
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T195	13		T196	4		T237	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T119	8		T196	18		T253	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T46	4		T251	16		T234	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T119	13		T46	1		T222	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	1		T24	2		T17	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T82	5		T136	20		T195	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T34	6		T124	14		T202	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T49	6		T37	1		T220	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T85	2		T133	2		T167	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	15		T143	13		T205	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T25	6		T122	19		T17	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T49	6		T50	4		T119	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	6		T24	18		T131	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	16		T84	6		T133	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	8		T14	1		T15	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	5		T47	11		T48	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T136	8		T243	2		T20	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T50	2		T14	15		T136	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T16	2		T222	1		T203	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T47	9		T35	2		T84	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1021	1			T10	20		T12	9		T13	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T136	21		T180	1		T198	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T43	2		T134	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T43	1		T82	6		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1311	1			T1	2		T2	2		T4	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T5	1		T49	7		T82	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T43	1		T85	3		T133	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	17		T49	7		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T40	1		T25	12		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T50	5		T137	1		T119	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	7		T24	19		T15	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T47	12		T48	17		T84	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	10		T14	2		T15	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T11	6		T48	11		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T16	6		T127	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	3		T160	12		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T248	1		T222	2		T203	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T47	10		T84	3		T134	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T35	2		T85	14		T119	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T35	5		T195	14		T252	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T128	1		T254	11		T271	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16941	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T24	3		T17	5		T168	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T136	17		T198	14		T205	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T134	5		T127	10		T18	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T195	12		T248	2		T255	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1415	1			T2	29		T4	34		T6	47
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	1		T198	2		T125	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T85	9		T133	2		T167	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	11		T49	17		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T40	12		T25	5		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T50	4		T119	4		T132	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T9	19		T24	18		T15	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T47	4		T48	15		T133	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	4		T14	1		T15	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	8		T48	13		T50	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	2		T127	18		T162	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T50	4		T160	11		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T248	5		T203	12		T220	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T47	12		T128	9		T196	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	1		T85	5		T119	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T35	1		T195	11		T245	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T128	12		T256	12		T272	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T119	13		T46	1		T230	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T24	2		T17	2		T168	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T195	14		T196	5		T118	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T119	9		T196	19		T253	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T46	5		T251	17		T234	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T119	14		T180	1		T46	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	2		T24	3		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T43	1		T82	6		T136	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T34	10		T127	1		T124	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T49	7		T82	1		T37	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T43	1		T85	3		T133	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T9	17		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T25	12		T122	20		T17	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T49	7		T50	5		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	7		T40	1		T24	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	17		T84	7		T133	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T11	10		T14	2		T15	29
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	6		T47	12		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T136	9		T127	1		T140	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T50	3		T14	20		T136	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T16	6		T248	1		T222	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T47	10		T35	5		T84	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1381	1			T1	2		T2	2		T4	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T195	11		T196	2		T118	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T119	1		T196	14		T253	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T46	1		T234	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T119	13		T46	1		T205	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T24	2		T134	5		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T136	17		T198	14		T195	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T34	7		T127	10		T128	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T37	1		T220	12		T273	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T85	9		T133	2		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	11		T143	13		T198	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T25	5		T122	8		T17	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T49	17		T50	4		T119	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	19		T40	12		T24	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T48	15		T133	2		T239	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	4		T14	1		T15	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	8		T47	4		T48	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T136	8		T127	18		T20	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T50	4		T14	9		T136	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	2		T248	5		T203	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	12		T35	1		T204	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1452	1			T2	29		T4	34		T6	47

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47