Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26052

1

T1

2

T2

31

T3

155

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22515

1

T1

2

T2

31

T3

155

auto[ADC_CTRL_FILTER_COND_OUT]

3537

1

T5

1

T9

39

T11

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19847

1

T3

155

T5

40

T7

20

auto[1]

6205

1

T1

2

T2

31

T4

37

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21988

1

T1

2

T2

31

T3

155

auto[1]

4064

1

T9

21

T10

20

T11

13

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	45	1			T213	12		T192	6		T274	8
values[0]	16	1			T222	2		T275	1		T276	1
values[1]	634	1			T48	24		T49	24		T50	9
values[2]	779	1			T9	15		T35	6		T43	1
values[3]	571	1			T5	1		T48	32		T50	14
values[4]	691	1			T11	2		T82	1		T136	55
values[5]	3174	1			T1	2		T2	31		T4	37
values[6]	577	1			T49	1		T35	3		T24	22
values[7]	582	1			T9	26		T43	1		T82	6
values[8]	956	1			T9	13		T49	7		T84	3
values[9]	1145	1			T11	26		T47	16		T50	7
minimum	16882	1			T3	155		T5	40		T7	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	883	1			T48	24		T49	24		T50	9
values[1]	658	1			T5	1		T50	14		T40	13
values[2]	556	1			T9	15		T11	2		T48	32
values[3]	3106	1			T1	2		T2	31		T4	37
values[4]	704	1			T47	22		T34	17		T24	5
values[5]	688	1			T49	1		T35	3		T24	22
values[6]	606	1			T9	39		T49	7		T43	1
values[7]	819	1			T11	14		T133	21		T193	1
values[8]	985	1			T11	12		T50	7		T84	3
values[9]	154	1			T47	16		T136	19		T213	12
minimum	16893	1			T3	155		T5	40		T7	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

4127

1

T2

29

T4

34

T6

47

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T49	18		T50	5		T35	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	14		T24	19		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T131	12		T219	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T50	7		T40	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	11		T15	12		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T48	16		T266	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1764	1			T1	2		T2	31		T4	37
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	14		T82	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	13		T24	3		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	11		T136	18		T119	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T82	1		T160	3		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T49	1		T35	3		T24	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T49	1		T37	1		T17	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	22		T43	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	9		T133	3		T198	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T133	3		T193	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T126	13		T127	10		T198	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T11	5		T50	5		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T47	5		T213	12		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T136	3		T140	1		T200	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T49	6		T50	4		T35	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T48	10		T24	18		T121	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T131	11		T219	11		T243	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T50	7		T37	1		T131	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T9	4		T15	10		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	1		T48	16		T146	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T10	20		T12	9		T13	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T14	15		T17	4		T239	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T47	9		T24	2		T122	38
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T34	6		T136	20		T119	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T82	5		T160	3		T233	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T24	10		T85	13		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T49	6		T17	5		T46	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	17		T16	2		T221	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	5		T133	2		T147	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T133	13		T120	6		T124	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T132	15		T196	4		T222	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	7		T50	2		T84	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T47	11		T274	7		T278	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T136	16		T200	8		T279	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T213	12		T274	1		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T192	4		T271	1		T281	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T222	1		T275	1		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T277	11		T282	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T49	18		T50	5		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T48	14		T24	19		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	11		T35	4		T25	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T43	1		T134	6		T167	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	2		T160	12		T131	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T48	16		T50	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T136	9		T119	14		T127	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	1		T82	1		T136	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1738	1			T1	2		T2	31		T4	37
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T34	11		T14	14		T119	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T134	1		T122	11		T160	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T49	1		T35	3		T24	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T82	1		T37	1		T17	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	20		T43	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T49	1		T133	3		T126	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	2		T84	1		T133	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T11	9		T47	5		T127	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T11	5		T50	5		T85	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16759	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T274	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T192	2		T235	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T222	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T49	6		T50	4		T43	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T48	10		T24	18		T121	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	4		T35	2		T25	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T167	11		T131	8		T195	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T160	11		T131	11		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T48	16		T50	7		T37	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T136	8		T119	13		T216	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	1		T136	20		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	943	1			T10	20		T12	9		T13	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T34	6		T14	15		T119	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T122	19		T160	3		T233	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T24	10		T85	13		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T82	5		T17	5		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	6		T171	12		T162	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T49	6		T133	2		T216	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	11		T84	2		T133	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	5		T47	11		T132	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	7		T50	2		T85	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	1		T35	2		T14	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T49	7		T50	5		T35	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T48	11		T24	19		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T131	12		T219	12		T243	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T50	8		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	5		T15	13		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T11	2		T48	17		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1355	1			T1	2		T2	2		T4	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T14	20		T82	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T47	10		T24	3		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T34	10		T136	21		T119	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T82	6		T160	4		T233	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T49	1		T35	2		T24	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	7		T37	1		T17	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	19		T43	1		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T11	6		T133	3		T198	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T133	14		T193	1		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T126	1		T127	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	8		T50	3		T84	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T47	12		T213	1		T274	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T136	17		T140	1		T200	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T49	17		T50	4		T35	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T48	13		T24	18		T167	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T131	11		T226	7		T217	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T50	6		T40	12		T37	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T9	10		T15	9		T160	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T48	15		T266	4		T146	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1402	1			T2	29		T4	34		T6	47
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	9		T17	2		T239	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T47	12		T24	2		T122	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T34	7		T136	17		T119	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T160	2		T226	12		T283	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T35	1		T24	11		T85	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T17	1		T128	9		T135	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	20		T16	2		T221	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	8		T133	2		T198	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T133	2		T135	12		T147	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T126	12		T127	9		T198	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	4		T50	4		T85	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T47	4		T213	11		T278	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T136	2		T200	4		T284	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T277	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T213	1		T274	8		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T192	4		T271	1		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T222	2		T275	1		T276	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T277	1		T282	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T49	7		T50	5		T43	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	11		T24	19		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T9	5		T35	5		T25	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T43	1		T134	1		T167	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	2		T160	12		T131	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	1		T48	17		T50	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T136	9		T119	14		T127	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	2		T82	1		T136	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1292	1			T1	2		T2	2		T4	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T34	10		T14	20		T119	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T134	1		T122	20		T160	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T49	1		T35	2		T24	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T82	6		T37	1		T17	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	7		T43	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T49	7		T133	3		T126	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T9	12		T84	3		T133	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T11	6		T47	12		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T11	8		T50	3		T85	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16882	1			T3	155		T5	40		T7	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T213	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T192	2		T281	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T277	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T49	17		T50	4		T119	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T48	13		T24	18		T196	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	10		T35	1		T25	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T134	5		T167	9		T131	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T160	11		T131	11		T172	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T48	15		T50	6		T40	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T136	8		T119	13		T127	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	17		T211	10		T255	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1389	1			T2	29		T4	34		T6	47
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T34	7		T14	9		T119	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T122	10		T160	2		T226	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T35	1		T24	11		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T17	1		T135	12		T46	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T9	19		T171	11		T162	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T133	2		T126	12		T198	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T133	2		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	8		T47	4		T127	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	4		T50	4		T85	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21925

1

T1

2

T2

2

T3

155

auto[1]

auto[0]

4127

1

T2

29

T4

34

T6

47