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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.69 99.07 96.67 100.00 100.00 98.83 98.33 90.97


Total test records in report: 919
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T789 /workspace/coverage/default/47.adc_ctrl_smoke.2978239906 May 02 04:11:18 PM PDT 24 May 02 04:11:22 PM PDT 24 5813700071 ps
T790 /workspace/coverage/default/35.adc_ctrl_smoke.860181105 May 02 04:08:25 PM PDT 24 May 02 04:08:33 PM PDT 24 6011435013 ps
T791 /workspace/coverage/default/27.adc_ctrl_smoke.282837682 May 02 04:06:28 PM PDT 24 May 02 04:06:44 PM PDT 24 6079049522 ps
T258 /workspace/coverage/default/21.adc_ctrl_filters_polled.3756200848 May 02 04:04:56 PM PDT 24 May 02 04:06:26 PM PDT 24 165986356058 ps
T72 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1618674262 May 02 02:59:45 PM PDT 24 May 02 02:59:50 PM PDT 24 378663036 ps
T792 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2713391248 May 02 02:59:55 PM PDT 24 May 02 02:59:58 PM PDT 24 449408923 ps
T793 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1271156977 May 02 02:59:53 PM PDT 24 May 02 02:59:56 PM PDT 24 382144159 ps
T794 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2192045542 May 02 03:00:03 PM PDT 24 May 02 03:00:06 PM PDT 24 320474088 ps
T67 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2772524249 May 02 02:59:50 PM PDT 24 May 02 02:59:54 PM PDT 24 459309631 ps
T100 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.373997555 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 541332236 ps
T61 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3933301105 May 02 02:59:53 PM PDT 24 May 02 02:59:58 PM PDT 24 4592232396 ps
T58 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3237724225 May 02 02:59:48 PM PDT 24 May 02 03:00:04 PM PDT 24 4198438363 ps
T59 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2595522524 May 02 02:59:39 PM PDT 24 May 02 02:59:43 PM PDT 24 2107553172 ps
T795 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3747652232 May 02 03:00:04 PM PDT 24 May 02 03:00:07 PM PDT 24 381576677 ps
T68 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1902572537 May 02 02:59:58 PM PDT 24 May 02 03:00:02 PM PDT 24 419613382 ps
T60 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3469388322 May 02 02:59:43 PM PDT 24 May 02 03:01:13 PM PDT 24 26038192731 ps
T62 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.565389131 May 02 02:59:54 PM PDT 24 May 02 03:00:01 PM PDT 24 4288890586 ps
T113 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3670506952 May 02 02:59:48 PM PDT 24 May 02 02:59:52 PM PDT 24 2437287034 ps
T101 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4279844992 May 02 02:59:33 PM PDT 24 May 02 02:59:35 PM PDT 24 487069795 ps
T796 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2234154928 May 02 02:59:51 PM PDT 24 May 02 02:59:54 PM PDT 24 481184496 ps
T69 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1570860572 May 02 02:59:44 PM PDT 24 May 02 02:59:50 PM PDT 24 471689579 ps
T114 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2474008472 May 02 02:59:56 PM PDT 24 May 02 02:59:59 PM PDT 24 331879744 ps
T63 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3195241439 May 02 02:59:28 PM PDT 24 May 02 02:59:38 PM PDT 24 8685640994 ps
T76 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3579076402 May 02 02:59:41 PM PDT 24 May 02 03:00:01 PM PDT 24 8548839090 ps
T102 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3242414384 May 02 02:59:24 PM PDT 24 May 02 02:59:27 PM PDT 24 997728755 ps
T103 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2097738788 May 02 02:59:29 PM PDT 24 May 02 02:59:33 PM PDT 24 475028873 ps
T797 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2008330212 May 02 02:59:52 PM PDT 24 May 02 02:59:55 PM PDT 24 307005017 ps
T798 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1185378240 May 02 02:59:47 PM PDT 24 May 02 02:59:50 PM PDT 24 374345954 ps
T77 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2390277545 May 02 02:59:42 PM PDT 24 May 02 03:00:05 PM PDT 24 8132168453 ps
T115 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.864210186 May 02 02:59:53 PM PDT 24 May 02 02:59:57 PM PDT 24 5718433439 ps
T799 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2129073132 May 02 02:59:55 PM PDT 24 May 02 02:59:58 PM PDT 24 417644829 ps
T800 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1279601271 May 02 02:59:55 PM PDT 24 May 02 02:59:58 PM PDT 24 341189797 ps
T801 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3448420382 May 02 02:59:55 PM PDT 24 May 02 02:59:57 PM PDT 24 345422547 ps
T70 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3455605422 May 02 02:59:54 PM PDT 24 May 02 02:59:58 PM PDT 24 449045979 ps
T104 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3656717791 May 02 02:59:40 PM PDT 24 May 02 02:59:48 PM PDT 24 771629098 ps
T802 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.31569557 May 02 03:00:00 PM PDT 24 May 02 03:00:03 PM PDT 24 477728114 ps
T86 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1718668105 May 02 02:59:53 PM PDT 24 May 02 03:00:17 PM PDT 24 8652569997 ps
T803 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2103583155 May 02 02:59:41 PM PDT 24 May 02 02:59:45 PM PDT 24 803340319 ps
T804 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2122243504 May 02 02:59:56 PM PDT 24 May 02 02:59:58 PM PDT 24 393464890 ps
T116 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1667491868 May 02 02:59:41 PM PDT 24 May 02 02:59:47 PM PDT 24 2463262428 ps
T71 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1808699089 May 02 02:59:52 PM PDT 24 May 02 02:59:57 PM PDT 24 1064404801 ps
T805 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2343789687 May 02 02:59:42 PM PDT 24 May 02 02:59:47 PM PDT 24 895609563 ps
T806 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2160471014 May 02 02:59:43 PM PDT 24 May 02 02:59:48 PM PDT 24 764078327 ps
T807 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2529447203 May 02 02:59:27 PM PDT 24 May 02 02:59:32 PM PDT 24 885981114 ps
T808 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2328485001 May 02 02:59:44 PM PDT 24 May 02 02:59:49 PM PDT 24 589488252 ps
T117 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2226100859 May 02 02:59:26 PM PDT 24 May 02 02:59:34 PM PDT 24 3679632610 ps
T809 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1991727776 May 02 02:59:52 PM PDT 24 May 02 02:59:54 PM PDT 24 351993460 ps
T105 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.470536656 May 02 02:59:44 PM PDT 24 May 02 02:59:48 PM PDT 24 426442601 ps
T78 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3804964018 May 02 02:59:44 PM PDT 24 May 02 02:59:54 PM PDT 24 8440912364 ps
T810 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.970916299 May 02 02:59:56 PM PDT 24 May 02 03:00:00 PM PDT 24 426122015 ps
T811 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3833377756 May 02 03:00:00 PM PDT 24 May 02 03:00:02 PM PDT 24 303552298 ps
T812 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2792314546 May 02 02:59:22 PM PDT 24 May 02 02:59:41 PM PDT 24 27216932977 ps
T813 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.492092241 May 02 02:59:53 PM PDT 24 May 02 02:59:57 PM PDT 24 552433479 ps
T814 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4143483699 May 02 02:59:56 PM PDT 24 May 02 03:00:00 PM PDT 24 567433748 ps
T815 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3017301859 May 02 02:59:53 PM PDT 24 May 02 02:59:57 PM PDT 24 410723662 ps
T816 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1214917700 May 02 02:59:53 PM PDT 24 May 02 02:59:55 PM PDT 24 489693907 ps
T817 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.643080943 May 02 02:59:42 PM PDT 24 May 02 02:59:46 PM PDT 24 522000352 ps
T106 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.365278171 May 02 02:59:42 PM PDT 24 May 02 02:59:46 PM PDT 24 453466191 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1823030674 May 02 02:59:27 PM PDT 24 May 02 02:59:31 PM PDT 24 527046035 ps
T819 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3069280313 May 02 02:59:43 PM PDT 24 May 02 02:59:47 PM PDT 24 345477908 ps
T820 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2301952709 May 02 02:59:42 PM PDT 24 May 02 02:59:50 PM PDT 24 2381604623 ps
T821 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4105587885 May 02 02:59:41 PM PDT 24 May 02 02:59:56 PM PDT 24 2611992027 ps
T822 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4162320120 May 02 02:59:43 PM PDT 24 May 02 03:00:07 PM PDT 24 8084273292 ps
T823 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.507437284 May 02 02:59:40 PM PDT 24 May 02 02:59:43 PM PDT 24 626071672 ps
T824 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2920034810 May 02 02:59:41 PM PDT 24 May 02 02:59:46 PM PDT 24 2606190725 ps
T825 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3531044670 May 02 03:00:05 PM PDT 24 May 02 03:00:09 PM PDT 24 304113726 ps
T826 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3369010063 May 02 02:59:41 PM PDT 24 May 02 02:59:55 PM PDT 24 4083169512 ps
T827 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3195185728 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 502045869 ps
T107 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1121251760 May 02 02:59:35 PM PDT 24 May 02 02:59:39 PM PDT 24 1140801673 ps
T828 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1524561481 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 480374764 ps
T829 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4268784787 May 02 02:59:53 PM PDT 24 May 02 02:59:57 PM PDT 24 562723322 ps
T830 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1462975714 May 02 02:59:29 PM PDT 24 May 02 02:59:37 PM PDT 24 9072310611 ps
T831 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.115807208 May 02 02:59:52 PM PDT 24 May 02 03:00:15 PM PDT 24 8742175620 ps
T832 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1633714025 May 02 02:59:54 PM PDT 24 May 02 03:00:05 PM PDT 24 4096162199 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.936307528 May 02 02:59:43 PM PDT 24 May 02 02:59:50 PM PDT 24 2769894610 ps
T834 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1295620072 May 02 02:59:55 PM PDT 24 May 02 02:59:59 PM PDT 24 529226349 ps
T835 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2302611031 May 02 02:59:46 PM PDT 24 May 02 02:59:52 PM PDT 24 4513886512 ps
T108 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3666256830 May 02 02:59:44 PM PDT 24 May 02 02:59:48 PM PDT 24 459825294 ps
T836 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3451446835 May 02 02:59:53 PM PDT 24 May 02 02:59:56 PM PDT 24 542160588 ps
T837 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3567325852 May 02 02:59:55 PM PDT 24 May 02 02:59:57 PM PDT 24 312083166 ps
T316 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2887998403 May 02 02:59:56 PM PDT 24 May 02 03:00:19 PM PDT 24 8627785087 ps
T109 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.196041226 May 02 02:59:30 PM PDT 24 May 02 02:59:34 PM PDT 24 1131450704 ps
T838 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1117009520 May 02 02:59:59 PM PDT 24 May 02 03:00:01 PM PDT 24 549628210 ps
T317 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1301402649 May 02 02:59:51 PM PDT 24 May 02 03:00:08 PM PDT 24 8013405363 ps
T839 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3064350688 May 02 02:59:52 PM PDT 24 May 02 02:59:58 PM PDT 24 2643637151 ps
T840 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3457248640 May 02 02:59:49 PM PDT 24 May 02 02:59:52 PM PDT 24 549768837 ps
T110 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1656027377 May 02 02:59:43 PM PDT 24 May 02 02:59:49 PM PDT 24 1214813597 ps
T841 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1628656354 May 02 02:59:55 PM PDT 24 May 02 02:59:57 PM PDT 24 362968323 ps
T842 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2061818371 May 02 02:59:44 PM PDT 24 May 02 02:59:48 PM PDT 24 532305956 ps
T843 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2189159888 May 02 03:00:05 PM PDT 24 May 02 03:00:10 PM PDT 24 404988899 ps
T844 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.84353416 May 02 02:59:47 PM PDT 24 May 02 03:00:50 PM PDT 24 26669952510 ps
T845 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2266556762 May 02 02:59:53 PM PDT 24 May 02 02:59:56 PM PDT 24 508840536 ps
T846 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2803234753 May 02 02:59:56 PM PDT 24 May 02 03:00:01 PM PDT 24 982876128 ps
T847 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3036410161 May 02 03:00:08 PM PDT 24 May 02 03:00:11 PM PDT 24 329061180 ps
T318 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2924590869 May 02 02:59:41 PM PDT 24 May 02 02:59:48 PM PDT 24 4429222611 ps
T848 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2150707107 May 02 02:59:42 PM PDT 24 May 02 02:59:46 PM PDT 24 320004115 ps
T849 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1555458544 May 02 02:59:52 PM PDT 24 May 02 02:59:54 PM PDT 24 570826633 ps
T850 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2336415886 May 02 02:59:53 PM PDT 24 May 02 02:59:57 PM PDT 24 420217589 ps
T851 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2194041932 May 02 02:59:56 PM PDT 24 May 02 03:00:02 PM PDT 24 3867071013 ps
T852 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.6325308 May 02 02:59:29 PM PDT 24 May 02 02:59:34 PM PDT 24 610136526 ps
T853 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1203770433 May 02 02:59:44 PM PDT 24 May 02 02:59:55 PM PDT 24 8203060535 ps
T854 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3458412441 May 02 02:59:48 PM PDT 24 May 02 03:00:08 PM PDT 24 5258157003 ps
T111 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1664395342 May 02 02:59:40 PM PDT 24 May 02 02:59:44 PM PDT 24 537875477 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3743927254 May 02 02:59:33 PM PDT 24 May 02 02:59:50 PM PDT 24 4371881590 ps
T856 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.829919008 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 562565699 ps
T857 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.527210685 May 02 02:59:54 PM PDT 24 May 02 02:59:59 PM PDT 24 4165713126 ps
T858 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.704309128 May 02 02:59:44 PM PDT 24 May 02 02:59:48 PM PDT 24 930710977 ps
T859 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3622555550 May 02 03:00:03 PM PDT 24 May 02 03:00:05 PM PDT 24 420567119 ps
T112 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1012013802 May 02 02:59:44 PM PDT 24 May 02 02:59:49 PM PDT 24 542953158 ps
T860 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1649379940 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 1853795589 ps
T861 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3032069491 May 02 02:59:42 PM PDT 24 May 02 02:59:46 PM PDT 24 694143167 ps
T862 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1507629625 May 02 02:59:52 PM PDT 24 May 02 03:00:00 PM PDT 24 4254309073 ps
T863 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.284235184 May 02 02:59:40 PM PDT 24 May 02 02:59:43 PM PDT 24 590737354 ps
T864 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.539620633 May 02 02:59:47 PM PDT 24 May 02 02:59:51 PM PDT 24 452674671 ps
T865 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2870946941 May 02 03:00:00 PM PDT 24 May 02 03:00:02 PM PDT 24 546128574 ps
T866 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2219739760 May 02 02:59:56 PM PDT 24 May 02 03:00:00 PM PDT 24 384244919 ps
T867 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1750149549 May 02 02:59:42 PM PDT 24 May 02 02:59:46 PM PDT 24 501880283 ps
T868 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.374736293 May 02 02:59:42 PM PDT 24 May 02 02:59:47 PM PDT 24 600383241 ps
T869 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2878456082 May 02 03:00:00 PM PDT 24 May 02 03:00:02 PM PDT 24 481500550 ps
T870 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3942680255 May 02 02:59:42 PM PDT 24 May 02 02:59:47 PM PDT 24 1074856269 ps
T871 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2977862224 May 02 02:59:50 PM PDT 24 May 02 02:59:53 PM PDT 24 517290213 ps
T872 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1919181654 May 02 02:59:47 PM PDT 24 May 02 02:59:50 PM PDT 24 400197884 ps
T873 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3935128818 May 02 02:59:42 PM PDT 24 May 02 02:59:59 PM PDT 24 4675480634 ps
T874 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1794839192 May 02 02:59:41 PM PDT 24 May 02 02:59:45 PM PDT 24 341685125 ps
T875 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1989213748 May 02 02:59:48 PM PDT 24 May 02 02:59:51 PM PDT 24 779582324 ps
T876 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4109129478 May 02 02:59:34 PM PDT 24 May 02 03:01:25 PM PDT 24 28877354031 ps
T877 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2063420877 May 02 03:00:03 PM PDT 24 May 02 03:00:06 PM PDT 24 355149774 ps
T878 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1618210751 May 02 02:59:40 PM PDT 24 May 02 02:59:43 PM PDT 24 558598933 ps
T879 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3594888101 May 02 02:59:41 PM PDT 24 May 02 02:59:45 PM PDT 24 541753041 ps
T880 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3017198433 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 427009625 ps
T881 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.150825439 May 02 02:59:40 PM PDT 24 May 02 02:59:44 PM PDT 24 415598640 ps
T882 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1953109675 May 02 02:59:27 PM PDT 24 May 02 02:59:33 PM PDT 24 1245280081 ps
T883 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3865987303 May 02 02:59:45 PM PDT 24 May 02 02:59:50 PM PDT 24 494484125 ps
T884 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2427073640 May 02 03:00:08 PM PDT 24 May 02 03:00:11 PM PDT 24 523177373 ps
T885 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1760520363 May 02 02:59:50 PM PDT 24 May 02 02:59:52 PM PDT 24 353469442 ps
T886 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3925925946 May 02 02:59:56 PM PDT 24 May 02 02:59:59 PM PDT 24 357648115 ps
T887 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.447854271 May 02 02:59:43 PM PDT 24 May 02 02:59:48 PM PDT 24 1986285038 ps
T888 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1767252476 May 02 02:59:42 PM PDT 24 May 02 03:00:16 PM PDT 24 53199008857 ps
T889 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3903610900 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 467217807 ps
T890 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.353842289 May 02 02:59:57 PM PDT 24 May 02 03:00:00 PM PDT 24 424358752 ps
T891 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3537796226 May 02 02:59:39 PM PDT 24 May 02 02:59:43 PM PDT 24 318603461 ps
T892 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3058331895 May 02 02:59:56 PM PDT 24 May 02 02:59:59 PM PDT 24 534098135 ps
T893 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3094886454 May 02 02:59:41 PM PDT 24 May 02 02:59:45 PM PDT 24 412914375 ps
T894 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4178327104 May 02 02:59:28 PM PDT 24 May 02 02:59:31 PM PDT 24 562079319 ps
T895 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.518202680 May 02 02:59:44 PM PDT 24 May 02 02:59:49 PM PDT 24 459814906 ps
T896 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.861327191 May 02 02:59:54 PM PDT 24 May 02 02:59:58 PM PDT 24 432437565 ps
T897 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2276474940 May 02 02:59:42 PM PDT 24 May 02 02:59:47 PM PDT 24 326870647 ps
T898 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1061901506 May 02 03:00:04 PM PDT 24 May 02 03:00:07 PM PDT 24 371180566 ps
T899 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1203211982 May 02 02:59:42 PM PDT 24 May 02 02:59:46 PM PDT 24 402828303 ps
T900 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.163670463 May 02 02:59:55 PM PDT 24 May 02 02:59:57 PM PDT 24 424432960 ps
T901 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3235785965 May 02 02:59:45 PM PDT 24 May 02 02:59:50 PM PDT 24 550872312 ps
T902 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2034624793 May 02 02:59:49 PM PDT 24 May 02 02:59:52 PM PDT 24 368537550 ps
T903 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2369514432 May 02 02:59:55 PM PDT 24 May 02 02:59:59 PM PDT 24 519954006 ps
T904 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2269926695 May 02 02:59:49 PM PDT 24 May 02 03:00:13 PM PDT 24 8290664146 ps
T905 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1472547118 May 02 02:59:52 PM PDT 24 May 02 02:59:55 PM PDT 24 499987884 ps
T906 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1152594318 May 02 02:59:55 PM PDT 24 May 02 03:00:09 PM PDT 24 4631043774 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.955176710 May 02 02:59:42 PM PDT 24 May 02 02:59:45 PM PDT 24 617241688 ps
T908 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.245976654 May 02 02:59:56 PM PDT 24 May 02 02:59:59 PM PDT 24 384114496 ps
T909 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4226756319 May 02 02:59:52 PM PDT 24 May 02 02:59:54 PM PDT 24 534352868 ps
T910 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1517095273 May 02 02:59:28 PM PDT 24 May 02 02:59:31 PM PDT 24 464258920 ps
T911 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3460725538 May 02 02:59:54 PM PDT 24 May 02 02:59:56 PM PDT 24 365097695 ps
T912 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1498306488 May 02 02:59:42 PM PDT 24 May 02 02:59:47 PM PDT 24 701977166 ps
T913 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1490174353 May 02 02:59:43 PM PDT 24 May 02 02:59:53 PM PDT 24 4353538621 ps
T914 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.601870020 May 02 02:59:42 PM PDT 24 May 02 02:59:46 PM PDT 24 449532471 ps
T915 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3884031270 May 02 02:59:34 PM PDT 24 May 02 02:59:36 PM PDT 24 432289612 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4206364346 May 02 02:59:42 PM PDT 24 May 02 02:59:54 PM PDT 24 3818134247 ps
T917 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4107733956 May 02 02:59:54 PM PDT 24 May 02 02:59:57 PM PDT 24 518364686 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1482579860 May 02 02:59:42 PM PDT 24 May 02 02:59:47 PM PDT 24 454745335 ps
T919 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1323853289 May 02 02:59:43 PM PDT 24 May 02 02:59:47 PM PDT 24 378962708 ps

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1727313645
Short name T9
Test name
Test status
Simulation time 509691065526 ps
CPU time 310.09 seconds
Started May 02 04:01:19 PM PDT 24
Finished May 02 04:06:29 PM PDT 24
Peak memory 202248 kb
Host smart-637e20b1-fa30-4852-8a3d-2ff4924674da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727313645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1727313645
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.712734958
Short name T36
Test name
Test status
Simulation time 61255167893 ps
CPU time 256.43 seconds
Started May 02 04:08:37 PM PDT 24
Finished May 02 04:12:54 PM PDT 24
Peak memory 202648 kb
Host smart-e901cd19-62f6-4a67-9e18-79b56488bfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712734958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.712734958
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1814214703
Short name T14
Test name
Test status
Simulation time 438044343122 ps
CPU time 317.83 seconds
Started May 02 04:05:28 PM PDT 24
Finished May 02 04:10:46 PM PDT 24
Peak memory 211012 kb
Host smart-fd9cceee-e4a9-4a1e-9e51-2172a019a696
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814214703 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1814214703
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2478380083
Short name T183
Test name
Test status
Simulation time 434213454617 ps
CPU time 880.96 seconds
Started May 02 04:04:10 PM PDT 24
Finished May 02 04:18:51 PM PDT 24
Peak memory 210880 kb
Host smart-c0941fcb-308b-44a2-9327-c9e36962cfcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478380083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2478380083
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.455476183
Short name T119
Test name
Test status
Simulation time 504148592285 ps
CPU time 194.57 seconds
Started May 02 04:06:52 PM PDT 24
Finished May 02 04:10:08 PM PDT 24
Peak memory 202304 kb
Host smart-92424d07-8c0b-49ff-8d2a-d0c8b1d1e431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455476183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.455476183
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.2466771054
Short name T131
Test name
Test status
Simulation time 528097818685 ps
CPU time 1223.16 seconds
Started May 02 04:00:35 PM PDT 24
Finished May 02 04:20:59 PM PDT 24
Peak memory 202252 kb
Host smart-8f12e2bc-2f91-4b79-b046-31f8cb2c268e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466771054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.2466771054
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3607640078
Short name T11
Test name
Test status
Simulation time 535651292229 ps
CPU time 123.42 seconds
Started May 02 04:11:31 PM PDT 24
Finished May 02 04:13:35 PM PDT 24
Peak memory 202268 kb
Host smart-910d33a5-2588-4bf3-aaf4-caee895f7f9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607640078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3607640078
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.913396568
Short name T194
Test name
Test status
Simulation time 271325864533 ps
CPU time 978.61 seconds
Started May 02 04:10:16 PM PDT 24
Finished May 02 04:26:36 PM PDT 24
Peak memory 202732 kb
Host smart-3509e150-eb5c-46d8-94b7-5a5629c43523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913396568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
913396568
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.333939977
Short name T136
Test name
Test status
Simulation time 493095249106 ps
CPU time 577.23 seconds
Started May 02 04:01:53 PM PDT 24
Finished May 02 04:11:31 PM PDT 24
Peak memory 202328 kb
Host smart-660c99ef-cf63-4cd7-ba93-ed88d5f0769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333939977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.333939977
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3531927849
Short name T147
Test name
Test status
Simulation time 508221077959 ps
CPU time 286.35 seconds
Started May 02 04:09:44 PM PDT 24
Finished May 02 04:14:31 PM PDT 24
Peak memory 202272 kb
Host smart-63554607-971d-428e-b51f-845e6e24cc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531927849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3531927849
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2772524249
Short name T67
Test name
Test status
Simulation time 459309631 ps
CPU time 2.87 seconds
Started May 02 02:59:50 PM PDT 24
Finished May 02 02:59:54 PM PDT 24
Peak memory 201520 kb
Host smart-079156f6-f843-472b-bf51-55d28a8d06cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772524249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2772524249
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2869072906
Short name T43
Test name
Test status
Simulation time 572193237092 ps
CPU time 872.68 seconds
Started May 02 04:01:37 PM PDT 24
Finished May 02 04:16:11 PM PDT 24
Peak memory 202328 kb
Host smart-5ef5848d-0d6e-4a77-95df-80014f966002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869072906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2869072906
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2239594632
Short name T30
Test name
Test status
Simulation time 4191483518 ps
CPU time 11.12 seconds
Started May 02 04:00:05 PM PDT 24
Finished May 02 04:00:17 PM PDT 24
Peak memory 217924 kb
Host smart-1151a23a-a83c-4db0-a7a1-6236bf075c90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239594632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2239594632
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3874948479
Short name T49
Test name
Test status
Simulation time 488248501283 ps
CPU time 304.41 seconds
Started May 02 04:08:20 PM PDT 24
Finished May 02 04:13:25 PM PDT 24
Peak memory 202296 kb
Host smart-f395adfe-eae9-4830-9645-3459075ce18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874948479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3874948479
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.4068995970
Short name T198
Test name
Test status
Simulation time 521924921844 ps
CPU time 328.96 seconds
Started May 02 04:00:24 PM PDT 24
Finished May 02 04:05:54 PM PDT 24
Peak memory 202372 kb
Host smart-61ba1116-3cc7-420b-acdd-de02fba7be4b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068995970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.4068995970
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3811582096
Short name T46
Test name
Test status
Simulation time 141189522150 ps
CPU time 32.23 seconds
Started May 02 04:10:27 PM PDT 24
Finished May 02 04:11:00 PM PDT 24
Peak memory 210968 kb
Host smart-af7a6037-0bcc-4486-ba6b-937f6097588f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811582096 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3811582096
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2621642497
Short name T24
Test name
Test status
Simulation time 523031634070 ps
CPU time 313.97 seconds
Started May 02 04:02:13 PM PDT 24
Finished May 02 04:07:28 PM PDT 24
Peak memory 202416 kb
Host smart-4c821a9c-aac5-4d99-ba22-9a583d0f6ef2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621642497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2621642497
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3015713136
Short name T10
Test name
Test status
Simulation time 334208274546 ps
CPU time 220.25 seconds
Started May 02 04:04:31 PM PDT 24
Finished May 02 04:08:12 PM PDT 24
Peak memory 202288 kb
Host smart-5b724fa3-64cb-44b8-936c-3170db2d7900
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015713136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3015713136
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.1846533871
Short name T160
Test name
Test status
Simulation time 350453171590 ps
CPU time 201.98 seconds
Started May 02 04:02:25 PM PDT 24
Finished May 02 04:05:48 PM PDT 24
Peak memory 202336 kb
Host smart-8cc5c42f-0824-46e4-a6c4-4bf91c59dab6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846533871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.1846533871
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2097738788
Short name T103
Test name
Test status
Simulation time 475028873 ps
CPU time 2.02 seconds
Started May 02 02:59:29 PM PDT 24
Finished May 02 02:59:33 PM PDT 24
Peak memory 201236 kb
Host smart-3de9c887-195f-411d-8f2b-6098fb443152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097738788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2097738788
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4034389232
Short name T265
Test name
Test status
Simulation time 87340319210 ps
CPU time 191.26 seconds
Started May 02 04:07:59 PM PDT 24
Finished May 02 04:11:11 PM PDT 24
Peak memory 212968 kb
Host smart-3bbf1355-b1af-4971-a0b3-ecfe0229ecdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034389232 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4034389232
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2667171146
Short name T222
Test name
Test status
Simulation time 488976629416 ps
CPU time 366.76 seconds
Started May 02 04:03:33 PM PDT 24
Finished May 02 04:09:40 PM PDT 24
Peak memory 202308 kb
Host smart-d6c286b5-9bb9-43c3-a23a-fe6f179ecaa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667171146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2667171146
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1689609183
Short name T200
Test name
Test status
Simulation time 349126097137 ps
CPU time 56.35 seconds
Started May 02 04:08:39 PM PDT 24
Finished May 02 04:09:35 PM PDT 24
Peak memory 202264 kb
Host smart-0fa7afce-a7fd-4cc6-bd7e-8b4e77a2c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689609183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1689609183
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.760180510
Short name T195
Test name
Test status
Simulation time 334668304737 ps
CPU time 225.06 seconds
Started May 02 04:02:57 PM PDT 24
Finished May 02 04:06:43 PM PDT 24
Peak memory 202364 kb
Host smart-f5812804-038f-48a1-92f0-9e2a65dc6c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760180510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all.
760180510
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.4092549765
Short name T162
Test name
Test status
Simulation time 518037708734 ps
CPU time 88.41 seconds
Started May 02 04:10:34 PM PDT 24
Finished May 02 04:12:03 PM PDT 24
Peak memory 202380 kb
Host smart-cef444ea-3739-4d07-b289-fa437b4a8ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092549765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.4092549765
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3033032447
Short name T221
Test name
Test status
Simulation time 402098715813 ps
CPU time 161.88 seconds
Started May 02 04:07:55 PM PDT 24
Finished May 02 04:10:37 PM PDT 24
Peak memory 202296 kb
Host smart-ac870ad6-f67d-45ff-a17c-fa3ba91d93a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033032447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3033032447
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.4115178551
Short name T50
Test name
Test status
Simulation time 585727438928 ps
CPU time 295.1 seconds
Started May 02 04:05:52 PM PDT 24
Finished May 02 04:10:48 PM PDT 24
Peak memory 202292 kb
Host smart-e4ac207b-b0d0-4dde-97e5-14c13fbc5362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115178551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.4115178551
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.980126973
Short name T34
Test name
Test status
Simulation time 203046599569 ps
CPU time 350.35 seconds
Started May 02 04:02:37 PM PDT 24
Finished May 02 04:08:27 PM PDT 24
Peak memory 210644 kb
Host smart-8a5e3e63-a074-4431-aee4-66366a116ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980126973 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.980126973
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1808273617
Short name T247
Test name
Test status
Simulation time 400622181481 ps
CPU time 439.49 seconds
Started May 02 04:04:18 PM PDT 24
Finished May 02 04:11:39 PM PDT 24
Peak memory 202324 kb
Host smart-caa09590-7147-4eca-ba88-e4fbbea20f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808273617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1808273617
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1190281847
Short name T211
Test name
Test status
Simulation time 324089576295 ps
CPU time 737.8 seconds
Started May 02 04:06:10 PM PDT 24
Finished May 02 04:18:28 PM PDT 24
Peak memory 202372 kb
Host smart-1e3fe63d-4b52-4f62-bed4-63f30c8ab36f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190281847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1190281847
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3194495772
Short name T250
Test name
Test status
Simulation time 695047588620 ps
CPU time 381.54 seconds
Started May 02 04:01:18 PM PDT 24
Finished May 02 04:07:40 PM PDT 24
Peak memory 202256 kb
Host smart-281d6d68-d38e-4727-b411-11c6ebfc72b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194495772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3194495772
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.3074166925
Short name T73
Test name
Test status
Simulation time 300971948 ps
CPU time 1.3 seconds
Started May 02 04:00:05 PM PDT 24
Finished May 02 04:00:06 PM PDT 24
Peak memory 202020 kb
Host smart-900c2a63-143e-48f9-808b-84dcedede87a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074166925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.3074166925
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.1860041767
Short name T209
Test name
Test status
Simulation time 490635394544 ps
CPU time 1044.77 seconds
Started May 02 04:10:21 PM PDT 24
Finished May 02 04:27:47 PM PDT 24
Peak memory 202320 kb
Host smart-5e023acd-2ee3-479d-b65b-095873b2abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860041767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.1860041767
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1462975714
Short name T830
Test name
Test status
Simulation time 9072310611 ps
CPU time 5.72 seconds
Started May 02 02:59:29 PM PDT 24
Finished May 02 02:59:37 PM PDT 24
Peak memory 201436 kb
Host smart-9a662d48-fc49-4d84-a050-bb4a9f0d345b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462975714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1462975714
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.2792314546
Short name T812
Test name
Test status
Simulation time 27216932977 ps
CPU time 17.63 seconds
Started May 02 02:59:22 PM PDT 24
Finished May 02 02:59:41 PM PDT 24
Peak memory 201524 kb
Host smart-7197942a-48fe-48f5-b10f-cabd449e0eab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792314546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.2792314546
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3399622907
Short name T180
Test name
Test status
Simulation time 314131861603 ps
CPU time 1044.1 seconds
Started May 02 04:10:52 PM PDT 24
Finished May 02 04:28:17 PM PDT 24
Peak memory 210876 kb
Host smart-cccefc56-37a0-4d75-9d5d-c28234ca2ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399622907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3399622907
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2757890058
Short name T139
Test name
Test status
Simulation time 504645419248 ps
CPU time 206.68 seconds
Started May 02 04:04:39 PM PDT 24
Finished May 02 04:08:07 PM PDT 24
Peak memory 202268 kb
Host smart-7779a499-f709-4c4d-bd85-022badf17dc5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757890058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2757890058
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1871624118
Short name T213
Test name
Test status
Simulation time 181296118755 ps
CPU time 80.91 seconds
Started May 02 04:11:20 PM PDT 24
Finished May 02 04:12:42 PM PDT 24
Peak memory 202320 kb
Host smart-6f209e9a-adb5-4cee-b6ff-9cb4a83b7bf1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871624118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1871624118
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2332342473
Short name T215
Test name
Test status
Simulation time 341842911843 ps
CPU time 278.12 seconds
Started May 02 04:00:17 PM PDT 24
Finished May 02 04:04:56 PM PDT 24
Peak memory 210940 kb
Host smart-cc33a575-0ef8-4386-81a4-03765a8a17b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332342473 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2332342473
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3913379829
Short name T235
Test name
Test status
Simulation time 500233061858 ps
CPU time 1209.3 seconds
Started May 02 04:07:23 PM PDT 24
Finished May 02 04:27:33 PM PDT 24
Peak memory 202408 kb
Host smart-69eff263-f7ec-4e01-9e6c-390d64482f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913379829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3913379829
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3121721721
Short name T277
Test name
Test status
Simulation time 522622269903 ps
CPU time 661.31 seconds
Started May 02 04:10:23 PM PDT 24
Finished May 02 04:21:26 PM PDT 24
Peak memory 202312 kb
Host smart-57ad2b3c-2d5a-4e71-82f2-650f1bfe23eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121721721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3121721721
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2202561212
Short name T224
Test name
Test status
Simulation time 325528698916 ps
CPU time 97.05 seconds
Started May 02 04:02:51 PM PDT 24
Finished May 02 04:04:29 PM PDT 24
Peak memory 202340 kb
Host smart-b0e14b9c-92e9-4a37-b385-7a5deebc9602
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202561212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2202561212
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.462965201
Short name T124
Test name
Test status
Simulation time 499840957696 ps
CPU time 641.99 seconds
Started May 02 04:03:33 PM PDT 24
Finished May 02 04:14:16 PM PDT 24
Peak memory 202300 kb
Host smart-9ddf50e2-32f8-4b42-8141-8922edcd3689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462965201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.462965201
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4249833000
Short name T296
Test name
Test status
Simulation time 507510133846 ps
CPU time 274.12 seconds
Started May 02 04:02:20 PM PDT 24
Finished May 02 04:06:55 PM PDT 24
Peak memory 202280 kb
Host smart-31ec4ad2-d8b6-4a8f-af79-b9ece0b9f271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249833000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4249833000
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.2308427435
Short name T19
Test name
Test status
Simulation time 704924807554 ps
CPU time 253.69 seconds
Started May 02 04:05:35 PM PDT 24
Finished May 02 04:09:49 PM PDT 24
Peak memory 211072 kb
Host smart-79aad6f5-44cf-4673-ac2b-99867f1232f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308427435 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.2308427435
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.4148982607
Short name T173
Test name
Test status
Simulation time 491680437856 ps
CPU time 603.95 seconds
Started May 02 04:03:11 PM PDT 24
Finished May 02 04:13:15 PM PDT 24
Peak memory 202400 kb
Host smart-c68d0a0f-0f15-4359-bf82-8c2f2e5c3ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148982607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.4148982607
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.236252349
Short name T259
Test name
Test status
Simulation time 328042001850 ps
CPU time 207.09 seconds
Started May 02 04:00:24 PM PDT 24
Finished May 02 04:03:52 PM PDT 24
Peak memory 202256 kb
Host smart-3c15f253-7bfc-4707-8c43-fcb05ae58431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236252349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.236252349
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.835877589
Short name T241
Test name
Test status
Simulation time 333711060708 ps
CPU time 152.41 seconds
Started May 02 04:11:12 PM PDT 24
Finished May 02 04:13:46 PM PDT 24
Peak memory 202304 kb
Host smart-922ea00f-3bc8-49d1-8353-64ac37d9764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835877589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.835877589
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2583820753
Short name T189
Test name
Test status
Simulation time 295399799285 ps
CPU time 1024.76 seconds
Started May 02 04:11:17 PM PDT 24
Finished May 02 04:28:22 PM PDT 24
Peak memory 210912 kb
Host smart-816aa780-c8e5-4297-916c-811f324ae297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583820753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2583820753
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3740087235
Short name T292
Test name
Test status
Simulation time 40771189012 ps
CPU time 67.48 seconds
Started May 02 04:00:04 PM PDT 24
Finished May 02 04:01:12 PM PDT 24
Peak memory 210572 kb
Host smart-0ba82b43-d04a-4d52-a23e-30137104c4b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740087235 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3740087235
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1776477920
Short name T48
Test name
Test status
Simulation time 343100937604 ps
CPU time 206.55 seconds
Started May 02 04:03:50 PM PDT 24
Finished May 02 04:07:17 PM PDT 24
Peak memory 202308 kb
Host smart-a10c4f3d-d873-4675-87a7-36bd288f3bbf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776477920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1776477920
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1855275188
Short name T146
Test name
Test status
Simulation time 542060939764 ps
CPU time 841.66 seconds
Started May 02 04:05:01 PM PDT 24
Finished May 02 04:19:03 PM PDT 24
Peak memory 202252 kb
Host smart-6687a8aa-c8b8-439c-9934-599b82656db0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855275188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1855275188
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2802825380
Short name T169
Test name
Test status
Simulation time 485655602795 ps
CPU time 120.92 seconds
Started May 02 04:07:28 PM PDT 24
Finished May 02 04:09:30 PM PDT 24
Peak memory 202316 kb
Host smart-902ec28b-8680-4477-98aa-d2848b8a94e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802825380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2802825380
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1385727000
Short name T274
Test name
Test status
Simulation time 333613879492 ps
CPU time 544.91 seconds
Started May 02 04:00:50 PM PDT 24
Finished May 02 04:09:55 PM PDT 24
Peak memory 202644 kb
Host smart-5d2bad5e-5987-476b-8bf5-73371c33a3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385727000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1385727000
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3017301859
Short name T815
Test name
Test status
Simulation time 410723662 ps
CPU time 2.17 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201484 kb
Host smart-bac687d7-cf04-4960-9d5b-0e26bf8ec807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017301859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3017301859
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3978998336
Short name T272
Test name
Test status
Simulation time 173042729439 ps
CPU time 47.27 seconds
Started May 02 04:03:30 PM PDT 24
Finished May 02 04:04:18 PM PDT 24
Peak memory 202260 kb
Host smart-89ff4c5b-8bb0-4617-8ccb-5b68bac0125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978998336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3978998336
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1055635117
Short name T295
Test name
Test status
Simulation time 370465393106 ps
CPU time 465.13 seconds
Started May 02 04:04:09 PM PDT 24
Finished May 02 04:11:55 PM PDT 24
Peak memory 202340 kb
Host smart-5c7a0540-702f-47f4-a1d3-cd611ede57b0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055635117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1055635117
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.611799509
Short name T261
Test name
Test status
Simulation time 509800878700 ps
CPU time 1206.69 seconds
Started May 02 04:09:02 PM PDT 24
Finished May 02 04:29:10 PM PDT 24
Peak memory 202392 kb
Host smart-a2c95193-15e8-40c6-9d1b-fb6854951a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611799509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.611799509
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.1543193305
Short name T163
Test name
Test status
Simulation time 496783905651 ps
CPU time 171.75 seconds
Started May 02 04:05:27 PM PDT 24
Finished May 02 04:08:19 PM PDT 24
Peak memory 202280 kb
Host smart-fe21fa45-1ebc-4e83-8817-4aa8b9e7be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543193305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.1543193305
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.2284945449
Short name T244
Test name
Test status
Simulation time 164586645483 ps
CPU time 381.11 seconds
Started May 02 04:00:24 PM PDT 24
Finished May 02 04:06:46 PM PDT 24
Peak memory 202368 kb
Host smart-b442a152-2e1d-4289-8d37-4f71101e8837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284945449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
2284945449
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2235581270
Short name T229
Test name
Test status
Simulation time 325998987976 ps
CPU time 747.2 seconds
Started May 02 04:09:37 PM PDT 24
Finished May 02 04:22:06 PM PDT 24
Peak memory 202280 kb
Host smart-572b98a2-eb78-4fc2-b489-50fd3d2afa2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235581270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2235581270
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.3430842215
Short name T218
Test name
Test status
Simulation time 328462701675 ps
CPU time 667.6 seconds
Started May 02 04:10:01 PM PDT 24
Finished May 02 04:21:09 PM PDT 24
Peak memory 202352 kb
Host smart-337ea8ad-51bd-4005-a1dd-5a46a17280b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430842215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.3430842215
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3382601725
Short name T216
Test name
Test status
Simulation time 488578291458 ps
CPU time 497.7 seconds
Started May 02 04:10:45 PM PDT 24
Finished May 02 04:19:03 PM PDT 24
Peak memory 202288 kb
Host smart-bf5b1b0b-8da3-4c7b-bf63-df3eeb1fe312
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382601725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3382601725
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1485547424
Short name T205
Test name
Test status
Simulation time 541687256514 ps
CPU time 463.89 seconds
Started May 02 04:00:41 PM PDT 24
Finished May 02 04:08:26 PM PDT 24
Peak memory 202296 kb
Host smart-c11de7e4-cfc0-4ecb-ac30-73b3930ab16d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485547424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1485547424
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2055941644
Short name T267
Test name
Test status
Simulation time 326907396306 ps
CPU time 47.35 seconds
Started May 02 04:00:05 PM PDT 24
Finished May 02 04:00:53 PM PDT 24
Peak memory 202396 kb
Host smart-b37c3b2f-4120-4779-bd06-f95d201dfe1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055941644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2055941644
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.193119592
Short name T320
Test name
Test status
Simulation time 294335337413 ps
CPU time 539.24 seconds
Started May 02 04:00:11 PM PDT 24
Finished May 02 04:09:11 PM PDT 24
Peak memory 210864 kb
Host smart-cb4474ae-526e-4c30-af18-d0e4236484ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193119592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.193119592
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.3756200848
Short name T258
Test name
Test status
Simulation time 165986356058 ps
CPU time 89.2 seconds
Started May 02 04:04:56 PM PDT 24
Finished May 02 04:06:26 PM PDT 24
Peak memory 202368 kb
Host smart-c74bdeec-631a-4b3a-aeca-8b516fb40dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756200848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.3756200848
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2715332391
Short name T231
Test name
Test status
Simulation time 521771880251 ps
CPU time 1176.93 seconds
Started May 02 04:06:35 PM PDT 24
Finished May 02 04:26:13 PM PDT 24
Peak memory 202384 kb
Host smart-77977361-1469-4f58-a2e4-1cbddff6bbd2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715332391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2715332391
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3005293412
Short name T299
Test name
Test status
Simulation time 325422169986 ps
CPU time 733.48 seconds
Started May 02 04:06:39 PM PDT 24
Finished May 02 04:18:53 PM PDT 24
Peak memory 202328 kb
Host smart-e3460891-9eca-416c-aece-7e500fe6e1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005293412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3005293412
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.160552256
Short name T193
Test name
Test status
Simulation time 192991755462 ps
CPU time 442.84 seconds
Started May 02 04:07:53 PM PDT 24
Finished May 02 04:15:17 PM PDT 24
Peak memory 202300 kb
Host smart-ee54a8e7-e39c-4144-84ad-3dc04db5b3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160552256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.160552256
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.747062417
Short name T89
Test name
Test status
Simulation time 147818662174 ps
CPU time 236.66 seconds
Started May 02 04:08:19 PM PDT 24
Finished May 02 04:12:16 PM PDT 24
Peak memory 210648 kb
Host smart-5955904f-f53c-48dc-bf0d-e030573188d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747062417 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.747062417
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2924590869
Short name T318
Test name
Test status
Simulation time 4429222611 ps
CPU time 3.86 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201552 kb
Host smart-b18c8e7b-1d5e-45a7-9fec-e560f7bf361c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924590869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2924590869
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2322779770
Short name T325
Test name
Test status
Simulation time 98819288041 ps
CPU time 352.89 seconds
Started May 02 04:00:04 PM PDT 24
Finished May 02 04:05:58 PM PDT 24
Peak memory 202664 kb
Host smart-50829d5b-d293-41e6-9d03-1158d49a7e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322779770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2322779770
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.326295011
Short name T186
Test name
Test status
Simulation time 131821730282 ps
CPU time 703.2 seconds
Started May 02 04:00:05 PM PDT 24
Finished May 02 04:11:49 PM PDT 24
Peak memory 202764 kb
Host smart-792bb1ea-a56c-46d6-99c6-438401ba0ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326295011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.326295011
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2244579401
Short name T321
Test name
Test status
Simulation time 107113106577 ps
CPU time 388.77 seconds
Started May 02 04:03:17 PM PDT 24
Finished May 02 04:09:47 PM PDT 24
Peak memory 202740 kb
Host smart-2d1299a3-cd6c-45ba-b77c-7beb6b97ad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244579401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2244579401
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.312804285
Short name T187
Test name
Test status
Simulation time 104974073825 ps
CPU time 546.64 seconds
Started May 02 04:04:26 PM PDT 24
Finished May 02 04:13:33 PM PDT 24
Peak memory 202612 kb
Host smart-d70675d3-4ebd-4c52-846e-f8ec92f3e5c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312804285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all.
312804285
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1280616125
Short name T270
Test name
Test status
Simulation time 544487130673 ps
CPU time 320.13 seconds
Started May 02 04:04:52 PM PDT 24
Finished May 02 04:10:13 PM PDT 24
Peak memory 202336 kb
Host smart-5d1c05ac-c8ed-42eb-8121-99d313e9f8ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280616125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1280616125
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.892104535
Short name T177
Test name
Test status
Simulation time 207766259342 ps
CPU time 1103.46 seconds
Started May 02 04:06:01 PM PDT 24
Finished May 02 04:24:25 PM PDT 24
Peak memory 211896 kb
Host smart-eb6efde2-6037-4a47-9432-ff08c1cf6262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892104535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
892104535
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2917876345
Short name T290
Test name
Test status
Simulation time 539447910063 ps
CPU time 616.32 seconds
Started May 02 04:06:12 PM PDT 24
Finished May 02 04:16:29 PM PDT 24
Peak memory 202304 kb
Host smart-a175a644-892b-4d86-b9b9-905d36335f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917876345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2917876345
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.442502192
Short name T281
Test name
Test status
Simulation time 208528448344 ps
CPU time 77.73 seconds
Started May 02 04:07:53 PM PDT 24
Finished May 02 04:09:12 PM PDT 24
Peak memory 202388 kb
Host smart-82e6c38e-b149-4b12-8a5a-2a56ba870e24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442502192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.442502192
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.791509654
Short name T278
Test name
Test status
Simulation time 164724386501 ps
CPU time 78.26 seconds
Started May 02 04:08:30 PM PDT 24
Finished May 02 04:09:48 PM PDT 24
Peak memory 202280 kb
Host smart-fc997c04-b700-4b6b-8af0-d0595e0764b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791509654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.791509654
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.424404803
Short name T225
Test name
Test status
Simulation time 326129584996 ps
CPU time 217.87 seconds
Started May 02 04:10:01 PM PDT 24
Finished May 02 04:13:40 PM PDT 24
Peak memory 202260 kb
Host smart-28354bc8-bd14-43d1-89c0-207092b8d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424404803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.424404803
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2260566691
Short name T230
Test name
Test status
Simulation time 226305552874 ps
CPU time 455.65 seconds
Started May 02 04:00:50 PM PDT 24
Finished May 02 04:08:26 PM PDT 24
Peak memory 211004 kb
Host smart-68c654b6-88c6-4750-a22d-26b278518494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260566691 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2260566691
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1953109675
Short name T882
Test name
Test status
Simulation time 1245280081 ps
CPU time 3.24 seconds
Started May 02 02:59:27 PM PDT 24
Finished May 02 02:59:33 PM PDT 24
Peak memory 201372 kb
Host smart-930e07e0-f4eb-436a-80f2-b0afd3ec88c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953109675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1953109675
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3242414384
Short name T102
Test name
Test status
Simulation time 997728755 ps
CPU time 1.04 seconds
Started May 02 02:59:24 PM PDT 24
Finished May 02 02:59:27 PM PDT 24
Peak memory 201176 kb
Host smart-c33e5729-c72d-41de-86c6-6f5bac5179e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242414384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3242414384
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1517095273
Short name T910
Test name
Test status
Simulation time 464258920 ps
CPU time 1.06 seconds
Started May 02 02:59:28 PM PDT 24
Finished May 02 02:59:31 PM PDT 24
Peak memory 201320 kb
Host smart-4b66d4f9-79c4-49e3-af03-c15dab2a2b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517095273 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1517095273
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.4178327104
Short name T894
Test name
Test status
Simulation time 562079319 ps
CPU time 0.99 seconds
Started May 02 02:59:28 PM PDT 24
Finished May 02 02:59:31 PM PDT 24
Peak memory 201168 kb
Host smart-d07c0dea-a8bc-40f7-8660-a0d55845df0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178327104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.4178327104
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2226100859
Short name T117
Test name
Test status
Simulation time 3679632610 ps
CPU time 5.54 seconds
Started May 02 02:59:26 PM PDT 24
Finished May 02 02:59:34 PM PDT 24
Peak memory 201492 kb
Host smart-5a57ec63-41ac-4938-a702-c12f8c05edba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226100859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2226100859
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.6325308
Short name T852
Test name
Test status
Simulation time 610136526 ps
CPU time 2.85 seconds
Started May 02 02:59:29 PM PDT 24
Finished May 02 02:59:34 PM PDT 24
Peak memory 201384 kb
Host smart-06792569-1480-4da0-8007-fcd6253e4701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6325308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.6325308
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3195241439
Short name T63
Test name
Test status
Simulation time 8685640994 ps
CPU time 7.65 seconds
Started May 02 02:59:28 PM PDT 24
Finished May 02 02:59:38 PM PDT 24
Peak memory 201464 kb
Host smart-4704448a-d50c-4f52-854a-bc7455d9ce56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195241439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3195241439
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.1121251760
Short name T107
Test name
Test status
Simulation time 1140801673 ps
CPU time 3.07 seconds
Started May 02 02:59:35 PM PDT 24
Finished May 02 02:59:39 PM PDT 24
Peak memory 201444 kb
Host smart-a7b22d92-3b40-4f84-9383-168c50939f0b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121251760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.1121251760
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4109129478
Short name T876
Test name
Test status
Simulation time 28877354031 ps
CPU time 110.11 seconds
Started May 02 02:59:34 PM PDT 24
Finished May 02 03:01:25 PM PDT 24
Peak memory 201452 kb
Host smart-f2a57b4b-7cb0-44e9-b414-a4f8114ab926
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109129478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4109129478
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.196041226
Short name T109
Test name
Test status
Simulation time 1131450704 ps
CPU time 2.11 seconds
Started May 02 02:59:30 PM PDT 24
Finished May 02 02:59:34 PM PDT 24
Peak memory 201212 kb
Host smart-7d0baae5-fc50-4661-8f75-b407b73ac899
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196041226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.196041226
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3884031270
Short name T915
Test name
Test status
Simulation time 432289612 ps
CPU time 1.1 seconds
Started May 02 02:59:34 PM PDT 24
Finished May 02 02:59:36 PM PDT 24
Peak memory 201272 kb
Host smart-fffb1827-1d89-4901-a051-cd3e3d9cb344
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884031270 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3884031270
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.4279844992
Short name T101
Test name
Test status
Simulation time 487069795 ps
CPU time 1.25 seconds
Started May 02 02:59:33 PM PDT 24
Finished May 02 02:59:35 PM PDT 24
Peak memory 201188 kb
Host smart-42cfe35b-7820-4572-b5c9-32cf1ef58544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279844992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.4279844992
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1823030674
Short name T818
Test name
Test status
Simulation time 527046035 ps
CPU time 1.25 seconds
Started May 02 02:59:27 PM PDT 24
Finished May 02 02:59:31 PM PDT 24
Peak memory 201156 kb
Host smart-fe0023f4-32bf-4969-b252-0abae78c0e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823030674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1823030674
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3743927254
Short name T855
Test name
Test status
Simulation time 4371881590 ps
CPU time 16.14 seconds
Started May 02 02:59:33 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 201520 kb
Host smart-4735afe1-8663-4c6f-8fc4-352537d2579f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743927254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3743927254
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2529447203
Short name T807
Test name
Test status
Simulation time 885981114 ps
CPU time 2.62 seconds
Started May 02 02:59:27 PM PDT 24
Finished May 02 02:59:32 PM PDT 24
Peak memory 210720 kb
Host smart-d6670b52-72ad-40fa-98a6-d60b32753449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529447203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2529447203
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3865987303
Short name T883
Test name
Test status
Simulation time 494484125 ps
CPU time 1.97 seconds
Started May 02 02:59:45 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 201268 kb
Host smart-0619d5ed-a156-4832-b960-ba85c642ac9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865987303 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3865987303
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1919181654
Short name T872
Test name
Test status
Simulation time 400197884 ps
CPU time 1.04 seconds
Started May 02 02:59:47 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 201220 kb
Host smart-82febd82-5602-427a-9a26-3c07ae1dc78e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919181654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1919181654
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1750149549
Short name T867
Test name
Test status
Simulation time 501880283 ps
CPU time 1.93 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201136 kb
Host smart-b513fd24-72a8-4d2d-84ab-f271e0d117ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750149549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1750149549
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1667491868
Short name T116
Test name
Test status
Simulation time 2463262428 ps
CPU time 3.16 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201224 kb
Host smart-27ca624e-ded7-4b2e-a7c6-68e006ceb202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667491868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1667491868
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2328485001
Short name T808
Test name
Test status
Simulation time 589488252 ps
CPU time 1.81 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:49 PM PDT 24
Peak memory 201456 kb
Host smart-8772ae7f-f5b1-4e34-a65d-a3a9c5442b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328485001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2328485001
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1555458544
Short name T849
Test name
Test status
Simulation time 570826633 ps
CPU time 1.43 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 02:59:54 PM PDT 24
Peak memory 201280 kb
Host smart-1c47b158-97db-4ae5-b60d-c5f1c5a7f35a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555458544 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1555458544
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.3925925946
Short name T886
Test name
Test status
Simulation time 357648115 ps
CPU time 1.06 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201156 kb
Host smart-54cc0624-4b1a-4ed4-9276-76e19486d68a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925925946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.3925925946
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2122243504
Short name T804
Test name
Test status
Simulation time 393464890 ps
CPU time 0.75 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201220 kb
Host smart-3a952e22-d836-4b18-86d6-f6e0efd22289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122243504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2122243504
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3670506952
Short name T113
Test name
Test status
Simulation time 2437287034 ps
CPU time 2 seconds
Started May 02 02:59:48 PM PDT 24
Finished May 02 02:59:52 PM PDT 24
Peak memory 201268 kb
Host smart-3674597d-f59e-4ed6-be92-434b2e354dd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670506952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3670506952
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3933301105
Short name T61
Test name
Test status
Simulation time 4592232396 ps
CPU time 3.33 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201532 kb
Host smart-7d6ca689-bf0a-46b5-866b-364529cc971b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933301105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3933301105
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.2266556762
Short name T845
Test name
Test status
Simulation time 508840536 ps
CPU time 1.28 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:56 PM PDT 24
Peak memory 201296 kb
Host smart-18ce42ff-f617-46d7-9b14-866adc948a36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266556762 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.2266556762
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.539620633
Short name T864
Test name
Test status
Simulation time 452674671 ps
CPU time 1.9 seconds
Started May 02 02:59:47 PM PDT 24
Finished May 02 02:59:51 PM PDT 24
Peak memory 201252 kb
Host smart-7a4390b5-01ab-473a-b330-7cbb0be7d95d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539620633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.539620633
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1214917700
Short name T816
Test name
Test status
Simulation time 489693907 ps
CPU time 0.98 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:55 PM PDT 24
Peak memory 201244 kb
Host smart-587b7a9e-fb91-481f-9ee6-a61165900992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214917700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1214917700
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2194041932
Short name T851
Test name
Test status
Simulation time 3867071013 ps
CPU time 4.45 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 03:00:02 PM PDT 24
Peak memory 201468 kb
Host smart-03526b30-9739-4875-a4a0-c15489f44eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194041932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2194041932
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1808699089
Short name T71
Test name
Test status
Simulation time 1064404801 ps
CPU time 3.14 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201456 kb
Host smart-fe10683c-d305-4ad1-811a-eb2060d7259a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808699089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1808699089
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.527210685
Short name T857
Test name
Test status
Simulation time 4165713126 ps
CPU time 4.09 seconds
Started May 02 02:59:54 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201400 kb
Host smart-38bba766-3359-4c8a-b294-845461817978
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527210685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.527210685
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1472547118
Short name T905
Test name
Test status
Simulation time 499987884 ps
CPU time 2.05 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 02:59:55 PM PDT 24
Peak memory 201288 kb
Host smart-87556b1a-7910-49a6-9b49-868ef7dbfb9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472547118 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1472547118
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4226756319
Short name T909
Test name
Test status
Simulation time 534352868 ps
CPU time 0.99 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 02:59:54 PM PDT 24
Peak memory 201244 kb
Host smart-3ec1a149-943e-4b02-9f65-6f7537e393d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226756319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4226756319
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1271156977
Short name T793
Test name
Test status
Simulation time 382144159 ps
CPU time 1.57 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:56 PM PDT 24
Peak memory 201244 kb
Host smart-a8913c87-5738-4c6e-a9d7-0d848f17b89f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271156977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1271156977
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3064350688
Short name T839
Test name
Test status
Simulation time 2643637151 ps
CPU time 4.84 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201264 kb
Host smart-e589c375-e48d-42bb-b6f3-437d457e98a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064350688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3064350688
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.2269926695
Short name T904
Test name
Test status
Simulation time 8290664146 ps
CPU time 22.21 seconds
Started May 02 02:59:49 PM PDT 24
Finished May 02 03:00:13 PM PDT 24
Peak memory 201504 kb
Host smart-f9ab552b-241c-4802-8d7f-7938926a096c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269926695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.2269926695
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3451446835
Short name T836
Test name
Test status
Simulation time 542160588 ps
CPU time 1.34 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:56 PM PDT 24
Peak memory 201160 kb
Host smart-fa61acfa-c369-41ec-9176-30ca615f2475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451446835 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3451446835
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1760520363
Short name T885
Test name
Test status
Simulation time 353469442 ps
CPU time 0.94 seconds
Started May 02 02:59:50 PM PDT 24
Finished May 02 02:59:52 PM PDT 24
Peak memory 201216 kb
Host smart-d3c73a68-76d3-4ad7-ad8d-e93041ac575f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760520363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1760520363
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2008330212
Short name T797
Test name
Test status
Simulation time 307005017 ps
CPU time 1.25 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 02:59:55 PM PDT 24
Peak memory 201156 kb
Host smart-026fafae-a82f-4c22-a4ed-cefdc5acdc2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008330212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2008330212
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3237724225
Short name T58
Test name
Test status
Simulation time 4198438363 ps
CPU time 14.37 seconds
Started May 02 02:59:48 PM PDT 24
Finished May 02 03:00:04 PM PDT 24
Peak memory 201468 kb
Host smart-d4f339bc-5d63-42c3-bf8b-8c954470fb84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237724225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3237724225
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3455605422
Short name T70
Test name
Test status
Simulation time 449045979 ps
CPU time 2.27 seconds
Started May 02 02:59:54 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201532 kb
Host smart-33c21b97-34e1-4261-9de1-eab9bfc6bccb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455605422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3455605422
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1507629625
Short name T862
Test name
Test status
Simulation time 4254309073 ps
CPU time 6.59 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201512 kb
Host smart-e961bc4b-c7d9-4d70-aab0-e4a7107cb365
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507629625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1507629625
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4143483699
Short name T814
Test name
Test status
Simulation time 567433748 ps
CPU time 1.4 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201280 kb
Host smart-1f70b0fd-5d18-4ffb-be52-507119ed803e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143483699 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.4143483699
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1989213748
Short name T875
Test name
Test status
Simulation time 779582324 ps
CPU time 0.92 seconds
Started May 02 02:59:48 PM PDT 24
Finished May 02 02:59:51 PM PDT 24
Peak memory 201184 kb
Host smart-7e938346-48a1-4570-8704-3606ddadc3e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989213748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1989213748
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.1185378240
Short name T798
Test name
Test status
Simulation time 374345954 ps
CPU time 1.47 seconds
Started May 02 02:59:47 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 201212 kb
Host smart-116c1de9-3e94-4ed3-946b-7df14bdfe7a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185378240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.1185378240
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.864210186
Short name T115
Test name
Test status
Simulation time 5718433439 ps
CPU time 3.19 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201468 kb
Host smart-b02694d9-cfa2-42d2-bd40-566d6144b1f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864210186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.864210186
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4268784787
Short name T829
Test name
Test status
Simulation time 562723322 ps
CPU time 2.55 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201528 kb
Host smart-e9f979a4-a557-4995-8be6-8fda6f65601b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268784787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4268784787
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.115807208
Short name T831
Test name
Test status
Simulation time 8742175620 ps
CPU time 22.15 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 03:00:15 PM PDT 24
Peak memory 201512 kb
Host smart-a1d139aa-de83-48a7-8269-76366e047471
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115807208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.115807208
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.3457248640
Short name T840
Test name
Test status
Simulation time 549768837 ps
CPU time 1.11 seconds
Started May 02 02:59:49 PM PDT 24
Finished May 02 02:59:52 PM PDT 24
Peak memory 201316 kb
Host smart-709a888a-2e55-406a-b9bb-062b127867c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457248640 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.3457248640
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2034624793
Short name T902
Test name
Test status
Simulation time 368537550 ps
CPU time 1.58 seconds
Started May 02 02:59:49 PM PDT 24
Finished May 02 02:59:52 PM PDT 24
Peak memory 201212 kb
Host smart-ac999f2e-d3c2-4c1a-a89c-e0fbc2244e58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034624793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2034624793
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2234154928
Short name T796
Test name
Test status
Simulation time 481184496 ps
CPU time 1.76 seconds
Started May 02 02:59:51 PM PDT 24
Finished May 02 02:59:54 PM PDT 24
Peak memory 201216 kb
Host smart-1fa6c410-33a6-415b-a305-d69465f692aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234154928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2234154928
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1633714025
Short name T832
Test name
Test status
Simulation time 4096162199 ps
CPU time 9.94 seconds
Started May 02 02:59:54 PM PDT 24
Finished May 02 03:00:05 PM PDT 24
Peak memory 201556 kb
Host smart-48bb3f70-fec3-4719-925a-a45593b34169
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633714025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1633714025
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2803234753
Short name T846
Test name
Test status
Simulation time 982876128 ps
CPU time 2.48 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 03:00:01 PM PDT 24
Peak memory 201516 kb
Host smart-e074b9dd-06de-4414-9c84-997c96e7979e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803234753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2803234753
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.1718668105
Short name T86
Test name
Test status
Simulation time 8652569997 ps
CPU time 22.38 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 03:00:17 PM PDT 24
Peak memory 201356 kb
Host smart-e476cdd2-5aed-4d33-b793-8cc48c154fc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718668105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.1718668105
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.492092241
Short name T813
Test name
Test status
Simulation time 552433479 ps
CPU time 1.6 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 209668 kb
Host smart-244b75fd-0285-47d5-8dd9-361567d2d1a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492092241 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.492092241
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2474008472
Short name T114
Test name
Test status
Simulation time 331879744 ps
CPU time 0.94 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201200 kb
Host smart-ef6ef630-bc1f-44f2-9ea2-bbc6db553ba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474008472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2474008472
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1991727776
Short name T809
Test name
Test status
Simulation time 351993460 ps
CPU time 1.11 seconds
Started May 02 02:59:52 PM PDT 24
Finished May 02 02:59:54 PM PDT 24
Peak memory 201220 kb
Host smart-3b80b87d-4ab0-45d9-9c00-8fdabe70a6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991727776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1991727776
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3458412441
Short name T854
Test name
Test status
Simulation time 5258157003 ps
CPU time 17.89 seconds
Started May 02 02:59:48 PM PDT 24
Finished May 02 03:00:08 PM PDT 24
Peak memory 201484 kb
Host smart-6fce9f77-6ada-4816-a7c8-73dceb0f8221
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458412441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3458412441
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2336415886
Short name T850
Test name
Test status
Simulation time 420217589 ps
CPU time 2.36 seconds
Started May 02 02:59:53 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 210768 kb
Host smart-821e267a-19e6-4165-b726-98b890356fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336415886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2336415886
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1301402649
Short name T317
Test name
Test status
Simulation time 8013405363 ps
CPU time 17 seconds
Started May 02 02:59:51 PM PDT 24
Finished May 02 03:00:08 PM PDT 24
Peak memory 201492 kb
Host smart-74a2233c-9b90-4028-8b56-e14d23cb2b95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301402649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1301402649
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.4107733956
Short name T917
Test name
Test status
Simulation time 518364686 ps
CPU time 1.07 seconds
Started May 02 02:59:54 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201288 kb
Host smart-2864bd00-f984-41e5-af88-41418f34b21e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107733956 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.4107733956
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.373997555
Short name T100
Test name
Test status
Simulation time 541332236 ps
CPU time 1.09 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201224 kb
Host smart-86684057-03a9-4419-8227-191ac8cbfc05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373997555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.373997555
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1524561481
Short name T828
Test name
Test status
Simulation time 480374764 ps
CPU time 1.01 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201244 kb
Host smart-5f3aa682-984c-40d1-9353-14ef876ca804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524561481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1524561481
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1152594318
Short name T906
Test name
Test status
Simulation time 4631043774 ps
CPU time 11.7 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 03:00:09 PM PDT 24
Peak memory 201428 kb
Host smart-97ac0784-a7d2-425c-8ede-6de204d1b885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152594318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1152594318
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.861327191
Short name T896
Test name
Test status
Simulation time 432437565 ps
CPU time 2.67 seconds
Started May 02 02:59:54 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201448 kb
Host smart-b4346977-0073-4f80-9b93-a80b53af07b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861327191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.861327191
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2887998403
Short name T316
Test name
Test status
Simulation time 8627785087 ps
CPU time 21.27 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 03:00:19 PM PDT 24
Peak memory 201496 kb
Host smart-803b607f-eeae-491e-ab68-b6519e08fe7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887998403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2887998403
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1117009520
Short name T838
Test name
Test status
Simulation time 549628210 ps
CPU time 1.11 seconds
Started May 02 02:59:59 PM PDT 24
Finished May 02 03:00:01 PM PDT 24
Peak memory 201272 kb
Host smart-277dccfa-0b86-4b33-a8d9-ac8bf205480d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117009520 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1117009520
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2870946941
Short name T865
Test name
Test status
Simulation time 546128574 ps
CPU time 1.15 seconds
Started May 02 03:00:00 PM PDT 24
Finished May 02 03:00:02 PM PDT 24
Peak memory 201200 kb
Host smart-2140985f-d7d7-4fa7-b6e9-d4aa98de8753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870946941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2870946941
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3448420382
Short name T801
Test name
Test status
Simulation time 345422547 ps
CPU time 0.8 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201216 kb
Host smart-092102f2-6beb-488b-a0e4-0fe951f2118e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448420382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3448420382
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1649379940
Short name T860
Test name
Test status
Simulation time 1853795589 ps
CPU time 1.79 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201244 kb
Host smart-b05f1236-97b3-462c-8b7b-13fca7ff3ae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649379940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1649379940
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1902572537
Short name T68
Test name
Test status
Simulation time 419613382 ps
CPU time 1.8 seconds
Started May 02 02:59:58 PM PDT 24
Finished May 02 03:00:02 PM PDT 24
Peak memory 217228 kb
Host smart-81d0c14e-de40-43af-b098-76f8e03efd06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902572537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1902572537
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.565389131
Short name T62
Test name
Test status
Simulation time 4288890586 ps
CPU time 6.23 seconds
Started May 02 02:59:54 PM PDT 24
Finished May 02 03:00:01 PM PDT 24
Peak memory 201524 kb
Host smart-9ad91d2b-7fc0-47a4-91ce-cfedfdfe5c82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565389131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.565389131
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3656717791
Short name T104
Test name
Test status
Simulation time 771629098 ps
CPU time 4.16 seconds
Started May 02 02:59:40 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201428 kb
Host smart-953a85df-7591-4bef-8786-38aaf73944b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656717791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3656717791
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3469388322
Short name T60
Test name
Test status
Simulation time 26038192731 ps
CPU time 86.85 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 03:01:13 PM PDT 24
Peak memory 201488 kb
Host smart-7f9916ed-57fa-4c17-9bbb-bf3f0eb52fa5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469388322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3469388322
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2103583155
Short name T803
Test name
Test status
Simulation time 803340319 ps
CPU time 1.17 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:45 PM PDT 24
Peak memory 201180 kb
Host smart-b95cf3ab-b314-4528-b8a1-d865e2b9ac24
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103583155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2103583155
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.150825439
Short name T881
Test name
Test status
Simulation time 415598640 ps
CPU time 1.75 seconds
Started May 02 02:59:40 PM PDT 24
Finished May 02 02:59:44 PM PDT 24
Peak memory 201220 kb
Host smart-367ef04f-2fc7-4a6e-8ba6-a625b7fccfdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150825439 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.150825439
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3666256830
Short name T108
Test name
Test status
Simulation time 459825294 ps
CPU time 0.96 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201188 kb
Host smart-03474bd6-0ea0-47b9-b0b2-007992332fa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666256830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3666256830
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.507437284
Short name T823
Test name
Test status
Simulation time 626071672 ps
CPU time 0.72 seconds
Started May 02 02:59:40 PM PDT 24
Finished May 02 02:59:43 PM PDT 24
Peak memory 201216 kb
Host smart-e6ecaf0b-7d48-4d86-8fe3-0caf1f8eccfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507437284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.507437284
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2595522524
Short name T59
Test name
Test status
Simulation time 2107553172 ps
CPU time 3.3 seconds
Started May 02 02:59:39 PM PDT 24
Finished May 02 02:59:43 PM PDT 24
Peak memory 201200 kb
Host smart-84ed204f-8b79-4b74-bf28-f69b4c82638c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595522524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2595522524
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1323853289
Short name T919
Test name
Test status
Simulation time 378962708 ps
CPU time 1.29 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201504 kb
Host smart-7906d097-4f15-4400-a8f7-dc191b14f8f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323853289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1323853289
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2390277545
Short name T77
Test name
Test status
Simulation time 8132168453 ps
CPU time 18.98 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 03:00:05 PM PDT 24
Peak memory 201464 kb
Host smart-acae7063-5041-4226-bd99-afc0d28f9834
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390277545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2390277545
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3567325852
Short name T837
Test name
Test status
Simulation time 312083166 ps
CPU time 1.02 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201176 kb
Host smart-c6f9db75-7ec9-4a6f-9c74-3fc33cdab8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567325852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3567325852
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1295620072
Short name T834
Test name
Test status
Simulation time 529226349 ps
CPU time 1.87 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201184 kb
Host smart-29a2f785-7dc7-48cc-9f72-4ff5d69a3c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295620072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1295620072
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2219739760
Short name T866
Test name
Test status
Simulation time 384244919 ps
CPU time 1.64 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201220 kb
Host smart-f71e9794-f03c-48ed-9055-5f0907c1a803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219739760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2219739760
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.970916299
Short name T810
Test name
Test status
Simulation time 426122015 ps
CPU time 1.66 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201220 kb
Host smart-28170017-77b9-4f4c-bd9b-858a9ed09d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970916299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.970916299
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3903610900
Short name T889
Test name
Test status
Simulation time 467217807 ps
CPU time 1.19 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201216 kb
Host smart-1bcea210-d506-494e-a976-f11dc474e324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903610900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3903610900
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.245976654
Short name T908
Test name
Test status
Simulation time 384114496 ps
CPU time 1.53 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201204 kb
Host smart-0c55c8b5-c917-4f8b-a2f4-b9e40e5d9cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245976654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.245976654
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.829919008
Short name T856
Test name
Test status
Simulation time 562565699 ps
CPU time 0.89 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201204 kb
Host smart-4a197836-a128-49e5-a2c9-93e1445f0eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829919008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.829919008
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1279601271
Short name T800
Test name
Test status
Simulation time 341189797 ps
CPU time 0.86 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201164 kb
Host smart-302013b8-eb10-40aa-b8bb-75506e167c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279601271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1279601271
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2129073132
Short name T799
Test name
Test status
Simulation time 417644829 ps
CPU time 0.85 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201220 kb
Host smart-1fc36a3f-4350-4764-b357-844cbbb8cb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129073132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2129073132
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1628656354
Short name T841
Test name
Test status
Simulation time 362968323 ps
CPU time 0.83 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201180 kb
Host smart-07a7efae-d527-4434-a22a-80d80cb5bd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628656354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1628656354
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.365278171
Short name T106
Test name
Test status
Simulation time 453466191 ps
CPU time 1.9 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201424 kb
Host smart-703dfb19-0510-470a-9213-a789f8b4d8de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365278171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.365278171
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.84353416
Short name T844
Test name
Test status
Simulation time 26669952510 ps
CPU time 60.84 seconds
Started May 02 02:59:47 PM PDT 24
Finished May 02 03:00:50 PM PDT 24
Peak memory 201460 kb
Host smart-81032fde-a06b-4494-b2f8-fa6b191c2e16
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84353416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_ba
sh.84353416
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1656027377
Short name T110
Test name
Test status
Simulation time 1214813597 ps
CPU time 3.47 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 02:59:49 PM PDT 24
Peak memory 201228 kb
Host smart-e10d80f8-8a45-4ba0-835e-7de0d921b76f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656027377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1656027377
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.955176710
Short name T907
Test name
Test status
Simulation time 617241688 ps
CPU time 1.09 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:45 PM PDT 24
Peak memory 201280 kb
Host smart-97e0e1f7-7d15-42d0-b260-ae12ccdc831f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955176710 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.955176710
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2276474940
Short name T897
Test name
Test status
Simulation time 326870647 ps
CPU time 1.52 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201248 kb
Host smart-d64d9133-43c0-470f-9d20-8dec97e8abf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276474940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2276474940
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3537796226
Short name T891
Test name
Test status
Simulation time 318603461 ps
CPU time 1.35 seconds
Started May 02 02:59:39 PM PDT 24
Finished May 02 02:59:43 PM PDT 24
Peak memory 201204 kb
Host smart-3e5d4015-f685-4956-a62a-f0e11655dc7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537796226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3537796226
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4206364346
Short name T916
Test name
Test status
Simulation time 3818134247 ps
CPU time 9.87 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:54 PM PDT 24
Peak memory 201472 kb
Host smart-1fa04b7c-162d-415c-bc57-d9891abf8965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206364346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4206364346
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.3094886454
Short name T893
Test name
Test status
Simulation time 412914375 ps
CPU time 1.47 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:45 PM PDT 24
Peak memory 201480 kb
Host smart-7631119e-c871-43af-8f37-87cb1774a3ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094886454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.3094886454
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1490174353
Short name T913
Test name
Test status
Simulation time 4353538621 ps
CPU time 6.72 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 02:59:53 PM PDT 24
Peak memory 201488 kb
Host smart-9659cb1b-1d58-4d25-b2e8-27297c650dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490174353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1490174353
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.2713391248
Short name T792
Test name
Test status
Simulation time 449408923 ps
CPU time 0.86 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:58 PM PDT 24
Peak memory 201168 kb
Host smart-db45b33b-0199-4d4e-b665-b3c90f0e5809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713391248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.2713391248
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3833377756
Short name T811
Test name
Test status
Simulation time 303552298 ps
CPU time 1.04 seconds
Started May 02 03:00:00 PM PDT 24
Finished May 02 03:00:02 PM PDT 24
Peak memory 201220 kb
Host smart-05486795-2659-4c47-9c2c-f43830c258e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833377756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3833377756
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.31569557
Short name T802
Test name
Test status
Simulation time 477728114 ps
CPU time 1.82 seconds
Started May 02 03:00:00 PM PDT 24
Finished May 02 03:00:03 PM PDT 24
Peak memory 201220 kb
Host smart-8f20b456-0dde-4b64-90d5-2f0636a69737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31569557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.31569557
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3195185728
Short name T827
Test name
Test status
Simulation time 502045869 ps
CPU time 1.25 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201196 kb
Host smart-0d2c2e86-9a48-47f6-8957-0fdad41c32ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195185728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3195185728
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2878456082
Short name T869
Test name
Test status
Simulation time 481500550 ps
CPU time 1.01 seconds
Started May 02 03:00:00 PM PDT 24
Finished May 02 03:00:02 PM PDT 24
Peak memory 201220 kb
Host smart-d743a7db-87d2-4e6f-aafc-a0664e9d5a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878456082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2878456082
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3017198433
Short name T880
Test name
Test status
Simulation time 427009625 ps
CPU time 1.54 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201244 kb
Host smart-f8bc1dfa-9ed0-4761-9c3b-fc2855877744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017198433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3017198433
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2369514432
Short name T903
Test name
Test status
Simulation time 519954006 ps
CPU time 1.89 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201212 kb
Host smart-8af216b0-02e9-4478-a225-228eaf0a40f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369514432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2369514432
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3460725538
Short name T911
Test name
Test status
Simulation time 365097695 ps
CPU time 0.72 seconds
Started May 02 02:59:54 PM PDT 24
Finished May 02 02:59:56 PM PDT 24
Peak memory 201176 kb
Host smart-edb38590-ee34-47d7-a59a-85a7456a24bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460725538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3460725538
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3058331895
Short name T892
Test name
Test status
Simulation time 534098135 ps
CPU time 0.98 seconds
Started May 02 02:59:56 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201248 kb
Host smart-d8a84735-1ead-4a27-9a0c-bb079e0b5c12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058331895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3058331895
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.163670463
Short name T900
Test name
Test status
Simulation time 424432960 ps
CPU time 0.89 seconds
Started May 02 02:59:55 PM PDT 24
Finished May 02 02:59:57 PM PDT 24
Peak memory 201228 kb
Host smart-9db4428a-da10-4ac6-957a-9bf895d1e041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163670463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.163670463
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3942680255
Short name T870
Test name
Test status
Simulation time 1074856269 ps
CPU time 3.08 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201360 kb
Host smart-0dc3d74d-a6f6-419c-990d-8d6ab39f94d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942680255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3942680255
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1767252476
Short name T888
Test name
Test status
Simulation time 53199008857 ps
CPU time 31.9 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 03:00:16 PM PDT 24
Peak memory 201468 kb
Host smart-bc2eb054-28cf-4038-a6e9-420371cda474
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767252476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1767252476
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.704309128
Short name T858
Test name
Test status
Simulation time 930710977 ps
CPU time 0.91 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201212 kb
Host smart-4e0b75fe-10dc-44dc-b5f6-755a94808a2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704309128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.704309128
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.284235184
Short name T863
Test name
Test status
Simulation time 590737354 ps
CPU time 1.27 seconds
Started May 02 02:59:40 PM PDT 24
Finished May 02 02:59:43 PM PDT 24
Peak memory 201200 kb
Host smart-b8ec2dd7-c5f5-485c-a6db-961f94feda6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284235184 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.284235184
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1664395342
Short name T111
Test name
Test status
Simulation time 537875477 ps
CPU time 1.1 seconds
Started May 02 02:59:40 PM PDT 24
Finished May 02 02:59:44 PM PDT 24
Peak memory 201232 kb
Host smart-e334935e-496e-4fa3-8fe6-226ad17b12c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664395342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1664395342
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2150707107
Short name T848
Test name
Test status
Simulation time 320004115 ps
CPU time 1.25 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201208 kb
Host smart-73e596e7-7f73-4ddc-b70b-8635554c1c29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150707107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2150707107
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2301952709
Short name T820
Test name
Test status
Simulation time 2381604623 ps
CPU time 4.58 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 201340 kb
Host smart-2f9716e6-390e-41c8-a39b-08e773ddd4f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301952709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2301952709
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.3594888101
Short name T879
Test name
Test status
Simulation time 541753041 ps
CPU time 1.94 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:45 PM PDT 24
Peak memory 201452 kb
Host smart-5ec5b4e9-c6e3-4350-a68f-299d48bae431
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594888101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.3594888101
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3579076402
Short name T76
Test name
Test status
Simulation time 8548839090 ps
CPU time 17.69 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 03:00:01 PM PDT 24
Peak memory 201496 kb
Host smart-82cd0f5c-7529-4f77-b6fa-6ce3f508cbe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579076402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3579076402
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.353842289
Short name T890
Test name
Test status
Simulation time 424358752 ps
CPU time 1.12 seconds
Started May 02 02:59:57 PM PDT 24
Finished May 02 03:00:00 PM PDT 24
Peak memory 201196 kb
Host smart-5c9ad4b3-8e68-458b-aa55-371348fc3f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353842289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.353842289
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2189159888
Short name T843
Test name
Test status
Simulation time 404988899 ps
CPU time 1.56 seconds
Started May 02 03:00:05 PM PDT 24
Finished May 02 03:00:10 PM PDT 24
Peak memory 201224 kb
Host smart-9941c153-4c3c-4d3b-8d7e-cdaf06c53a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189159888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2189159888
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3622555550
Short name T859
Test name
Test status
Simulation time 420567119 ps
CPU time 0.87 seconds
Started May 02 03:00:03 PM PDT 24
Finished May 02 03:00:05 PM PDT 24
Peak memory 201240 kb
Host smart-bc5dfa3c-3285-4d71-95e2-6044e4aeb3b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622555550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3622555550
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.3747652232
Short name T795
Test name
Test status
Simulation time 381576677 ps
CPU time 0.78 seconds
Started May 02 03:00:04 PM PDT 24
Finished May 02 03:00:07 PM PDT 24
Peak memory 201228 kb
Host smart-75d8d8be-3f57-4009-a795-b531a179ff54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747652232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.3747652232
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2192045542
Short name T794
Test name
Test status
Simulation time 320474088 ps
CPU time 1.37 seconds
Started May 02 03:00:03 PM PDT 24
Finished May 02 03:00:06 PM PDT 24
Peak memory 201200 kb
Host smart-414b4aaf-014b-456c-9f23-8a074a8f6b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192045542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2192045542
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3036410161
Short name T847
Test name
Test status
Simulation time 329061180 ps
CPU time 0.76 seconds
Started May 02 03:00:08 PM PDT 24
Finished May 02 03:00:11 PM PDT 24
Peak memory 201216 kb
Host smart-42508d43-6c25-4905-b0c7-8dcb58be2fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036410161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3036410161
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3531044670
Short name T825
Test name
Test status
Simulation time 304113726 ps
CPU time 1.32 seconds
Started May 02 03:00:05 PM PDT 24
Finished May 02 03:00:09 PM PDT 24
Peak memory 201204 kb
Host smart-39b93d3a-4625-436b-b905-d36e05e5656b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531044670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3531044670
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1061901506
Short name T898
Test name
Test status
Simulation time 371180566 ps
CPU time 0.83 seconds
Started May 02 03:00:04 PM PDT 24
Finished May 02 03:00:07 PM PDT 24
Peak memory 201240 kb
Host smart-e15ace5c-6209-4697-bc01-136cb60796a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061901506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1061901506
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2063420877
Short name T877
Test name
Test status
Simulation time 355149774 ps
CPU time 0.86 seconds
Started May 02 03:00:03 PM PDT 24
Finished May 02 03:00:06 PM PDT 24
Peak memory 201228 kb
Host smart-cf667943-4c27-4657-8c5e-b844ae32c839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063420877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2063420877
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2427073640
Short name T884
Test name
Test status
Simulation time 523177373 ps
CPU time 1.25 seconds
Started May 02 03:00:08 PM PDT 24
Finished May 02 03:00:11 PM PDT 24
Peak memory 201220 kb
Host smart-014f8967-60c0-4ba7-8eff-249448022dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427073640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2427073640
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1498306488
Short name T912
Test name
Test status
Simulation time 701977166 ps
CPU time 1.38 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201348 kb
Host smart-32c08133-9b5f-47c0-8697-182afb195972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498306488 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1498306488
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1203211982
Short name T899
Test name
Test status
Simulation time 402828303 ps
CPU time 0.98 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201220 kb
Host smart-f9c068e8-2a9d-4051-8fdf-b54005490898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203211982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1203211982
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.643080943
Short name T817
Test name
Test status
Simulation time 522000352 ps
CPU time 1 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201176 kb
Host smart-022c8ed5-aeb4-4622-b020-4cd0db67c422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643080943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.643080943
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.447854271
Short name T887
Test name
Test status
Simulation time 1986285038 ps
CPU time 1.22 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201184 kb
Host smart-0fd3c428-113c-4581-8a53-c7fad378f042
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447854271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.447854271
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1618674262
Short name T72
Test name
Test status
Simulation time 378663036 ps
CPU time 2.35 seconds
Started May 02 02:59:45 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 201280 kb
Host smart-f7c4f36e-0d3f-4f54-91c2-9ec13e4fc09a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618674262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1618674262
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.4162320120
Short name T822
Test name
Test status
Simulation time 8084273292 ps
CPU time 21.4 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 03:00:07 PM PDT 24
Peak memory 201488 kb
Host smart-1a19bdfb-2119-497b-9f00-47a299caa2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162320120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.4162320120
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2977862224
Short name T871
Test name
Test status
Simulation time 517290213 ps
CPU time 1.38 seconds
Started May 02 02:59:50 PM PDT 24
Finished May 02 02:59:53 PM PDT 24
Peak memory 201280 kb
Host smart-c2a9c3fd-a4b5-4132-ade2-acb728752653
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977862224 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2977862224
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.601870020
Short name T914
Test name
Test status
Simulation time 449532471 ps
CPU time 1.9 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201200 kb
Host smart-7d284e8c-5619-4aba-9b5b-cbd777045f38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601870020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.601870020
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1618210751
Short name T878
Test name
Test status
Simulation time 558598933 ps
CPU time 0.82 seconds
Started May 02 02:59:40 PM PDT 24
Finished May 02 02:59:43 PM PDT 24
Peak memory 201224 kb
Host smart-8bb9c4da-6b88-4296-90d4-92984b2d954c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618210751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1618210751
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2920034810
Short name T824
Test name
Test status
Simulation time 2606190725 ps
CPU time 2.4 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201276 kb
Host smart-5d82f01a-f2ea-428a-95d8-483317fc65c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920034810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2920034810
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2343789687
Short name T805
Test name
Test status
Simulation time 895609563 ps
CPU time 2.76 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201504 kb
Host smart-04dfeb46-eb32-4ac9-9f58-f50bff0100b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343789687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2343789687
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.3369010063
Short name T826
Test name
Test status
Simulation time 4083169512 ps
CPU time 11.35 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:55 PM PDT 24
Peak memory 201512 kb
Host smart-5d46852f-86da-42b2-98d8-2d3902fae622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369010063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.3369010063
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3032069491
Short name T861
Test name
Test status
Simulation time 694143167 ps
CPU time 1.08 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:46 PM PDT 24
Peak memory 201292 kb
Host smart-dda0bbb2-3536-4d00-ba81-88d0b56fc46c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032069491 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3032069491
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.470536656
Short name T105
Test name
Test status
Simulation time 426442601 ps
CPU time 0.99 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201192 kb
Host smart-b5266579-d02f-48fc-8282-34aecceb30a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470536656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.470536656
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1482579860
Short name T918
Test name
Test status
Simulation time 454745335 ps
CPU time 1.57 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201232 kb
Host smart-998588c3-10a5-46e3-a34e-8dcca70789ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482579860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1482579860
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3935128818
Short name T873
Test name
Test status
Simulation time 4675480634 ps
CPU time 14.61 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:59 PM PDT 24
Peak memory 201448 kb
Host smart-5c896595-58f4-44cc-a103-23f821e044ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935128818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3935128818
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1570860572
Short name T69
Test name
Test status
Simulation time 471689579 ps
CPU time 3.17 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 210800 kb
Host smart-055c26eb-357c-474b-8728-4461bc5325d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570860572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1570860572
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3804964018
Short name T78
Test name
Test status
Simulation time 8440912364 ps
CPU time 7.44 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:54 PM PDT 24
Peak memory 201516 kb
Host smart-6a03f2e4-c20d-426c-824b-44a83460fccb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804964018 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3804964018
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2061818371
Short name T842
Test name
Test status
Simulation time 532305956 ps
CPU time 1.15 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201348 kb
Host smart-f79b354c-8c1b-4875-be16-f1c65dca3a86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061818371 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2061818371
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1012013802
Short name T112
Test name
Test status
Simulation time 542953158 ps
CPU time 2.09 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:49 PM PDT 24
Peak memory 201260 kb
Host smart-358e456c-8478-47e9-8bae-64f89ad9e2b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012013802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1012013802
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1794839192
Short name T874
Test name
Test status
Simulation time 341685125 ps
CPU time 0.74 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:45 PM PDT 24
Peak memory 201248 kb
Host smart-6d416d6c-7ffa-4a13-b00b-29e5cb8ec917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794839192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1794839192
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.936307528
Short name T833
Test name
Test status
Simulation time 2769894610 ps
CPU time 4.17 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 201244 kb
Host smart-0a434a4b-a574-4c46-ad2d-4e292c645d66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936307528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.936307528
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.374736293
Short name T868
Test name
Test status
Simulation time 600383241 ps
CPU time 2.35 seconds
Started May 02 02:59:42 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 217200 kb
Host smart-8c868437-675d-429a-9d2b-41bfd547312e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374736293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.374736293
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2302611031
Short name T835
Test name
Test status
Simulation time 4513886512 ps
CPU time 4.28 seconds
Started May 02 02:59:46 PM PDT 24
Finished May 02 02:59:52 PM PDT 24
Peak memory 201432 kb
Host smart-5cac79b7-7996-45de-b903-425546042caa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302611031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2302611031
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.518202680
Short name T895
Test name
Test status
Simulation time 459814906 ps
CPU time 1.8 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:49 PM PDT 24
Peak memory 201248 kb
Host smart-9cb93d58-f5bf-4f2f-820d-dd6aecfc7ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518202680 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.518202680
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3235785965
Short name T901
Test name
Test status
Simulation time 550872312 ps
CPU time 2.21 seconds
Started May 02 02:59:45 PM PDT 24
Finished May 02 02:59:50 PM PDT 24
Peak memory 200988 kb
Host smart-bd9c1dcc-c0ed-4885-b385-4625dd425b08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235785965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3235785965
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3069280313
Short name T819
Test name
Test status
Simulation time 345477908 ps
CPU time 0.94 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 02:59:47 PM PDT 24
Peak memory 201204 kb
Host smart-d27a378c-4e5b-4769-be63-0f20d839c379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069280313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3069280313
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4105587885
Short name T821
Test name
Test status
Simulation time 2611992027 ps
CPU time 12.93 seconds
Started May 02 02:59:41 PM PDT 24
Finished May 02 02:59:56 PM PDT 24
Peak memory 201308 kb
Host smart-f2fdb897-6f07-4a1a-bd2f-958d743627d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105587885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4105587885
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2160471014
Short name T806
Test name
Test status
Simulation time 764078327 ps
CPU time 2.28 seconds
Started May 02 02:59:43 PM PDT 24
Finished May 02 02:59:48 PM PDT 24
Peak memory 201504 kb
Host smart-57c99f4e-8863-4313-8511-9463f0b60289
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160471014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2160471014
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.1203770433
Short name T853
Test name
Test status
Simulation time 8203060535 ps
CPU time 7.77 seconds
Started May 02 02:59:44 PM PDT 24
Finished May 02 02:59:55 PM PDT 24
Peak memory 201468 kb
Host smart-1df480f6-7449-4a80-99a2-1e3051158b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203770433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.1203770433
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.228239715
Short name T547
Test name
Test status
Simulation time 597965908541 ps
CPU time 357.78 seconds
Started May 02 03:59:57 PM PDT 24
Finished May 02 04:05:55 PM PDT 24
Peak memory 202396 kb
Host smart-981386d5-58c4-44fd-a9f1-d9cf75f7b343
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228239715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.228239715
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.237637918
Short name T284
Test name
Test status
Simulation time 497530738130 ps
CPU time 1121.65 seconds
Started May 02 03:59:59 PM PDT 24
Finished May 02 04:18:41 PM PDT 24
Peak memory 202324 kb
Host smart-e937298d-d9a2-4a86-9618-1c861d2ada88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237637918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.237637918
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.37654993
Short name T219
Test name
Test status
Simulation time 165947105737 ps
CPU time 422.5 seconds
Started May 02 03:59:59 PM PDT 24
Finished May 02 04:07:02 PM PDT 24
Peak memory 202332 kb
Host smart-2ac4e2c0-dd5d-4b16-b962-140b36d1cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37654993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.37654993
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1698417097
Short name T361
Test name
Test status
Simulation time 166872907621 ps
CPU time 190.85 seconds
Started May 02 03:59:58 PM PDT 24
Finished May 02 04:03:09 PM PDT 24
Peak memory 202248 kb
Host smart-e4ee50c2-4011-4861-bf6d-2b227e276704
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698417097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1698417097
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.282516929
Short name T137
Test name
Test status
Simulation time 490193849180 ps
CPU time 1002.12 seconds
Started May 02 03:59:55 PM PDT 24
Finished May 02 04:16:38 PM PDT 24
Peak memory 202404 kb
Host smart-ce0f5f3c-4f33-4e75-822c-3f55a4c59bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282516929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.282516929
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2996278672
Short name T679
Test name
Test status
Simulation time 480692554112 ps
CPU time 1205.29 seconds
Started May 02 03:59:59 PM PDT 24
Finished May 02 04:20:05 PM PDT 24
Peak memory 202276 kb
Host smart-e54aa245-b044-4877-8d39-d69b93a2c62a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996278672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2996278672
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1785156652
Short name T226
Test name
Test status
Simulation time 559068776802 ps
CPU time 325.71 seconds
Started May 02 03:59:55 PM PDT 24
Finished May 02 04:05:21 PM PDT 24
Peak memory 202292 kb
Host smart-c4a8d48b-894e-48a9-adaf-dfeab1bef266
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785156652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1785156652
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4129039755
Short name T474
Test name
Test status
Simulation time 203705259657 ps
CPU time 247.44 seconds
Started May 02 03:59:57 PM PDT 24
Finished May 02 04:04:05 PM PDT 24
Peak memory 202308 kb
Host smart-b50a696f-0438-4cc8-8d2e-cbb116f7d083
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129039755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4129039755
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3254351115
Short name T626
Test name
Test status
Simulation time 32516621033 ps
CPU time 38.03 seconds
Started May 02 04:00:04 PM PDT 24
Finished May 02 04:00:43 PM PDT 24
Peak memory 202172 kb
Host smart-b9b5f0db-e89f-4e0d-a634-7b0ae8f0e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254351115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3254351115
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1023777465
Short name T445
Test name
Test status
Simulation time 4142741912 ps
CPU time 11.01 seconds
Started May 02 03:59:57 PM PDT 24
Finished May 02 04:00:08 PM PDT 24
Peak memory 202136 kb
Host smart-c7fd7c00-82bd-40a4-9f5b-0f18272bcf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023777465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1023777465
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1540759430
Short name T658
Test name
Test status
Simulation time 6150561337 ps
CPU time 14.68 seconds
Started May 02 03:59:58 PM PDT 24
Finished May 02 04:00:13 PM PDT 24
Peak memory 202096 kb
Host smart-53985042-a99d-4ff6-b71e-6d4dad68f926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540759430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1540759430
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3262072627
Short name T591
Test name
Test status
Simulation time 503802752 ps
CPU time 0.73 seconds
Started May 02 04:00:12 PM PDT 24
Finished May 02 04:00:13 PM PDT 24
Peak memory 202008 kb
Host smart-1142c4c8-e4db-44fe-8f63-60d7564af424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262072627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3262072627
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.3148662181
Short name T785
Test name
Test status
Simulation time 497616215684 ps
CPU time 987.88 seconds
Started May 02 04:00:11 PM PDT 24
Finished May 02 04:16:40 PM PDT 24
Peak memory 202376 kb
Host smart-ba718a3b-5083-4c4a-8cc3-2f76205f8c76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148662181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.3148662181
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3027618524
Short name T90
Test name
Test status
Simulation time 498877456125 ps
CPU time 313.85 seconds
Started May 02 04:00:11 PM PDT 24
Finished May 02 04:05:25 PM PDT 24
Peak memory 202404 kb
Host smart-546fcf1e-3b6b-418e-a1ff-d08c69f95ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027618524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3027618524
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.406987789
Short name T260
Test name
Test status
Simulation time 328669829769 ps
CPU time 204.23 seconds
Started May 02 04:00:03 PM PDT 24
Finished May 02 04:03:28 PM PDT 24
Peak memory 202288 kb
Host smart-4a6a73e0-dbf3-43fb-991c-adcef7759963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406987789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.406987789
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1894476883
Short name T339
Test name
Test status
Simulation time 325432730930 ps
CPU time 208.85 seconds
Started May 02 04:00:04 PM PDT 24
Finished May 02 04:03:33 PM PDT 24
Peak memory 202248 kb
Host smart-e7eb6cfe-507e-423a-8b72-1eb2cd2941df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894476883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1894476883
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.4070058034
Short name T161
Test name
Test status
Simulation time 163186669995 ps
CPU time 72.92 seconds
Started May 02 04:00:03 PM PDT 24
Finished May 02 04:01:17 PM PDT 24
Peak memory 202248 kb
Host smart-61094924-58b9-4fdd-94c5-329c4af6fea0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070058034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.4070058034
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3002994294
Short name T633
Test name
Test status
Simulation time 385311138981 ps
CPU time 218.07 seconds
Started May 02 04:00:04 PM PDT 24
Finished May 02 04:03:43 PM PDT 24
Peak memory 202304 kb
Host smart-88137e50-9f0a-4002-9ebd-113cee3ca2c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002994294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3002994294
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2722834345
Short name T450
Test name
Test status
Simulation time 611342584417 ps
CPU time 392.71 seconds
Started May 02 04:00:03 PM PDT 24
Finished May 02 04:06:36 PM PDT 24
Peak memory 202244 kb
Host smart-c012c9e7-37a5-4731-8ad0-1acaf4666ec4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722834345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2722834345
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.577785787
Short name T448
Test name
Test status
Simulation time 81304478065 ps
CPU time 282.67 seconds
Started May 02 04:00:11 PM PDT 24
Finished May 02 04:04:55 PM PDT 24
Peak memory 202680 kb
Host smart-5dfeb826-7304-4ce4-960e-0643b8520fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577785787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.577785787
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2633695838
Short name T413
Test name
Test status
Simulation time 39633390305 ps
CPU time 89.17 seconds
Started May 02 04:00:11 PM PDT 24
Finished May 02 04:01:41 PM PDT 24
Peak memory 202168 kb
Host smart-e39a9abe-0f90-4e9f-8d5f-759456a9e6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633695838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2633695838
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1814832268
Short name T443
Test name
Test status
Simulation time 3932755067 ps
CPU time 10.23 seconds
Started May 02 04:00:13 PM PDT 24
Finished May 02 04:00:24 PM PDT 24
Peak memory 202092 kb
Host smart-d1da224f-81ce-42b3-9a82-76d40addae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814832268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1814832268
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3017642469
Short name T65
Test name
Test status
Simulation time 4489893922 ps
CPU time 2.09 seconds
Started May 02 04:00:12 PM PDT 24
Finished May 02 04:00:14 PM PDT 24
Peak memory 217828 kb
Host smart-7b38cf92-dd96-4466-aacb-59b847f0ec40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017642469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3017642469
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2776494212
Short name T572
Test name
Test status
Simulation time 6052953934 ps
CPU time 15.09 seconds
Started May 02 04:00:04 PM PDT 24
Finished May 02 04:00:20 PM PDT 24
Peak memory 202140 kb
Host smart-c9502d9f-872d-4a41-9f51-ea983d4c1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776494212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2776494212
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1776880085
Short name T17
Test name
Test status
Simulation time 155024463950 ps
CPU time 205.56 seconds
Started May 02 04:00:11 PM PDT 24
Finished May 02 04:03:37 PM PDT 24
Peak memory 210644 kb
Host smart-067e7b36-c0af-44a0-9bfc-e62a4b949288
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776880085 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1776880085
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1326220180
Short name T670
Test name
Test status
Simulation time 376466507 ps
CPU time 1.51 seconds
Started May 02 04:02:01 PM PDT 24
Finished May 02 04:02:03 PM PDT 24
Peak memory 202000 kb
Host smart-82057e73-9cee-4b1e-9eb6-0edc570e22b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326220180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1326220180
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2707431208
Short name T597
Test name
Test status
Simulation time 551057248308 ps
CPU time 118.95 seconds
Started May 02 04:01:45 PM PDT 24
Finished May 02 04:03:45 PM PDT 24
Peak memory 202348 kb
Host smart-555fcea7-1329-46b2-b05f-a08c7ccd4462
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707431208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2707431208
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2321898061
Short name T262
Test name
Test status
Simulation time 332585686020 ps
CPU time 198.99 seconds
Started May 02 04:01:44 PM PDT 24
Finished May 02 04:05:03 PM PDT 24
Peak memory 202312 kb
Host smart-a10d567f-41b0-45ed-9d56-36d50cba1eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321898061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2321898061
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.222251800
Short name T688
Test name
Test status
Simulation time 159879867003 ps
CPU time 199.69 seconds
Started May 02 04:01:43 PM PDT 24
Finished May 02 04:05:04 PM PDT 24
Peak memory 202260 kb
Host smart-9145032e-6ef6-41fd-aa9b-f9567b8dcaa4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=222251800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrup
t_fixed.222251800
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.959131905
Short name T764
Test name
Test status
Simulation time 327330299161 ps
CPU time 742.3 seconds
Started May 02 04:01:38 PM PDT 24
Finished May 02 04:14:01 PM PDT 24
Peak memory 202428 kb
Host smart-646cd7a5-bfb1-45a9-9f38-6c3b7a8bda63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959131905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.959131905
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.4110349666
Short name T401
Test name
Test status
Simulation time 331485543608 ps
CPU time 224.6 seconds
Started May 02 04:01:45 PM PDT 24
Finished May 02 04:05:30 PM PDT 24
Peak memory 202220 kb
Host smart-8eb70f71-684c-46d5-89bc-4e5f40351e98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110349666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.4110349666
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.1448888265
Short name T585
Test name
Test status
Simulation time 178459692652 ps
CPU time 113.44 seconds
Started May 02 04:01:45 PM PDT 24
Finished May 02 04:03:39 PM PDT 24
Peak memory 202348 kb
Host smart-7f5bd44b-0afe-46d1-962f-e28c90da7cf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448888265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.1448888265
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3742070581
Short name T408
Test name
Test status
Simulation time 587370478904 ps
CPU time 735.56 seconds
Started May 02 04:01:45 PM PDT 24
Finished May 02 04:14:02 PM PDT 24
Peak memory 202268 kb
Host smart-cc257df7-5d47-494c-b169-a1c9fc50c763
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742070581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3742070581
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3510651072
Short name T748
Test name
Test status
Simulation time 78335429396 ps
CPU time 433.72 seconds
Started May 02 04:01:53 PM PDT 24
Finished May 02 04:09:08 PM PDT 24
Peak memory 202736 kb
Host smart-c4af5301-df8b-407e-9378-8e7aa113f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510651072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3510651072
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.708571122
Short name T144
Test name
Test status
Simulation time 32283756773 ps
CPU time 19.57 seconds
Started May 02 04:01:52 PM PDT 24
Finished May 02 04:02:12 PM PDT 24
Peak memory 202132 kb
Host smart-29aa1c36-e739-444c-8d74-3a458aff3acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708571122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.708571122
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.342564366
Short name T516
Test name
Test status
Simulation time 3146587346 ps
CPU time 8.28 seconds
Started May 02 04:01:53 PM PDT 24
Finished May 02 04:02:02 PM PDT 24
Peak memory 202136 kb
Host smart-e18f0d33-f8bb-4029-925a-b6ea16a3acf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342564366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.342564366
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2261164141
Short name T460
Test name
Test status
Simulation time 5816366394 ps
CPU time 7.19 seconds
Started May 02 04:01:37 PM PDT 24
Finished May 02 04:01:46 PM PDT 24
Peak memory 202088 kb
Host smart-688c2a6b-d669-499e-8a77-6b5cf995e876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261164141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2261164141
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1390356922
Short name T5
Test name
Test status
Simulation time 180030276821 ps
CPU time 463.13 seconds
Started May 02 04:01:52 PM PDT 24
Finished May 02 04:09:36 PM PDT 24
Peak memory 202316 kb
Host smart-32f53657-4387-42f5-9146-15ae87c91d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390356922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1390356922
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3295527403
Short name T614
Test name
Test status
Simulation time 21726107506 ps
CPU time 23.34 seconds
Started May 02 04:01:55 PM PDT 24
Finished May 02 04:02:19 PM PDT 24
Peak memory 210700 kb
Host smart-97cc03ba-b89e-449f-9c1b-4c613277e7ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295527403 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3295527403
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2894489939
Short name T383
Test name
Test status
Simulation time 342499489 ps
CPU time 0.97 seconds
Started May 02 04:02:20 PM PDT 24
Finished May 02 04:02:22 PM PDT 24
Peak memory 202020 kb
Host smart-a321a055-4ee7-48e5-98ab-938938048065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894489939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2894489939
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.976139434
Short name T315
Test name
Test status
Simulation time 331586629590 ps
CPU time 657.64 seconds
Started May 02 04:02:12 PM PDT 24
Finished May 02 04:13:10 PM PDT 24
Peak memory 202356 kb
Host smart-59504c97-0831-4c13-ad38-1b6326010d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976139434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.976139434
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3732859375
Short name T486
Test name
Test status
Simulation time 497589464406 ps
CPU time 328.42 seconds
Started May 02 04:02:07 PM PDT 24
Finished May 02 04:07:36 PM PDT 24
Peak memory 202280 kb
Host smart-7a17878f-2ec9-497d-9e01-714c455817c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732859375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3732859375
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3865481861
Short name T414
Test name
Test status
Simulation time 161275229392 ps
CPU time 359.8 seconds
Started May 02 04:02:07 PM PDT 24
Finished May 02 04:08:08 PM PDT 24
Peak memory 202244 kb
Host smart-1d936f56-4da5-4498-aea3-3882d9dcc07e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865481861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3865481861
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3401876204
Short name T581
Test name
Test status
Simulation time 491297022169 ps
CPU time 921.66 seconds
Started May 02 04:02:01 PM PDT 24
Finished May 02 04:17:23 PM PDT 24
Peak memory 202240 kb
Host smart-7f3743e3-f3b8-4876-ae34-7e67184ef899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401876204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3401876204
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.4250031726
Short name T347
Test name
Test status
Simulation time 332897905600 ps
CPU time 758.38 seconds
Started May 02 04:02:06 PM PDT 24
Finished May 02 04:14:45 PM PDT 24
Peak memory 202380 kb
Host smart-3b52518c-3655-481d-a71a-0ac5821ff2be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250031726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.4250031726
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1411012510
Short name T604
Test name
Test status
Simulation time 365211235892 ps
CPU time 398.68 seconds
Started May 02 04:02:08 PM PDT 24
Finished May 02 04:08:47 PM PDT 24
Peak memory 202312 kb
Host smart-95ebd910-5aa8-4991-a145-5b9e086069d0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411012510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1411012510
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2193387438
Short name T610
Test name
Test status
Simulation time 609701149571 ps
CPU time 157.73 seconds
Started May 02 04:02:06 PM PDT 24
Finished May 02 04:04:45 PM PDT 24
Peak memory 202288 kb
Host smart-705bc749-75ad-4190-982d-7fb288f1197f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193387438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2193387438
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3953616123
Short name T774
Test name
Test status
Simulation time 95623260719 ps
CPU time 463.02 seconds
Started May 02 04:02:17 PM PDT 24
Finished May 02 04:10:00 PM PDT 24
Peak memory 202668 kb
Host smart-7950211e-1fdc-4803-aa72-438cba9bce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953616123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3953616123
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.669745258
Short name T376
Test name
Test status
Simulation time 35440056647 ps
CPU time 86.76 seconds
Started May 02 04:02:12 PM PDT 24
Finished May 02 04:03:40 PM PDT 24
Peak memory 202112 kb
Host smart-1456ebf2-27d9-45cf-9a0c-6207499ec960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669745258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.669745258
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1485820274
Short name T758
Test name
Test status
Simulation time 3634507257 ps
CPU time 3.21 seconds
Started May 02 04:02:13 PM PDT 24
Finished May 02 04:02:17 PM PDT 24
Peak memory 202148 kb
Host smart-04eae775-f04a-4fac-8b32-b1e7c11249f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485820274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1485820274
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3191762087
Short name T8
Test name
Test status
Simulation time 5856604356 ps
CPU time 2.29 seconds
Started May 02 04:02:00 PM PDT 24
Finished May 02 04:02:03 PM PDT 24
Peak memory 202088 kb
Host smart-a165ae03-b44b-4a1b-b989-f661124392b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191762087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3191762087
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1559376337
Short name T471
Test name
Test status
Simulation time 86258128114 ps
CPU time 35.92 seconds
Started May 02 04:02:21 PM PDT 24
Finished May 02 04:02:57 PM PDT 24
Peak memory 211080 kb
Host smart-e959892c-c824-4dbb-9cd0-1fb95020870e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559376337 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1559376337
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3366993929
Short name T390
Test name
Test status
Simulation time 367465569 ps
CPU time 0.71 seconds
Started May 02 04:02:38 PM PDT 24
Finished May 02 04:02:39 PM PDT 24
Peak memory 201972 kb
Host smart-830c269b-1b76-4223-b2a9-cc72c7bce701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366993929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3366993929
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1909807144
Short name T85
Test name
Test status
Simulation time 351128500289 ps
CPU time 850.4 seconds
Started May 02 04:02:32 PM PDT 24
Finished May 02 04:16:43 PM PDT 24
Peak memory 202292 kb
Host smart-dee57fc8-8ca0-4beb-b7df-9ded18dc78c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909807144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1909807144
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.4266071616
Short name T767
Test name
Test status
Simulation time 493248372296 ps
CPU time 1260.89 seconds
Started May 02 04:02:26 PM PDT 24
Finished May 02 04:23:27 PM PDT 24
Peak memory 202296 kb
Host smart-2d9dee2c-500b-4d34-b0b2-473ff049f9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266071616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.4266071616
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2989447714
Short name T463
Test name
Test status
Simulation time 164535906051 ps
CPU time 193.87 seconds
Started May 02 04:02:26 PM PDT 24
Finished May 02 04:05:40 PM PDT 24
Peak memory 202300 kb
Host smart-f263c260-c302-4014-84b8-8a8eb48ae00a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989447714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2989447714
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4138559314
Short name T155
Test name
Test status
Simulation time 495781231884 ps
CPU time 339.4 seconds
Started May 02 04:02:20 PM PDT 24
Finished May 02 04:08:00 PM PDT 24
Peak memory 202388 kb
Host smart-4f073787-7b84-4f6f-afce-e1ece1157ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138559314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4138559314
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.796568858
Short name T509
Test name
Test status
Simulation time 493061712853 ps
CPU time 288.95 seconds
Started May 02 04:02:27 PM PDT 24
Finished May 02 04:07:17 PM PDT 24
Peak memory 202316 kb
Host smart-d6573371-921b-4789-a851-aea10534b02b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=796568858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.796568858
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3937062190
Short name T568
Test name
Test status
Simulation time 185076312796 ps
CPU time 111.43 seconds
Started May 02 04:02:28 PM PDT 24
Finished May 02 04:04:20 PM PDT 24
Peak memory 202332 kb
Host smart-841337a1-4117-43c7-ab68-799b7535cee8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937062190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3937062190
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.553771313
Short name T2
Test name
Test status
Simulation time 406204443349 ps
CPU time 253.17 seconds
Started May 02 04:02:26 PM PDT 24
Finished May 02 04:06:40 PM PDT 24
Peak memory 202292 kb
Host smart-a267685b-0f51-49ed-83f9-25330bc65706
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553771313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.553771313
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1844723193
Short name T179
Test name
Test status
Simulation time 133013232765 ps
CPU time 415.35 seconds
Started May 02 04:02:39 PM PDT 24
Finished May 02 04:09:35 PM PDT 24
Peak memory 202676 kb
Host smart-a48a3b13-523b-4e40-93aa-0488480f136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844723193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1844723193
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2249212032
Short name T599
Test name
Test status
Simulation time 25357543215 ps
CPU time 59.53 seconds
Started May 02 04:02:37 PM PDT 24
Finished May 02 04:03:37 PM PDT 24
Peak memory 202112 kb
Host smart-bf6f576b-5249-44e7-b690-8ca62858dcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249212032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2249212032
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2334500346
Short name T327
Test name
Test status
Simulation time 3698721321 ps
CPU time 8.65 seconds
Started May 02 04:02:37 PM PDT 24
Finished May 02 04:02:46 PM PDT 24
Peak memory 202100 kb
Host smart-510682b0-a3d3-4001-95f9-3cbda072e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334500346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2334500346
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2214517673
Short name T421
Test name
Test status
Simulation time 6036306747 ps
CPU time 4.02 seconds
Started May 02 04:02:19 PM PDT 24
Finished May 02 04:02:24 PM PDT 24
Peak memory 202120 kb
Host smart-8f032449-2d22-4144-9496-e3675d1dc255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214517673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2214517673
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.195396357
Short name T549
Test name
Test status
Simulation time 342015386807 ps
CPU time 198.84 seconds
Started May 02 04:02:39 PM PDT 24
Finished May 02 04:05:58 PM PDT 24
Peak memory 202352 kb
Host smart-16ce3ba8-1264-46a6-ac8f-184dc33fbe69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195396357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
195396357
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2396782604
Short name T79
Test name
Test status
Simulation time 493407064 ps
CPU time 0.92 seconds
Started May 02 04:02:59 PM PDT 24
Finished May 02 04:03:00 PM PDT 24
Peak memory 202052 kb
Host smart-008439d4-58cb-4c23-a852-da4e4d930f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396782604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2396782604
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2920056195
Short name T707
Test name
Test status
Simulation time 164766763546 ps
CPU time 193.88 seconds
Started May 02 04:02:51 PM PDT 24
Finished May 02 04:06:06 PM PDT 24
Peak memory 202380 kb
Host smart-523f83e4-6e38-4cc0-b12f-3d1cc6a79c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920056195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2920056195
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3445122318
Short name T121
Test name
Test status
Simulation time 161091928427 ps
CPU time 183.08 seconds
Started May 02 04:02:39 PM PDT 24
Finished May 02 04:05:43 PM PDT 24
Peak memory 202256 kb
Host smart-263fd40f-41e2-42e9-834e-9738ce9f10ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445122318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3445122318
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3138254909
Short name T455
Test name
Test status
Simulation time 330703621489 ps
CPU time 601.1 seconds
Started May 02 04:02:47 PM PDT 24
Finished May 02 04:12:49 PM PDT 24
Peak memory 202324 kb
Host smart-3ec7cf03-9823-4392-a5d7-e35cad6c63c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138254909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3138254909
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1806153985
Short name T622
Test name
Test status
Simulation time 494632718074 ps
CPU time 555.01 seconds
Started May 02 04:02:37 PM PDT 24
Finished May 02 04:11:53 PM PDT 24
Peak memory 202304 kb
Host smart-d54e8790-4471-4287-9723-951c35396782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806153985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1806153985
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.691744144
Short name T742
Test name
Test status
Simulation time 167038935542 ps
CPU time 383.24 seconds
Started May 02 04:02:39 PM PDT 24
Finished May 02 04:09:03 PM PDT 24
Peak memory 202384 kb
Host smart-d133f84e-0b3c-4901-88e6-1482a1ec8dd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=691744144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fixe
d.691744144
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1043061382
Short name T172
Test name
Test status
Simulation time 444374019060 ps
CPU time 242.23 seconds
Started May 02 04:02:47 PM PDT 24
Finished May 02 04:06:50 PM PDT 24
Peak memory 202320 kb
Host smart-d175e34c-1279-4869-8af2-e575066c5245
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043061382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1043061382
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.3198159412
Short name T747
Test name
Test status
Simulation time 203512024383 ps
CPU time 45.99 seconds
Started May 02 04:02:47 PM PDT 24
Finished May 02 04:03:33 PM PDT 24
Peak memory 202256 kb
Host smart-a064f8c3-ae0d-45c9-9668-1c312e5f64fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198159412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.3198159412
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.7569201
Short name T185
Test name
Test status
Simulation time 113678120561 ps
CPU time 428.6 seconds
Started May 02 04:02:57 PM PDT 24
Finished May 02 04:10:06 PM PDT 24
Peak memory 202716 kb
Host smart-94bb48b5-10fa-4616-935d-f878ab7d19f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7569201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.7569201
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2011944185
Short name T766
Test name
Test status
Simulation time 29730769232 ps
CPU time 64.89 seconds
Started May 02 04:02:51 PM PDT 24
Finished May 02 04:03:57 PM PDT 24
Peak memory 202124 kb
Host smart-d76db799-d520-4a5c-91e7-f0ddfa6bccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011944185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2011944185
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1961102774
Short name T381
Test name
Test status
Simulation time 3817124475 ps
CPU time 6.57 seconds
Started May 02 04:02:51 PM PDT 24
Finished May 02 04:02:58 PM PDT 24
Peak memory 202148 kb
Host smart-e7a4c840-1605-43af-86d4-05dc1d435c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961102774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1961102774
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.142175213
Short name T492
Test name
Test status
Simulation time 5573752419 ps
CPU time 13.41 seconds
Started May 02 04:02:40 PM PDT 24
Finished May 02 04:02:53 PM PDT 24
Peak memory 202080 kb
Host smart-72289549-8f54-412e-a1a1-6d5d97077f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142175213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.142175213
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3436446897
Short name T314
Test name
Test status
Simulation time 120978593743 ps
CPU time 77.8 seconds
Started May 02 04:02:58 PM PDT 24
Finished May 02 04:04:16 PM PDT 24
Peak memory 202460 kb
Host smart-e5788947-d233-4758-a759-b1df899e1171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436446897 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3436446897
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.4023622581
Short name T697
Test name
Test status
Simulation time 284119425 ps
CPU time 1.28 seconds
Started May 02 04:03:23 PM PDT 24
Finished May 02 04:03:24 PM PDT 24
Peak memory 201952 kb
Host smart-c91a4fd5-634f-4fbe-8c65-0ba2c094ebae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023622581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.4023622581
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3475670563
Short name T760
Test name
Test status
Simulation time 332881092410 ps
CPU time 723.56 seconds
Started May 02 04:03:11 PM PDT 24
Finished May 02 04:15:15 PM PDT 24
Peak memory 202404 kb
Host smart-c6a5cdf3-b8b0-4f89-b0fe-2381f3203d6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475670563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3475670563
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2761281012
Short name T737
Test name
Test status
Simulation time 170639985868 ps
CPU time 404.42 seconds
Started May 02 04:03:02 PM PDT 24
Finished May 02 04:09:47 PM PDT 24
Peak memory 202248 kb
Host smart-f85d7737-f97c-49b4-a116-ba29903d89c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761281012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2761281012
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.121642111
Short name T452
Test name
Test status
Simulation time 161627646174 ps
CPU time 96.77 seconds
Started May 02 04:03:11 PM PDT 24
Finished May 02 04:04:48 PM PDT 24
Peak memory 202248 kb
Host smart-f49ed79d-da2e-4a29-a918-7a61713252af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=121642111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.121642111
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1686449763
Short name T271
Test name
Test status
Simulation time 497652332437 ps
CPU time 303.07 seconds
Started May 02 04:03:10 PM PDT 24
Finished May 02 04:08:13 PM PDT 24
Peak memory 202412 kb
Host smart-a83e6a9a-2268-40b7-9972-9dc1a3926f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686449763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1686449763
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.247462797
Short name T673
Test name
Test status
Simulation time 161601382455 ps
CPU time 280.31 seconds
Started May 02 04:03:03 PM PDT 24
Finished May 02 04:07:44 PM PDT 24
Peak memory 202288 kb
Host smart-bf0e1873-eb44-4eb6-bbb6-d81db7bdeffd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=247462797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.247462797
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1072869241
Short name T485
Test name
Test status
Simulation time 526035970227 ps
CPU time 291.89 seconds
Started May 02 04:03:11 PM PDT 24
Finished May 02 04:08:04 PM PDT 24
Peak memory 202324 kb
Host smart-ed133781-35cc-4598-8269-d62e795797cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072869241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1072869241
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2901012973
Short name T504
Test name
Test status
Simulation time 394958291610 ps
CPU time 148.28 seconds
Started May 02 04:03:16 PM PDT 24
Finished May 02 04:05:45 PM PDT 24
Peak memory 202284 kb
Host smart-6cd56690-412d-4d53-abb0-ea4bdd9b6085
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901012973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2901012973
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3419654137
Short name T363
Test name
Test status
Simulation time 33392411794 ps
CPU time 20.47 seconds
Started May 02 04:03:11 PM PDT 24
Finished May 02 04:03:32 PM PDT 24
Peak memory 202084 kb
Host smart-f87774d1-e3ba-4cfe-be73-e9186191273d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419654137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3419654137
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1169349755
Short name T555
Test name
Test status
Simulation time 3811477689 ps
CPU time 1.63 seconds
Started May 02 04:03:11 PM PDT 24
Finished May 02 04:03:13 PM PDT 24
Peak memory 202140 kb
Host smart-38d28b78-fd38-4a7b-be64-27d1bba6cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169349755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1169349755
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2264566014
Short name T763
Test name
Test status
Simulation time 6008388578 ps
CPU time 7.75 seconds
Started May 02 04:02:58 PM PDT 24
Finished May 02 04:03:06 PM PDT 24
Peak memory 202132 kb
Host smart-8cff58db-915a-462c-8489-5e1583f9e398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264566014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2264566014
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.540685668
Short name T578
Test name
Test status
Simulation time 353240234747 ps
CPU time 225.98 seconds
Started May 02 04:03:15 PM PDT 24
Finished May 02 04:07:02 PM PDT 24
Peak memory 202312 kb
Host smart-d0957870-fc93-4d71-9ce2-cc58a7137fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540685668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
540685668
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2117126508
Short name T64
Test name
Test status
Simulation time 278196816228 ps
CPU time 207.18 seconds
Started May 02 04:03:16 PM PDT 24
Finished May 02 04:06:44 PM PDT 24
Peak memory 219172 kb
Host smart-e548c8fa-87a1-4819-888e-0fbdc3b958ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117126508 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2117126508
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1650160421
Short name T379
Test name
Test status
Simulation time 404807471 ps
CPU time 1.51 seconds
Started May 02 04:03:37 PM PDT 24
Finished May 02 04:03:40 PM PDT 24
Peak memory 202024 kb
Host smart-beeb092f-7b54-4e7d-b1a4-c9956774c263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650160421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1650160421
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2000042784
Short name T395
Test name
Test status
Simulation time 166210817010 ps
CPU time 111.47 seconds
Started May 02 04:03:30 PM PDT 24
Finished May 02 04:05:22 PM PDT 24
Peak memory 202276 kb
Host smart-514499db-d6c0-418b-941d-f236e6e8a6b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000042784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2000042784
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3624948242
Short name T138
Test name
Test status
Simulation time 502487624435 ps
CPU time 1148.23 seconds
Started May 02 04:03:25 PM PDT 24
Finished May 02 04:22:34 PM PDT 24
Peak memory 202324 kb
Host smart-a2c221c3-100d-4799-bdfc-9f0332a5614b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624948242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3624948242
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.288237120
Short name T543
Test name
Test status
Simulation time 488798922887 ps
CPU time 1210.55 seconds
Started May 02 04:03:23 PM PDT 24
Finished May 02 04:23:35 PM PDT 24
Peak memory 202248 kb
Host smart-28a65fcb-07cb-4ee6-ad54-2c083aba0f38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=288237120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.288237120
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.1251060358
Short name T255
Test name
Test status
Simulation time 170057635841 ps
CPU time 410.5 seconds
Started May 02 04:03:32 PM PDT 24
Finished May 02 04:10:23 PM PDT 24
Peak memory 202316 kb
Host smart-d54a8a4c-6ef0-40cf-999f-0f414492ced5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251060358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.1251060358
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.347631486
Short name T551
Test name
Test status
Simulation time 609939835745 ps
CPU time 655.45 seconds
Started May 02 04:03:33 PM PDT 24
Finished May 02 04:14:29 PM PDT 24
Peak memory 202284 kb
Host smart-6004ce85-9b45-41fd-881b-b01652b69ab6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347631486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.347631486
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2290440544
Short name T579
Test name
Test status
Simulation time 72109641091 ps
CPU time 250.44 seconds
Started May 02 04:03:38 PM PDT 24
Finished May 02 04:07:50 PM PDT 24
Peak memory 202660 kb
Host smart-97bb6b1d-6b68-49cd-b319-94626588d816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290440544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2290440544
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3755908448
Short name T453
Test name
Test status
Simulation time 22254963773 ps
CPU time 27.9 seconds
Started May 02 04:03:37 PM PDT 24
Finished May 02 04:04:05 PM PDT 24
Peak memory 202144 kb
Host smart-b8e095da-0157-4b8f-9dc9-09b7222ebfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755908448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3755908448
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1287813180
Short name T93
Test name
Test status
Simulation time 5142475345 ps
CPU time 1.84 seconds
Started May 02 04:03:38 PM PDT 24
Finished May 02 04:03:40 PM PDT 24
Peak memory 202148 kb
Host smart-11b7f6df-3a61-452d-bc72-c897c964d8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287813180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1287813180
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.962490122
Short name T510
Test name
Test status
Simulation time 6014840524 ps
CPU time 13.42 seconds
Started May 02 04:03:25 PM PDT 24
Finished May 02 04:03:39 PM PDT 24
Peak memory 202136 kb
Host smart-a0dc3bb5-4606-4353-9bc7-46fef96d1773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962490122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.962490122
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.2580900410
Short name T302
Test name
Test status
Simulation time 329997223187 ps
CPU time 482.53 seconds
Started May 02 04:03:38 PM PDT 24
Finished May 02 04:11:42 PM PDT 24
Peak memory 202336 kb
Host smart-8e75c58b-2fe6-4d05-ba45-005d6bf0a333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580900410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.2580900410
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.807069012
Short name T273
Test name
Test status
Simulation time 56634883527 ps
CPU time 76.23 seconds
Started May 02 04:03:37 PM PDT 24
Finished May 02 04:04:54 PM PDT 24
Peak memory 210636 kb
Host smart-3e2fc1e1-58ad-4eae-ba4e-6e8de73c355e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807069012 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.807069012
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.3958859995
Short name T330
Test name
Test status
Simulation time 500277680 ps
CPU time 1.88 seconds
Started May 02 04:04:05 PM PDT 24
Finished May 02 04:04:08 PM PDT 24
Peak memory 201972 kb
Host smart-77759a0b-3c46-4080-84e1-3ee4e58aa38d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958859995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.3958859995
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2140802881
Short name T47
Test name
Test status
Simulation time 362145350337 ps
CPU time 440.8 seconds
Started May 02 04:03:50 PM PDT 24
Finished May 02 04:11:12 PM PDT 24
Peak memory 202300 kb
Host smart-d57370ae-7d6e-46df-83d4-632254047dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140802881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2140802881
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2979589396
Short name T120
Test name
Test status
Simulation time 493445424635 ps
CPU time 821.11 seconds
Started May 02 04:03:44 PM PDT 24
Finished May 02 04:17:26 PM PDT 24
Peak memory 202272 kb
Host smart-d28aabcf-bf20-41e2-bcc8-000bf6970284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979589396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2979589396
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2682992920
Short name T373
Test name
Test status
Simulation time 497688914329 ps
CPU time 551.19 seconds
Started May 02 04:03:51 PM PDT 24
Finished May 02 04:13:02 PM PDT 24
Peak memory 202360 kb
Host smart-937a3d91-0fa5-40f0-9c54-7a52f7e11749
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682992920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2682992920
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.375447769
Short name T671
Test name
Test status
Simulation time 160225292370 ps
CPU time 92.98 seconds
Started May 02 04:03:38 PM PDT 24
Finished May 02 04:05:12 PM PDT 24
Peak memory 202268 kb
Host smart-a251dc95-beb4-4f50-84ad-e91322a33807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375447769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.375447769
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.902845465
Short name T427
Test name
Test status
Simulation time 331329788369 ps
CPU time 716.33 seconds
Started May 02 04:03:44 PM PDT 24
Finished May 02 04:15:41 PM PDT 24
Peak memory 202320 kb
Host smart-804074d7-5a07-40dd-96af-4f6ea647ec60
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=902845465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.902845465
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.438487944
Short name T310
Test name
Test status
Simulation time 354936850998 ps
CPU time 408.89 seconds
Started May 02 04:03:49 PM PDT 24
Finished May 02 04:10:39 PM PDT 24
Peak memory 202380 kb
Host smart-db6ca991-dee0-4da4-b4da-16cc8488a0f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438487944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_
wakeup.438487944
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3157935185
Short name T728
Test name
Test status
Simulation time 421794298223 ps
CPU time 370.61 seconds
Started May 02 04:03:50 PM PDT 24
Finished May 02 04:10:01 PM PDT 24
Peak memory 202316 kb
Host smart-e2cc1f33-5032-4531-931e-e379e0b17166
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157935185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3157935185
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3968997185
Short name T54
Test name
Test status
Simulation time 106478808895 ps
CPU time 343.03 seconds
Started May 02 04:03:59 PM PDT 24
Finished May 02 04:09:43 PM PDT 24
Peak memory 202604 kb
Host smart-3d0f9061-1c53-4c46-9500-b651a204b394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968997185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3968997185
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.4177517813
Short name T663
Test name
Test status
Simulation time 27667395376 ps
CPU time 15.57 seconds
Started May 02 04:03:58 PM PDT 24
Finished May 02 04:04:14 PM PDT 24
Peak memory 202108 kb
Host smart-acc0cca3-f7e2-4dfc-9b26-43b5ff6c1888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177517813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.4177517813
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1872254888
Short name T451
Test name
Test status
Simulation time 5351917981 ps
CPU time 3.78 seconds
Started May 02 04:03:49 PM PDT 24
Finished May 02 04:03:53 PM PDT 24
Peak memory 202104 kb
Host smart-e50a21df-6715-4e79-8a20-47097fa5c437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872254888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1872254888
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3054025923
Short name T399
Test name
Test status
Simulation time 5855976840 ps
CPU time 14.31 seconds
Started May 02 04:03:38 PM PDT 24
Finished May 02 04:03:53 PM PDT 24
Peak memory 202140 kb
Host smart-7fe35f11-bfb7-454a-a51d-0cd3d1237adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054025923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3054025923
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2587863433
Short name T305
Test name
Test status
Simulation time 496818586237 ps
CPU time 195.07 seconds
Started May 02 04:04:05 PM PDT 24
Finished May 02 04:07:21 PM PDT 24
Peak memory 202288 kb
Host smart-693910a0-80be-412d-b3bd-4f31bfe8a7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587863433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2587863433
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.525500162
Short name T88
Test name
Test status
Simulation time 133729267001 ps
CPU time 214.74 seconds
Started May 02 04:03:58 PM PDT 24
Finished May 02 04:07:34 PM PDT 24
Peak memory 210972 kb
Host smart-e50a3989-7bc4-48d6-9f92-6fac0e287adc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525500162 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.525500162
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.4110603382
Short name T682
Test name
Test status
Simulation time 511958633 ps
CPU time 0.94 seconds
Started May 02 04:04:14 PM PDT 24
Finished May 02 04:04:16 PM PDT 24
Peak memory 202016 kb
Host smart-29a54107-6c78-4b9f-a087-d107519b3a74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110603382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.4110603382
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.862410594
Short name T733
Test name
Test status
Simulation time 255310230316 ps
CPU time 112.51 seconds
Started May 02 04:04:11 PM PDT 24
Finished May 02 04:06:05 PM PDT 24
Peak memory 202308 kb
Host smart-89d2bda6-c845-4c64-b723-8435c40ce83a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862410594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.862410594
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3902469001
Short name T170
Test name
Test status
Simulation time 167138220665 ps
CPU time 84.27 seconds
Started May 02 04:04:13 PM PDT 24
Finished May 02 04:05:38 PM PDT 24
Peak memory 202316 kb
Host smart-f54f137f-f35c-4dea-962f-c268fa287d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902469001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3902469001
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.4280313798
Short name T294
Test name
Test status
Simulation time 492353195000 ps
CPU time 1092.36 seconds
Started May 02 04:04:06 PM PDT 24
Finished May 02 04:22:19 PM PDT 24
Peak memory 202240 kb
Host smart-f95b1a2c-b525-44c7-ad53-00eaaff4fff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280313798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.4280313798
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1647203850
Short name T603
Test name
Test status
Simulation time 161921016597 ps
CPU time 368.29 seconds
Started May 02 04:04:10 PM PDT 24
Finished May 02 04:10:19 PM PDT 24
Peak memory 202240 kb
Host smart-57815376-64dd-44c4-810c-8f628c978eba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647203850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1647203850
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.827722201
Short name T275
Test name
Test status
Simulation time 172819798214 ps
CPU time 380.21 seconds
Started May 02 04:04:05 PM PDT 24
Finished May 02 04:10:26 PM PDT 24
Peak memory 202348 kb
Host smart-33ab656e-be07-4016-b17b-24f4ef19f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827722201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.827722201
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3691956082
Short name T592
Test name
Test status
Simulation time 491144695186 ps
CPU time 1079.6 seconds
Started May 02 04:04:05 PM PDT 24
Finished May 02 04:22:06 PM PDT 24
Peak memory 202292 kb
Host smart-afa4b4e6-6eb6-4999-abbb-b384a99c7200
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691956082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3691956082
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3256093921
Short name T357
Test name
Test status
Simulation time 583909101421 ps
CPU time 208.27 seconds
Started May 02 04:04:11 PM PDT 24
Finished May 02 04:07:40 PM PDT 24
Peak memory 202272 kb
Host smart-019b2555-50b2-43fd-b57f-085b62b9f0b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256093921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3256093921
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2473393978
Short name T699
Test name
Test status
Simulation time 110823186009 ps
CPU time 610.78 seconds
Started May 02 04:04:14 PM PDT 24
Finished May 02 04:14:25 PM PDT 24
Peak memory 202668 kb
Host smart-58caceef-e217-4e8f-9239-e0036da18d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473393978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2473393978
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3299398791
Short name T462
Test name
Test status
Simulation time 33484004887 ps
CPU time 37.56 seconds
Started May 02 04:04:12 PM PDT 24
Finished May 02 04:04:51 PM PDT 24
Peak memory 202140 kb
Host smart-2d26d479-b099-49b4-8d69-4ea95f545cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299398791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3299398791
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3079313129
Short name T611
Test name
Test status
Simulation time 4681603076 ps
CPU time 3.67 seconds
Started May 02 04:04:11 PM PDT 24
Finished May 02 04:04:15 PM PDT 24
Peak memory 202088 kb
Host smart-c2be0ed6-6314-4828-b5ee-082b9d60ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079313129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3079313129
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.505625912
Short name T506
Test name
Test status
Simulation time 5680635577 ps
CPU time 7.57 seconds
Started May 02 04:04:05 PM PDT 24
Finished May 02 04:04:14 PM PDT 24
Peak memory 202072 kb
Host smart-f411fc95-7ee2-404b-9043-60e5547d92f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505625912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.505625912
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2579715567
Short name T16
Test name
Test status
Simulation time 2337183847331 ps
CPU time 153.66 seconds
Started May 02 04:04:12 PM PDT 24
Finished May 02 04:06:47 PM PDT 24
Peak memory 210984 kb
Host smart-39adc658-ce13-4a8f-a38f-2508f1d7d7e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579715567 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2579715567
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.742861101
Short name T367
Test name
Test status
Simulation time 548302406 ps
CPU time 0.9 seconds
Started May 02 04:04:26 PM PDT 24
Finished May 02 04:04:28 PM PDT 24
Peak memory 201996 kb
Host smart-97321af7-d791-4303-b8f6-c3b05f88b7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742861101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.742861101
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.4052521429
Short name T600
Test name
Test status
Simulation time 489104325036 ps
CPU time 781.04 seconds
Started May 02 04:04:20 PM PDT 24
Finished May 02 04:17:22 PM PDT 24
Peak memory 202320 kb
Host smart-0bbfa537-0d1c-4c89-a3b3-94ae16868555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052521429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.4052521429
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4193429996
Short name T574
Test name
Test status
Simulation time 490095510840 ps
CPU time 628.21 seconds
Started May 02 04:04:21 PM PDT 24
Finished May 02 04:14:49 PM PDT 24
Peak memory 202396 kb
Host smart-b5d23111-37df-40d8-8051-1eb3c6242573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193429996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4193429996
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3267248488
Short name T608
Test name
Test status
Simulation time 160555583611 ps
CPU time 192.23 seconds
Started May 02 04:04:18 PM PDT 24
Finished May 02 04:07:32 PM PDT 24
Peak memory 202324 kb
Host smart-84aaec48-8955-4a35-9bf6-e791b8ea8e42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267248488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3267248488
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1947234976
Short name T154
Test name
Test status
Simulation time 490832017990 ps
CPU time 277.63 seconds
Started May 02 04:04:18 PM PDT 24
Finished May 02 04:08:57 PM PDT 24
Peak memory 202320 kb
Host smart-2f1e312e-fce0-4e11-bc93-e42ea5d014b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947234976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1947234976
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2660696750
Short name T722
Test name
Test status
Simulation time 498646461633 ps
CPU time 1052.92 seconds
Started May 02 04:04:18 PM PDT 24
Finished May 02 04:21:52 PM PDT 24
Peak memory 202268 kb
Host smart-2682e829-c6a6-471d-bc22-b7d9c2c57f0f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660696750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2660696750
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.868165783
Short name T601
Test name
Test status
Simulation time 381220805915 ps
CPU time 240.64 seconds
Started May 02 04:04:18 PM PDT 24
Finished May 02 04:08:20 PM PDT 24
Peak memory 202324 kb
Host smart-c67c74c6-be0d-4855-9b74-d8a1877e8af8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868165783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.868165783
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.576967095
Short name T6
Test name
Test status
Simulation time 586472508063 ps
CPU time 1229.99 seconds
Started May 02 04:04:19 PM PDT 24
Finished May 02 04:24:50 PM PDT 24
Peak memory 202288 kb
Host smart-e64760cc-9f14-45d2-9d75-2eae21db232f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576967095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
adc_ctrl_filters_wakeup_fixed.576967095
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2685340108
Short name T322
Test name
Test status
Simulation time 88533687209 ps
CPU time 345.77 seconds
Started May 02 04:04:26 PM PDT 24
Finished May 02 04:10:12 PM PDT 24
Peak memory 202672 kb
Host smart-5456d2a4-427d-461f-82e9-77565f4e8d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685340108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2685340108
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.4214795086
Short name T348
Test name
Test status
Simulation time 43930393398 ps
CPU time 24.36 seconds
Started May 02 04:04:28 PM PDT 24
Finished May 02 04:04:53 PM PDT 24
Peak memory 202148 kb
Host smart-cab1f6d7-2421-4005-b790-b6ac4e1463d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214795086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.4214795086
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1031902894
Short name T338
Test name
Test status
Simulation time 2990861501 ps
CPU time 4.92 seconds
Started May 02 04:04:26 PM PDT 24
Finished May 02 04:04:31 PM PDT 24
Peak memory 202192 kb
Host smart-6ec2a7f6-b311-46da-bbcb-0b552ede20a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031902894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1031902894
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1773639138
Short name T384
Test name
Test status
Simulation time 5938729281 ps
CPU time 13.98 seconds
Started May 02 04:04:12 PM PDT 24
Finished May 02 04:04:27 PM PDT 24
Peak memory 202188 kb
Host smart-5d88e85c-31d2-40ff-a924-fffeb514bb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773639138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1773639138
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1521876117
Short name T37
Test name
Test status
Simulation time 93969730560 ps
CPU time 237.13 seconds
Started May 02 04:04:26 PM PDT 24
Finished May 02 04:08:24 PM PDT 24
Peak memory 218664 kb
Host smart-ee14b112-c491-451e-9ee2-e32380e77ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521876117 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1521876117
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.3256864475
Short name T541
Test name
Test status
Simulation time 461019760 ps
CPU time 0.95 seconds
Started May 02 04:04:46 PM PDT 24
Finished May 02 04:04:48 PM PDT 24
Peak memory 201992 kb
Host smart-750b4d9e-8c25-4d12-a8b4-6e593d1a8f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256864475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.3256864475
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2198100459
Short name T152
Test name
Test status
Simulation time 516257951832 ps
CPU time 151.95 seconds
Started May 02 04:04:39 PM PDT 24
Finished May 02 04:07:12 PM PDT 24
Peak memory 202248 kb
Host smart-5cb49ed4-697d-4aa0-a7a0-6bec4239aebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198100459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2198100459
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3373562438
Short name T637
Test name
Test status
Simulation time 161871844535 ps
CPU time 389.39 seconds
Started May 02 04:04:30 PM PDT 24
Finished May 02 04:11:00 PM PDT 24
Peak memory 201516 kb
Host smart-1270ba19-46c8-4cfb-84dc-0b2cc42cece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373562438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3373562438
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.116921937
Short name T257
Test name
Test status
Simulation time 324819485829 ps
CPU time 192.7 seconds
Started May 02 04:04:33 PM PDT 24
Finished May 02 04:07:47 PM PDT 24
Peak memory 202360 kb
Host smart-e74696e2-e41f-4f0d-be4e-4dee81a39010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116921937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.116921937
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.948703325
Short name T437
Test name
Test status
Simulation time 492638136914 ps
CPU time 705.51 seconds
Started May 02 04:04:33 PM PDT 24
Finished May 02 04:16:19 PM PDT 24
Peak memory 202296 kb
Host smart-e2dee159-3da1-4292-89b2-89c1cab9f0ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=948703325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.948703325
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2806459486
Short name T40
Test name
Test status
Simulation time 177025149560 ps
CPU time 93.53 seconds
Started May 02 04:04:32 PM PDT 24
Finished May 02 04:06:06 PM PDT 24
Peak memory 202256 kb
Host smart-1bd08c77-363a-403b-9f56-559a135ddf54
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806459486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2806459486
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.253914818
Short name T685
Test name
Test status
Simulation time 414244168119 ps
CPU time 930.51 seconds
Started May 02 04:04:33 PM PDT 24
Finished May 02 04:20:04 PM PDT 24
Peak memory 202284 kb
Host smart-c2573779-2037-4939-a20f-a3bafdb1c587
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253914818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.253914818
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.3643573944
Short name T642
Test name
Test status
Simulation time 115776236909 ps
CPU time 615.63 seconds
Started May 02 04:04:39 PM PDT 24
Finished May 02 04:14:56 PM PDT 24
Peak memory 202656 kb
Host smart-fd102737-4020-441c-8077-e972de1d5772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643573944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.3643573944
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.3203254498
Short name T377
Test name
Test status
Simulation time 37709347339 ps
CPU time 5.3 seconds
Started May 02 04:04:40 PM PDT 24
Finished May 02 04:04:47 PM PDT 24
Peak memory 202112 kb
Host smart-ed3d00aa-20cf-49ac-a99a-7c003d402338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203254498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.3203254498
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.878754588
Short name T741
Test name
Test status
Simulation time 5199628399 ps
CPU time 11.95 seconds
Started May 02 04:04:39 PM PDT 24
Finished May 02 04:04:52 PM PDT 24
Peak memory 202088 kb
Host smart-d830f883-b490-4944-ac4a-697dde1d59c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878754588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.878754588
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2865728855
Short name T38
Test name
Test status
Simulation time 5722449984 ps
CPU time 15.01 seconds
Started May 02 04:04:32 PM PDT 24
Finished May 02 04:04:48 PM PDT 24
Peak memory 202084 kb
Host smart-58933b8a-93a8-494c-b81c-d05c510e32c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865728855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2865728855
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1537671160
Short name T405
Test name
Test status
Simulation time 313850164382 ps
CPU time 573.64 seconds
Started May 02 04:04:40 PM PDT 24
Finished May 02 04:14:15 PM PDT 24
Peak memory 210848 kb
Host smart-8c052ac8-73f8-4ab7-90ad-66e78318eea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537671160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1537671160
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.896780576
Short name T20
Test name
Test status
Simulation time 53420180797 ps
CPU time 100.33 seconds
Started May 02 04:04:39 PM PDT 24
Finished May 02 04:06:20 PM PDT 24
Peak memory 211004 kb
Host smart-c3d85f6a-77d1-41cf-b29d-0f910baf75af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896780576 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.896780576
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.19600561
Short name T584
Test name
Test status
Simulation time 473891979 ps
CPU time 1.65 seconds
Started May 02 04:00:19 PM PDT 24
Finished May 02 04:00:22 PM PDT 24
Peak memory 201992 kb
Host smart-4b5ca476-1bf4-46b5-aadd-183204d7f32c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19600561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.19600561
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1684443019
Short name T167
Test name
Test status
Simulation time 211000600902 ps
CPU time 124.46 seconds
Started May 02 04:00:16 PM PDT 24
Finished May 02 04:02:21 PM PDT 24
Peak memory 202300 kb
Host smart-d8a330a3-ef3f-46c0-b542-6525de53060d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684443019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1684443019
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.36347853
Short name T560
Test name
Test status
Simulation time 168999097705 ps
CPU time 103.45 seconds
Started May 02 04:00:17 PM PDT 24
Finished May 02 04:02:01 PM PDT 24
Peak memory 202284 kb
Host smart-a37b25c0-c0a2-4cac-b7f7-c31337b9a372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36347853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.36347853
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.1382253679
Short name T311
Test name
Test status
Simulation time 492468542428 ps
CPU time 249.68 seconds
Started May 02 04:00:10 PM PDT 24
Finished May 02 04:04:21 PM PDT 24
Peak memory 202240 kb
Host smart-758e312e-a0f0-4f7b-a0f1-ae49400cd855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382253679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.1382253679
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3298228829
Short name T29
Test name
Test status
Simulation time 166041270467 ps
CPU time 392.36 seconds
Started May 02 04:00:18 PM PDT 24
Finished May 02 04:06:51 PM PDT 24
Peak memory 202304 kb
Host smart-63d3a311-7154-4815-b22c-cfa3587ba422
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298228829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3298228829
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1784728446
Short name T726
Test name
Test status
Simulation time 163460961664 ps
CPU time 318.27 seconds
Started May 02 04:00:12 PM PDT 24
Finished May 02 04:05:31 PM PDT 24
Peak memory 202376 kb
Host smart-4d7c5c2d-63eb-4501-ae9c-bbda8a6b1c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784728446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1784728446
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.3703284766
Short name T39
Test name
Test status
Simulation time 329910114964 ps
CPU time 196.1 seconds
Started May 02 04:00:12 PM PDT 24
Finished May 02 04:03:29 PM PDT 24
Peak memory 202276 kb
Host smart-523b5d1b-36fb-47c4-b715-eb7cac858fc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703284766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.3703284766
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2514904842
Short name T616
Test name
Test status
Simulation time 350984398407 ps
CPU time 317.52 seconds
Started May 02 04:00:18 PM PDT 24
Finished May 02 04:05:37 PM PDT 24
Peak memory 202320 kb
Host smart-bc58c260-3413-43b0-ae93-664ed70c00bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514904842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2514904842
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2132630619
Short name T538
Test name
Test status
Simulation time 604530481615 ps
CPU time 333.46 seconds
Started May 02 04:00:18 PM PDT 24
Finished May 02 04:05:53 PM PDT 24
Peak memory 202272 kb
Host smart-49dc550e-19c2-4a1f-a2e1-8e941a07dce2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132630619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2132630619
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1178574758
Short name T669
Test name
Test status
Simulation time 126259557527 ps
CPU time 483.48 seconds
Started May 02 04:00:19 PM PDT 24
Finished May 02 04:08:23 PM PDT 24
Peak memory 202628 kb
Host smart-96f7715b-1af2-4484-8050-6aeb5f8c6707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178574758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1178574758
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.138852247
Short name T651
Test name
Test status
Simulation time 40633187644 ps
CPU time 101.13 seconds
Started May 02 04:00:18 PM PDT 24
Finished May 02 04:02:00 PM PDT 24
Peak memory 202080 kb
Host smart-b51864de-b1c1-4d7e-89ed-d0c892ea2cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138852247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.138852247
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2215269264
Short name T496
Test name
Test status
Simulation time 3580913940 ps
CPU time 2.88 seconds
Started May 02 04:00:16 PM PDT 24
Finished May 02 04:00:20 PM PDT 24
Peak memory 202180 kb
Host smart-2612e6d7-f6de-488a-afb2-ac2ff69bb303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215269264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2215269264
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.4114680774
Short name T66
Test name
Test status
Simulation time 4287447865 ps
CPU time 2.28 seconds
Started May 02 04:00:18 PM PDT 24
Finished May 02 04:00:21 PM PDT 24
Peak memory 217780 kb
Host smart-57ba19cf-424a-4fd0-ae46-24bcd4160869
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114680774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.4114680774
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.113467270
Short name T444
Test name
Test status
Simulation time 5547788881 ps
CPU time 7.28 seconds
Started May 02 04:00:11 PM PDT 24
Finished May 02 04:00:19 PM PDT 24
Peak memory 202128 kb
Host smart-a5880315-dbc5-4a19-8c41-3976f476c5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113467270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.113467270
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1640739773
Short name T201
Test name
Test status
Simulation time 282140913356 ps
CPU time 906.24 seconds
Started May 02 04:00:17 PM PDT 24
Finished May 02 04:15:24 PM PDT 24
Peak memory 210868 kb
Host smart-11cf295e-25d4-4ab3-9346-f3b15f875e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640739773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1640739773
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1251001757
Short name T674
Test name
Test status
Simulation time 453165961 ps
CPU time 1.7 seconds
Started May 02 04:04:53 PM PDT 24
Finished May 02 04:04:56 PM PDT 24
Peak memory 201924 kb
Host smart-0c7df4a3-3ca3-42d3-91b8-dd41efec8343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251001757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1251001757
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3658434534
Short name T696
Test name
Test status
Simulation time 178696337288 ps
CPU time 419.01 seconds
Started May 02 04:05:10 PM PDT 24
Finished May 02 04:12:10 PM PDT 24
Peak memory 202252 kb
Host smart-595707e0-516e-4a68-87ce-8918f3fd9751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658434534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3658434534
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3548642421
Short name T457
Test name
Test status
Simulation time 165907985979 ps
CPU time 353.03 seconds
Started May 02 04:04:47 PM PDT 24
Finished May 02 04:10:40 PM PDT 24
Peak memory 202244 kb
Host smart-11fec4da-4fbd-4360-8b3d-b6f2cd96750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548642421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3548642421
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3632104987
Short name T744
Test name
Test status
Simulation time 497291621067 ps
CPU time 130.17 seconds
Started May 02 04:04:46 PM PDT 24
Finished May 02 04:06:56 PM PDT 24
Peak memory 202252 kb
Host smart-0c6772a1-764f-49a5-a390-dd924f13dc9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632104987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3632104987
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3858706709
Short name T693
Test name
Test status
Simulation time 329575659250 ps
CPU time 726.67 seconds
Started May 02 04:04:47 PM PDT 24
Finished May 02 04:16:55 PM PDT 24
Peak memory 202296 kb
Host smart-b178658e-bd3a-471c-aed2-da292a0cda49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858706709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3858706709
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.43904688
Short name T571
Test name
Test status
Simulation time 166457437021 ps
CPU time 368 seconds
Started May 02 04:04:47 PM PDT 24
Finished May 02 04:10:56 PM PDT 24
Peak memory 202260 kb
Host smart-430081c3-3698-4bae-90ac-88e1e9b75bbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=43904688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fixed
.43904688
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1379760879
Short name T750
Test name
Test status
Simulation time 174993019387 ps
CPU time 410.77 seconds
Started May 02 04:04:46 PM PDT 24
Finished May 02 04:11:37 PM PDT 24
Peak memory 202344 kb
Host smart-02fd5a0f-416d-4e1b-9a0b-9e37f2429f7e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379760879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1379760879
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2046183083
Short name T387
Test name
Test status
Simulation time 193220795022 ps
CPU time 466.68 seconds
Started May 02 04:04:53 PM PDT 24
Finished May 02 04:12:41 PM PDT 24
Peak memory 202248 kb
Host smart-23323f57-843b-4c21-9039-71a218bdf7a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046183083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2046183083
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3864883230
Short name T731
Test name
Test status
Simulation time 117779294702 ps
CPU time 588.11 seconds
Started May 02 04:04:53 PM PDT 24
Finished May 02 04:14:41 PM PDT 24
Peak memory 202604 kb
Host smart-bcab5261-734b-4a17-b052-c9fa799c4bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864883230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3864883230
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.4197169898
Short name T686
Test name
Test status
Simulation time 27119836601 ps
CPU time 16.72 seconds
Started May 02 04:04:52 PM PDT 24
Finished May 02 04:05:10 PM PDT 24
Peak memory 202136 kb
Host smart-5a493230-ef16-4f8f-9104-af28912e49bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197169898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.4197169898
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.4031255742
Short name T446
Test name
Test status
Simulation time 3953211702 ps
CPU time 4.74 seconds
Started May 02 04:04:54 PM PDT 24
Finished May 02 04:05:00 PM PDT 24
Peak memory 202088 kb
Host smart-7b7087e6-3d3b-42fb-8862-6a61b136678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031255742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.4031255742
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1463018559
Short name T436
Test name
Test status
Simulation time 5586187362 ps
CPU time 3.93 seconds
Started May 02 04:04:46 PM PDT 24
Finished May 02 04:04:50 PM PDT 24
Peak memory 202136 kb
Host smart-da6dc813-45f3-4ba4-8bb6-73c5f19c8f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463018559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1463018559
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.657537621
Short name T487
Test name
Test status
Simulation time 171746538834 ps
CPU time 319.77 seconds
Started May 02 04:04:53 PM PDT 24
Finished May 02 04:10:14 PM PDT 24
Peak memory 202360 kb
Host smart-6a370172-6e5e-4a28-8bc7-b4d7ad0de88e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657537621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
657537621
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1287343345
Short name T723
Test name
Test status
Simulation time 255778492860 ps
CPU time 124.66 seconds
Started May 02 04:04:53 PM PDT 24
Finished May 02 04:06:59 PM PDT 24
Peak memory 210624 kb
Host smart-6016e484-a74d-4c38-85ff-a725a559a42a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287343345 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1287343345
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.4109453059
Short name T352
Test name
Test status
Simulation time 398685349 ps
CPU time 0.99 seconds
Started May 02 04:05:09 PM PDT 24
Finished May 02 04:05:11 PM PDT 24
Peak memory 202000 kb
Host smart-a8ffdcb3-f336-440e-be9b-9f1484cd510a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109453059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.4109453059
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2809252577
Short name T291
Test name
Test status
Simulation time 339609279269 ps
CPU time 207.38 seconds
Started May 02 04:05:01 PM PDT 24
Finished May 02 04:08:30 PM PDT 24
Peak memory 202312 kb
Host smart-b6c5db48-df6d-433b-b23f-84fe4c81cbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809252577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2809252577
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3109836622
Short name T141
Test name
Test status
Simulation time 328328899452 ps
CPU time 389.58 seconds
Started May 02 04:05:01 PM PDT 24
Finished May 02 04:11:32 PM PDT 24
Peak memory 202292 kb
Host smart-4860cfb2-dff4-48cd-bda7-171bf36311a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109836622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3109836622
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.842831150
Short name T705
Test name
Test status
Simulation time 492407791202 ps
CPU time 609.46 seconds
Started May 02 04:05:01 PM PDT 24
Finished May 02 04:15:12 PM PDT 24
Peak memory 202272 kb
Host smart-6b282cbf-4a40-49c5-9e7e-1446777054eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=842831150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.842831150
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3401564210
Short name T359
Test name
Test status
Simulation time 323479154611 ps
CPU time 212.98 seconds
Started May 02 04:04:56 PM PDT 24
Finished May 02 04:08:30 PM PDT 24
Peak memory 202264 kb
Host smart-cc3a5622-929f-44de-955b-14218362b651
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401564210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3401564210
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.312243611
Short name T735
Test name
Test status
Simulation time 520877435877 ps
CPU time 1190.16 seconds
Started May 02 04:05:00 PM PDT 24
Finished May 02 04:24:52 PM PDT 24
Peak memory 202336 kb
Host smart-4b54c9fe-433f-4822-a860-32cbf9f93eaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312243611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_
wakeup.312243611
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1483619177
Short name T736
Test name
Test status
Simulation time 396956367275 ps
CPU time 355.53 seconds
Started May 02 04:05:01 PM PDT 24
Finished May 02 04:10:58 PM PDT 24
Peak memory 202308 kb
Host smart-a2be2217-db9b-4f8f-885c-8c0b8b8e8da0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483619177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1483619177
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.4032959706
Short name T459
Test name
Test status
Simulation time 77854439688 ps
CPU time 269.01 seconds
Started May 02 04:05:11 PM PDT 24
Finished May 02 04:09:40 PM PDT 24
Peak memory 202668 kb
Host smart-0c1260f7-e6e6-4957-807c-46305d33f823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032959706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.4032959706
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.792862440
Short name T580
Test name
Test status
Simulation time 22985384708 ps
CPU time 37.35 seconds
Started May 02 04:05:02 PM PDT 24
Finished May 02 04:05:40 PM PDT 24
Peak memory 202096 kb
Host smart-4f170f87-19e2-4a35-9f17-bf0a9fd4590b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792862440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.792862440
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3586125577
Short name T743
Test name
Test status
Simulation time 4156153660 ps
CPU time 3.42 seconds
Started May 02 04:05:00 PM PDT 24
Finished May 02 04:05:04 PM PDT 24
Peak memory 202160 kb
Host smart-72776f9b-0839-4035-9fcc-0486d7b370c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586125577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3586125577
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2490184945
Short name T41
Test name
Test status
Simulation time 5466317154 ps
CPU time 4.11 seconds
Started May 02 04:04:54 PM PDT 24
Finished May 02 04:04:58 PM PDT 24
Peak memory 202124 kb
Host smart-31092abc-4e89-4dca-a05c-3dd923f59c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490184945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2490184945
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3467100690
Short name T227
Test name
Test status
Simulation time 172713640595 ps
CPU time 99.44 seconds
Started May 02 04:05:09 PM PDT 24
Finished May 02 04:06:49 PM PDT 24
Peak memory 202280 kb
Host smart-0419fd8d-520e-425b-ae2d-3821ff0649cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467100690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3467100690
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2106617238
Short name T596
Test name
Test status
Simulation time 104614091839 ps
CPU time 121.11 seconds
Started May 02 04:05:12 PM PDT 24
Finished May 02 04:07:13 PM PDT 24
Peak memory 210620 kb
Host smart-e29f2910-6353-416d-a8a2-262bcb6d254a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106617238 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2106617238
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2148462652
Short name T400
Test name
Test status
Simulation time 445854903 ps
CPU time 0.87 seconds
Started May 02 04:05:27 PM PDT 24
Finished May 02 04:05:29 PM PDT 24
Peak memory 202028 kb
Host smart-c88fdebe-d76d-4108-8722-68b79e243428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148462652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2148462652
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.277746444
Short name T207
Test name
Test status
Simulation time 333583864687 ps
CPU time 572.43 seconds
Started May 02 04:05:21 PM PDT 24
Finished May 02 04:14:54 PM PDT 24
Peak memory 202316 kb
Host smart-00e99fc2-0be4-40b5-810f-5f9a33c1f014
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277746444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.277746444
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3275128769
Short name T166
Test name
Test status
Simulation time 331005592991 ps
CPU time 235.94 seconds
Started May 02 04:05:20 PM PDT 24
Finished May 02 04:09:17 PM PDT 24
Peak memory 202336 kb
Host smart-b4131200-c7ae-4cca-a105-cd362bfd6365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275128769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3275128769
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.1969555678
Short name T645
Test name
Test status
Simulation time 486922723929 ps
CPU time 1172.85 seconds
Started May 02 04:05:10 PM PDT 24
Finished May 02 04:24:43 PM PDT 24
Peak memory 202316 kb
Host smart-2929746f-ffd9-43a9-9264-664942a0a7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969555678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.1969555678
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.4094212879
Short name T350
Test name
Test status
Simulation time 163946372503 ps
CPU time 101.21 seconds
Started May 02 04:05:14 PM PDT 24
Finished May 02 04:06:56 PM PDT 24
Peak memory 202292 kb
Host smart-87743853-a112-4f73-aba2-3d4aa67f0378
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094212879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.4094212879
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3308632727
Short name T232
Test name
Test status
Simulation time 164862155484 ps
CPU time 405.1 seconds
Started May 02 04:05:07 PM PDT 24
Finished May 02 04:11:53 PM PDT 24
Peak memory 202316 kb
Host smart-0e8470db-ef71-48c1-9ec8-37ae04c08562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308632727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3308632727
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.217509379
Short name T704
Test name
Test status
Simulation time 163954219118 ps
CPU time 371.05 seconds
Started May 02 04:05:08 PM PDT 24
Finished May 02 04:11:20 PM PDT 24
Peak memory 202300 kb
Host smart-195cfc09-b088-4101-b5d4-29046e0533cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=217509379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.217509379
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1824240146
Short name T495
Test name
Test status
Simulation time 180935414308 ps
CPU time 113.61 seconds
Started May 02 04:05:14 PM PDT 24
Finished May 02 04:07:08 PM PDT 24
Peak memory 202388 kb
Host smart-5d7ef855-99d0-4293-bf1c-d4473b8f129d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824240146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1824240146
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3128509715
Short name T4
Test name
Test status
Simulation time 599964628691 ps
CPU time 486.71 seconds
Started May 02 04:05:23 PM PDT 24
Finished May 02 04:13:31 PM PDT 24
Peak memory 202288 kb
Host smart-323d4441-2fcb-4eb2-ad8d-7645dff489cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128509715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3128509715
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3251059076
Short name T544
Test name
Test status
Simulation time 69926108824 ps
CPU time 305.33 seconds
Started May 02 04:05:27 PM PDT 24
Finished May 02 04:10:33 PM PDT 24
Peak memory 202720 kb
Host smart-20419e2e-5711-4466-b7b5-a233f8c9501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251059076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3251059076
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1177740336
Short name T428
Test name
Test status
Simulation time 34706466092 ps
CPU time 37.99 seconds
Started May 02 04:05:21 PM PDT 24
Finished May 02 04:06:00 PM PDT 24
Peak memory 202112 kb
Host smart-2373e151-803b-4697-884e-99ecade48273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177740336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1177740336
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1485571521
Short name T565
Test name
Test status
Simulation time 4394832704 ps
CPU time 3.12 seconds
Started May 02 04:05:23 PM PDT 24
Finished May 02 04:05:27 PM PDT 24
Peak memory 202120 kb
Host smart-ec978a12-ac9d-4f17-9eef-224fe1916d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485571521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1485571521
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.1806525152
Short name T83
Test name
Test status
Simulation time 6013692986 ps
CPU time 16.13 seconds
Started May 02 04:05:11 PM PDT 24
Finished May 02 04:05:28 PM PDT 24
Peak memory 202128 kb
Host smart-72703bd0-62cc-475e-a4d5-2aad9e83934f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806525152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.1806525152
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3956926891
Short name T171
Test name
Test status
Simulation time 445138807027 ps
CPU time 561.75 seconds
Started May 02 04:05:28 PM PDT 24
Finished May 02 04:14:51 PM PDT 24
Peak memory 202268 kb
Host smart-e454dd6e-8661-4255-971f-72f1359a0db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956926891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3956926891
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.2729595741
Short name T74
Test name
Test status
Simulation time 357364603 ps
CPU time 0.82 seconds
Started May 02 04:05:40 PM PDT 24
Finished May 02 04:05:41 PM PDT 24
Peak memory 201964 kb
Host smart-dace9842-d6c5-438a-aa48-d3315b11b7d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729595741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.2729595741
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3193870351
Short name T143
Test name
Test status
Simulation time 161690127175 ps
CPU time 365.28 seconds
Started May 02 04:05:35 PM PDT 24
Finished May 02 04:11:41 PM PDT 24
Peak memory 202388 kb
Host smart-d2fd945f-62ae-4476-ab5f-9c4420350845
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193870351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3193870351
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.2639831269
Short name T245
Test name
Test status
Simulation time 499388167769 ps
CPU time 337.68 seconds
Started May 02 04:05:34 PM PDT 24
Finished May 02 04:11:13 PM PDT 24
Peak memory 202232 kb
Host smart-65cc95be-5b96-4ffa-a196-63ab8a684a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639831269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.2639831269
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1549657220
Short name T12
Test name
Test status
Simulation time 164474673969 ps
CPU time 25.28 seconds
Started May 02 04:05:27 PM PDT 24
Finished May 02 04:05:53 PM PDT 24
Peak memory 202276 kb
Host smart-6b2f1d12-eee5-4375-953f-19bca358b577
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549657220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1549657220
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1464622542
Short name T264
Test name
Test status
Simulation time 490096649276 ps
CPU time 259.76 seconds
Started May 02 04:05:29 PM PDT 24
Finished May 02 04:09:49 PM PDT 24
Peak memory 202368 kb
Host smart-eb07cef8-f444-4366-ab7f-40ffa8c2b217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464622542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1464622542
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.706648296
Short name T329
Test name
Test status
Simulation time 170745794259 ps
CPU time 402.52 seconds
Started May 02 04:05:34 PM PDT 24
Finished May 02 04:12:17 PM PDT 24
Peak memory 202316 kb
Host smart-35e20db0-dc29-4e84-b049-f88aa158b78c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=706648296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.706648296
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1147064378
Short name T212
Test name
Test status
Simulation time 203150410189 ps
CPU time 50.51 seconds
Started May 02 04:05:26 PM PDT 24
Finished May 02 04:06:18 PM PDT 24
Peak memory 202264 kb
Host smart-6dc1ca6e-8943-4790-ab00-2d3268a94c8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147064378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1147064378
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1867065112
Short name T343
Test name
Test status
Simulation time 418506114566 ps
CPU time 913.96 seconds
Started May 02 04:05:34 PM PDT 24
Finished May 02 04:20:48 PM PDT 24
Peak memory 202248 kb
Host smart-9047d9dd-035f-4779-ba55-1fae013c6254
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867065112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1867065112
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3109744759
Short name T617
Test name
Test status
Simulation time 67423695249 ps
CPU time 339.43 seconds
Started May 02 04:05:36 PM PDT 24
Finished May 02 04:11:16 PM PDT 24
Peak memory 202740 kb
Host smart-f32420ed-bcc3-4868-b3f1-b40ce6d0e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109744759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3109744759
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3966609774
Short name T521
Test name
Test status
Simulation time 27035966613 ps
CPU time 63.88 seconds
Started May 02 04:05:34 PM PDT 24
Finished May 02 04:06:38 PM PDT 24
Peak memory 202144 kb
Host smart-7d281633-1ccd-4c10-aad0-d91a5ea791ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966609774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3966609774
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3778063777
Short name T656
Test name
Test status
Simulation time 4853222813 ps
CPU time 6.24 seconds
Started May 02 04:05:35 PM PDT 24
Finished May 02 04:05:42 PM PDT 24
Peak memory 202152 kb
Host smart-4152729a-a1f9-47be-9e30-e40142232e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778063777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3778063777
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3128841188
Short name T42
Test name
Test status
Simulation time 5969699804 ps
CPU time 4.45 seconds
Started May 02 04:05:28 PM PDT 24
Finished May 02 04:05:33 PM PDT 24
Peak memory 202128 kb
Host smart-5d791c5c-447b-4157-91cf-a8abe5f0da01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128841188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3128841188
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2176859783
Short name T615
Test name
Test status
Simulation time 199275939023 ps
CPU time 211.98 seconds
Started May 02 04:05:40 PM PDT 24
Finished May 02 04:09:13 PM PDT 24
Peak memory 202352 kb
Host smart-898ac4b3-47d0-49e0-9457-3cd4efcb0ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176859783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2176859783
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3874521875
Short name T621
Test name
Test status
Simulation time 323180390 ps
CPU time 1.21 seconds
Started May 02 04:06:01 PM PDT 24
Finished May 02 04:06:02 PM PDT 24
Peak memory 201996 kb
Host smart-006fa4bf-a665-4ac2-97e7-fbd63928e0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874521875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3874521875
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.911970306
Short name T298
Test name
Test status
Simulation time 378611676772 ps
CPU time 218.63 seconds
Started May 02 04:05:45 PM PDT 24
Finished May 02 04:09:24 PM PDT 24
Peak memory 202344 kb
Host smart-c6573cb3-c0e9-42cb-84e7-e828dba3820f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911970306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.911970306
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2167109699
Short name T149
Test name
Test status
Simulation time 480833818267 ps
CPU time 307.78 seconds
Started May 02 04:05:45 PM PDT 24
Finished May 02 04:10:53 PM PDT 24
Peak memory 202372 kb
Host smart-2b3bf020-5428-40b8-a3f9-de28f2884db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167109699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2167109699
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3212416761
Short name T27
Test name
Test status
Simulation time 322677434784 ps
CPU time 198.84 seconds
Started May 02 04:05:45 PM PDT 24
Finished May 02 04:09:05 PM PDT 24
Peak memory 202324 kb
Host smart-a8b8f0c0-8a99-402a-893c-cd6c7c895b19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212416761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3212416761
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2949574354
Short name T98
Test name
Test status
Simulation time 164380976969 ps
CPU time 96.65 seconds
Started May 02 04:05:40 PM PDT 24
Finished May 02 04:07:18 PM PDT 24
Peak memory 202384 kb
Host smart-479e27f4-cf85-43f7-beca-3b740f9a9e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949574354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2949574354
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1867913730
Short name T398
Test name
Test status
Simulation time 321819476840 ps
CPU time 740.93 seconds
Started May 02 04:05:47 PM PDT 24
Finished May 02 04:18:08 PM PDT 24
Peak memory 202288 kb
Host smart-759d064b-e9c6-452d-83e9-11aaeb3a6d48
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867913730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1867913730
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1222672784
Short name T718
Test name
Test status
Simulation time 371241118620 ps
CPU time 867.24 seconds
Started May 02 04:05:47 PM PDT 24
Finished May 02 04:20:15 PM PDT 24
Peak memory 202300 kb
Host smart-54bfac3a-11e9-42a1-b39a-f2e9f5595396
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222672784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1222672784
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1336898815
Short name T87
Test name
Test status
Simulation time 586672618533 ps
CPU time 1049.77 seconds
Started May 02 04:05:48 PM PDT 24
Finished May 02 04:23:18 PM PDT 24
Peak memory 202236 kb
Host smart-8639ffab-bd5b-4d4c-a784-7b3064991f91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336898815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1336898815
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1276386231
Short name T324
Test name
Test status
Simulation time 82288340815 ps
CPU time 451.06 seconds
Started May 02 04:06:03 PM PDT 24
Finished May 02 04:13:35 PM PDT 24
Peak memory 202720 kb
Host smart-8f382bbe-ef08-46d7-8040-67e957ade144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276386231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1276386231
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4253531757
Short name T389
Test name
Test status
Simulation time 40934022934 ps
CPU time 25.01 seconds
Started May 02 04:06:01 PM PDT 24
Finished May 02 04:06:27 PM PDT 24
Peak memory 202112 kb
Host smart-facc8655-02da-4431-ad65-e17eb4123db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253531757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4253531757
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1176515395
Short name T26
Test name
Test status
Simulation time 5137444615 ps
CPU time 1.88 seconds
Started May 02 04:06:02 PM PDT 24
Finished May 02 04:06:05 PM PDT 24
Peak memory 202152 kb
Host smart-f12c6d51-05e0-487f-bf6e-3c37fcac4d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176515395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1176515395
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1773628056
Short name T360
Test name
Test status
Simulation time 5695599254 ps
CPU time 7.44 seconds
Started May 02 04:05:42 PM PDT 24
Finished May 02 04:05:50 PM PDT 24
Peak memory 202108 kb
Host smart-c3f27b91-4e16-489f-a06a-eada94f53934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773628056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1773628056
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3193661864
Short name T661
Test name
Test status
Simulation time 43378004390 ps
CPU time 103.75 seconds
Started May 02 04:06:03 PM PDT 24
Finished May 02 04:07:48 PM PDT 24
Peak memory 210748 kb
Host smart-e383a043-30ac-47ba-a621-ab79d96ef724
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193661864 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3193661864
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3377647878
Short name T788
Test name
Test status
Simulation time 464365738 ps
CPU time 1.61 seconds
Started May 02 04:06:16 PM PDT 24
Finished May 02 04:06:18 PM PDT 24
Peak memory 201964 kb
Host smart-f3684bbe-1e1b-4629-ba69-692733c0e551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377647878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3377647878
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2345084689
Short name T641
Test name
Test status
Simulation time 165554658453 ps
CPU time 42.87 seconds
Started May 02 04:06:10 PM PDT 24
Finished May 02 04:06:54 PM PDT 24
Peak memory 202280 kb
Host smart-a455e781-39bb-4708-9f19-3420b2f5d79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345084689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2345084689
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1372898339
Short name T440
Test name
Test status
Simulation time 321277813336 ps
CPU time 623.78 seconds
Started May 02 04:06:09 PM PDT 24
Finished May 02 04:16:33 PM PDT 24
Peak memory 202296 kb
Host smart-7e844f93-5475-4de7-8472-f2d7e168ed47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372898339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1372898339
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1584522149
Short name T589
Test name
Test status
Simulation time 158445462631 ps
CPU time 363.85 seconds
Started May 02 04:06:04 PM PDT 24
Finished May 02 04:12:08 PM PDT 24
Peak memory 202280 kb
Host smart-9d0ac653-0ac1-488f-b9ad-8c19ac42c128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584522149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1584522149
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.2032175898
Short name T625
Test name
Test status
Simulation time 329838527971 ps
CPU time 811.57 seconds
Started May 02 04:06:03 PM PDT 24
Finished May 02 04:19:35 PM PDT 24
Peak memory 202260 kb
Host smart-8b8ae03f-1d44-403d-9d30-1a2bd27eb66f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032175898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.2032175898
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2205957820
Short name T678
Test name
Test status
Simulation time 358150180380 ps
CPU time 91.86 seconds
Started May 02 04:06:10 PM PDT 24
Finished May 02 04:07:42 PM PDT 24
Peak memory 202340 kb
Host smart-fc95a28b-60ca-4301-a387-e162cc5c56de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205957820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2205957820
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2342095034
Short name T629
Test name
Test status
Simulation time 392640915737 ps
CPU time 209.51 seconds
Started May 02 04:06:09 PM PDT 24
Finished May 02 04:09:39 PM PDT 24
Peak memory 202288 kb
Host smart-af5a5225-d1de-4ef9-999c-287c686af61a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342095034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2342095034
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1891834290
Short name T32
Test name
Test status
Simulation time 111351722532 ps
CPU time 555.45 seconds
Started May 02 04:06:11 PM PDT 24
Finished May 02 04:15:27 PM PDT 24
Peak memory 202740 kb
Host smart-1763a722-3355-45b1-9dcc-96dafdec19fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891834290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1891834290
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1261958837
Short name T53
Test name
Test status
Simulation time 39561227706 ps
CPU time 33.73 seconds
Started May 02 04:06:10 PM PDT 24
Finished May 02 04:06:44 PM PDT 24
Peak memory 202108 kb
Host smart-9215a2c0-75e8-4aa4-9b49-8e7c1bd521eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261958837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1261958837
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1796836894
Short name T422
Test name
Test status
Simulation time 3923670124 ps
CPU time 1.88 seconds
Started May 02 04:06:12 PM PDT 24
Finished May 02 04:06:14 PM PDT 24
Peak memory 202136 kb
Host smart-f62f7379-f4fa-467e-ac8d-e4aa35295d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796836894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1796836894
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.501448406
Short name T335
Test name
Test status
Simulation time 5820877728 ps
CPU time 12.7 seconds
Started May 02 04:06:02 PM PDT 24
Finished May 02 04:06:15 PM PDT 24
Peak memory 202132 kb
Host smart-dcbb0f89-026f-4b1c-9cae-de05d2386799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501448406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.501448406
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3929845578
Short name T598
Test name
Test status
Simulation time 334221607795 ps
CPU time 63.72 seconds
Started May 02 04:06:14 PM PDT 24
Finished May 02 04:07:18 PM PDT 24
Peak memory 202324 kb
Host smart-378843b8-8913-4cc7-bd63-7e721eb2f2be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929845578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3929845578
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.982948464
Short name T22
Test name
Test status
Simulation time 571057540238 ps
CPU time 370.84 seconds
Started May 02 04:06:16 PM PDT 24
Finished May 02 04:12:27 PM PDT 24
Peak memory 219092 kb
Host smart-e677e529-b0cf-4e92-a647-aa7ed7d43120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982948464 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.982948464
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3572276297
Short name T713
Test name
Test status
Simulation time 522210146 ps
CPU time 0.96 seconds
Started May 02 04:06:29 PM PDT 24
Finished May 02 04:06:31 PM PDT 24
Peak memory 202032 kb
Host smart-fe6323a9-e3f4-4d42-8cdf-85a1db6d90df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572276297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3572276297
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3024825594
Short name T203
Test name
Test status
Simulation time 169106397462 ps
CPU time 361.11 seconds
Started May 02 04:06:23 PM PDT 24
Finished May 02 04:12:24 PM PDT 24
Peak memory 202300 kb
Host smart-277e7759-e60e-4a6b-a3a2-7ebfd5dc2d80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024825594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3024825594
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2458493768
Short name T133
Test name
Test status
Simulation time 326426813928 ps
CPU time 351.52 seconds
Started May 02 04:06:22 PM PDT 24
Finished May 02 04:12:14 PM PDT 24
Peak memory 202296 kb
Host smart-5afe6829-9063-412c-beb7-be1f50f3fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458493768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2458493768
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.122295008
Short name T665
Test name
Test status
Simulation time 170522177179 ps
CPU time 138.72 seconds
Started May 02 04:06:24 PM PDT 24
Finished May 02 04:08:43 PM PDT 24
Peak memory 202284 kb
Host smart-1ee34f7c-0e28-4ed3-aa6a-acfa8d0db9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122295008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.122295008
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.148124389
Short name T753
Test name
Test status
Simulation time 326681759891 ps
CPU time 763.29 seconds
Started May 02 04:06:22 PM PDT 24
Finished May 02 04:19:06 PM PDT 24
Peak memory 202280 kb
Host smart-1353c324-c294-424f-8c5c-8f83d10fece2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=148124389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.148124389
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2262970219
Short name T559
Test name
Test status
Simulation time 165844152422 ps
CPU time 100.05 seconds
Started May 02 04:06:18 PM PDT 24
Finished May 02 04:07:58 PM PDT 24
Peak memory 202284 kb
Host smart-83f467ac-3089-4735-8bc8-718ade4d9364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262970219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2262970219
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3160031200
Short name T1
Test name
Test status
Simulation time 327043382436 ps
CPU time 369.75 seconds
Started May 02 04:06:17 PM PDT 24
Finished May 02 04:12:27 PM PDT 24
Peak memory 202304 kb
Host smart-fe75c27b-fa1d-436a-806d-aee61a5645db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160031200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3160031200
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3134285158
Short name T770
Test name
Test status
Simulation time 385973111314 ps
CPU time 139.01 seconds
Started May 02 04:06:23 PM PDT 24
Finished May 02 04:08:43 PM PDT 24
Peak memory 202388 kb
Host smart-b1caa6d0-4ddd-44b5-af11-bd9707a53f1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134285158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3134285158
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.353323873
Short name T477
Test name
Test status
Simulation time 587663118800 ps
CPU time 769.26 seconds
Started May 02 04:06:22 PM PDT 24
Finished May 02 04:19:11 PM PDT 24
Peak memory 202316 kb
Host smart-e694d6c1-7e89-46be-b43a-cbcc6e2abf77
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353323873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.353323873
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1138573033
Short name T52
Test name
Test status
Simulation time 101032273941 ps
CPU time 318.1 seconds
Started May 02 04:06:26 PM PDT 24
Finished May 02 04:11:44 PM PDT 24
Peak memory 202660 kb
Host smart-a7fbea99-c50e-405f-95ba-d05360109a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138573033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1138573033
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.540361347
Short name T497
Test name
Test status
Simulation time 41704176067 ps
CPU time 22.7 seconds
Started May 02 04:06:28 PM PDT 24
Finished May 02 04:06:52 PM PDT 24
Peak memory 202140 kb
Host smart-0182247b-4de5-46c4-8ea3-7efb00c7387a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540361347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.540361347
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4217635511
Short name T695
Test name
Test status
Simulation time 5102928289 ps
CPU time 1.81 seconds
Started May 02 04:06:23 PM PDT 24
Finished May 02 04:06:26 PM PDT 24
Peak memory 202092 kb
Host smart-ea2bc937-320a-4227-89d1-da841ad0cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217635511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4217635511
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1001415999
Short name T349
Test name
Test status
Simulation time 5688698140 ps
CPU time 4.17 seconds
Started May 02 04:06:17 PM PDT 24
Finished May 02 04:06:22 PM PDT 24
Peak memory 202128 kb
Host smart-0ef4a34f-7d66-4746-ab64-072abee4caa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001415999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1001415999
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1397790590
Short name T256
Test name
Test status
Simulation time 316701559499 ps
CPU time 1021.53 seconds
Started May 02 04:06:29 PM PDT 24
Finished May 02 04:23:31 PM PDT 24
Peak memory 210892 kb
Host smart-44152266-8907-48ed-81d1-35d07a896d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397790590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1397790590
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3621784491
Short name T184
Test name
Test status
Simulation time 184254168966 ps
CPU time 243.25 seconds
Started May 02 04:06:28 PM PDT 24
Finished May 02 04:10:31 PM PDT 24
Peak memory 218576 kb
Host smart-d100cb43-6189-4047-b14a-519b8f02c778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621784491 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3621784491
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1837391947
Short name T562
Test name
Test status
Simulation time 304197782 ps
CPU time 0.78 seconds
Started May 02 04:06:39 PM PDT 24
Finished May 02 04:06:41 PM PDT 24
Peak memory 201996 kb
Host smart-c02f5bbc-053d-40d6-8720-4acb1e2f8c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837391947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1837391947
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4215982872
Short name T239
Test name
Test status
Simulation time 161267275195 ps
CPU time 97.34 seconds
Started May 02 04:06:36 PM PDT 24
Finished May 02 04:08:14 PM PDT 24
Peak memory 202296 kb
Host smart-40e5de53-2792-4175-8713-9bab6d8c0b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215982872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4215982872
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2095624237
Short name T489
Test name
Test status
Simulation time 168182066144 ps
CPU time 425.8 seconds
Started May 02 04:06:34 PM PDT 24
Finished May 02 04:13:41 PM PDT 24
Peak memory 202388 kb
Host smart-3346e582-4552-4bf2-8270-ae5c74f0150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095624237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2095624237
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.456063674
Short name T441
Test name
Test status
Simulation time 328687288279 ps
CPU time 193.35 seconds
Started May 02 04:06:36 PM PDT 24
Finished May 02 04:09:50 PM PDT 24
Peak memory 202312 kb
Host smart-13dcb46e-8053-4318-aaa9-7d11e78099f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=456063674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.456063674
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1594949828
Short name T438
Test name
Test status
Simulation time 489162596822 ps
CPU time 1137.73 seconds
Started May 02 04:06:35 PM PDT 24
Finished May 02 04:25:33 PM PDT 24
Peak memory 202400 kb
Host smart-fee464a9-a2ce-4764-a0a9-aed9b65d2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594949828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1594949828
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.731626250
Short name T587
Test name
Test status
Simulation time 165070447864 ps
CPU time 302.56 seconds
Started May 02 04:06:36 PM PDT 24
Finished May 02 04:11:39 PM PDT 24
Peak memory 202272 kb
Host smart-c6a161ad-5571-4cff-9c3c-d613ab64f5b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=731626250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fixe
d.731626250
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2375847546
Short name T433
Test name
Test status
Simulation time 186564918571 ps
CPU time 433.6 seconds
Started May 02 04:06:34 PM PDT 24
Finished May 02 04:13:49 PM PDT 24
Peak memory 202360 kb
Host smart-954a7584-5bd9-4282-bcdc-cdbea0d1e6ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375847546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2375847546
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.52657325
Short name T676
Test name
Test status
Simulation time 411870517993 ps
CPU time 242.76 seconds
Started May 02 04:06:35 PM PDT 24
Finished May 02 04:10:39 PM PDT 24
Peak memory 202284 kb
Host smart-33803899-421b-4bbb-93b1-359f98d3dae4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52657325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
dc_ctrl_filters_wakeup_fixed.52657325
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2385018542
Short name T3
Test name
Test status
Simulation time 111348693406 ps
CPU time 452.18 seconds
Started May 02 04:06:40 PM PDT 24
Finished May 02 04:14:14 PM PDT 24
Peak memory 202756 kb
Host smart-edd3aea0-60bf-4deb-be85-81c2ba33f20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385018542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2385018542
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.1777246805
Short name T472
Test name
Test status
Simulation time 33000822474 ps
CPU time 78.62 seconds
Started May 02 04:06:40 PM PDT 24
Finished May 02 04:08:00 PM PDT 24
Peak memory 202080 kb
Host smart-f8740bd9-387e-4358-bcc8-0f7d4f98e350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777246805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.1777246805
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3890007823
Short name T548
Test name
Test status
Simulation time 3154470474 ps
CPU time 7.66 seconds
Started May 02 04:06:41 PM PDT 24
Finished May 02 04:06:50 PM PDT 24
Peak memory 202124 kb
Host smart-103fab43-890b-434c-8e6d-371ebc64bda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890007823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3890007823
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.282837682
Short name T791
Test name
Test status
Simulation time 6079049522 ps
CPU time 15.79 seconds
Started May 02 04:06:28 PM PDT 24
Finished May 02 04:06:44 PM PDT 24
Peak memory 202108 kb
Host smart-954853b2-10e0-448f-82a3-aed0a9dc2e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282837682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.282837682
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2978792057
Short name T286
Test name
Test status
Simulation time 214126782904 ps
CPU time 72.22 seconds
Started May 02 04:06:40 PM PDT 24
Finished May 02 04:07:53 PM PDT 24
Peak memory 202320 kb
Host smart-591dc957-07e0-477d-9a5b-4b205d2a37e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978792057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2978792057
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3321887352
Short name T650
Test name
Test status
Simulation time 216071209995 ps
CPU time 208.37 seconds
Started May 02 04:06:42 PM PDT 24
Finished May 02 04:10:11 PM PDT 24
Peak memory 218832 kb
Host smart-cc993a4d-c611-4532-8db6-acc5b13ecb63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321887352 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3321887352
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.4107544105
Short name T553
Test name
Test status
Simulation time 318487321 ps
CPU time 1.23 seconds
Started May 02 04:07:05 PM PDT 24
Finished May 02 04:07:06 PM PDT 24
Peak memory 201964 kb
Host smart-1e12b2fe-663f-43a4-befe-6734795cd4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107544105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.4107544105
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.912454007
Short name T123
Test name
Test status
Simulation time 164170652013 ps
CPU time 8.53 seconds
Started May 02 04:06:52 PM PDT 24
Finished May 02 04:07:02 PM PDT 24
Peak memory 202320 kb
Host smart-2ea88b59-b717-452e-a8ef-5d3a1832b085
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912454007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.912454007
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2735882050
Short name T537
Test name
Test status
Simulation time 494496848941 ps
CPU time 1223.19 seconds
Started May 02 04:06:45 PM PDT 24
Finished May 02 04:27:09 PM PDT 24
Peak memory 202384 kb
Host smart-04392000-284b-4925-af99-de25f10d664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735882050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2735882050
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2089126037
Short name T556
Test name
Test status
Simulation time 321028360777 ps
CPU time 717.19 seconds
Started May 02 04:06:45 PM PDT 24
Finished May 02 04:18:43 PM PDT 24
Peak memory 202220 kb
Host smart-5021e8cd-88fc-4c41-bb50-7e4272e06f65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089126037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2089126037
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.2706461140
Short name T336
Test name
Test status
Simulation time 327869875415 ps
CPU time 126.74 seconds
Started May 02 04:06:41 PM PDT 24
Finished May 02 04:08:49 PM PDT 24
Peak memory 202264 kb
Host smart-3c1e62b6-5c08-4481-b80e-9f645a387d29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706461140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.2706461140
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3583705362
Short name T128
Test name
Test status
Simulation time 612594206626 ps
CPU time 340.74 seconds
Started May 02 04:06:54 PM PDT 24
Finished May 02 04:12:35 PM PDT 24
Peak memory 202324 kb
Host smart-4fc3019c-0189-4877-893f-e694bf7d5350
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583705362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3583705362
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1590041097
Short name T524
Test name
Test status
Simulation time 597860599353 ps
CPU time 284.35 seconds
Started May 02 04:06:53 PM PDT 24
Finished May 02 04:11:38 PM PDT 24
Peak memory 202316 kb
Host smart-0e58914f-b5a3-4cfa-bc30-575f839a50b1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590041097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1590041097
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3975651999
Short name T570
Test name
Test status
Simulation time 112893607613 ps
CPU time 632.76 seconds
Started May 02 04:06:58 PM PDT 24
Finished May 02 04:17:31 PM PDT 24
Peak memory 202732 kb
Host smart-a7c4ff31-ed1b-442e-8efa-ebd0975a5a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975651999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3975651999
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.2250852119
Short name T368
Test name
Test status
Simulation time 28367284667 ps
CPU time 6.3 seconds
Started May 02 04:06:59 PM PDT 24
Finished May 02 04:07:05 PM PDT 24
Peak memory 202132 kb
Host smart-70fd4038-d013-4110-a4f0-a9480552d7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250852119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.2250852119
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.530185605
Short name T659
Test name
Test status
Simulation time 2812852359 ps
CPU time 2.24 seconds
Started May 02 04:06:53 PM PDT 24
Finished May 02 04:06:56 PM PDT 24
Peak memory 202140 kb
Host smart-0b1ffc5c-1d6d-4197-a85e-07f076b648c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530185605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.530185605
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2129792138
Short name T652
Test name
Test status
Simulation time 6046309522 ps
CPU time 15.34 seconds
Started May 02 04:06:40 PM PDT 24
Finished May 02 04:06:57 PM PDT 24
Peak memory 202116 kb
Host smart-407f4e03-0a87-4abe-8920-a0e3aa7b1ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129792138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2129792138
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3279838009
Short name T287
Test name
Test status
Simulation time 378570675550 ps
CPU time 914.08 seconds
Started May 02 04:07:05 PM PDT 24
Finished May 02 04:22:20 PM PDT 24
Peak memory 202276 kb
Host smart-56895930-d127-42c4-81f4-b25471df3627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279838009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3279838009
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.719142991
Short name T249
Test name
Test status
Simulation time 357479212849 ps
CPU time 313.67 seconds
Started May 02 04:06:58 PM PDT 24
Finished May 02 04:12:13 PM PDT 24
Peak memory 210988 kb
Host smart-e4b9bb6f-5fe0-4844-8383-39f8ff9151b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719142991 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.719142991
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.777404336
Short name T781
Test name
Test status
Simulation time 341842941 ps
CPU time 0.79 seconds
Started May 02 04:07:22 PM PDT 24
Finished May 02 04:07:24 PM PDT 24
Peak memory 201996 kb
Host smart-01c7ef9a-82ba-4a1e-a9f4-b91fd10a4d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777404336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.777404336
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.649443125
Short name T196
Test name
Test status
Simulation time 565110250766 ps
CPU time 1222.77 seconds
Started May 02 04:07:17 PM PDT 24
Finished May 02 04:27:41 PM PDT 24
Peak memory 202380 kb
Host smart-c9249b00-0b85-4571-912a-39d2e5013154
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649443125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gati
ng.649443125
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1934688455
Short name T206
Test name
Test status
Simulation time 171556441032 ps
CPU time 114.11 seconds
Started May 02 04:07:19 PM PDT 24
Finished May 02 04:09:14 PM PDT 24
Peak memory 202324 kb
Host smart-f19ec087-d562-4275-86b9-0432c3f2aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934688455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1934688455
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.364751419
Short name T508
Test name
Test status
Simulation time 324223710911 ps
CPU time 204.37 seconds
Started May 02 04:07:08 PM PDT 24
Finished May 02 04:10:32 PM PDT 24
Peak memory 202324 kb
Host smart-0a739226-9528-4f22-9de3-2a86f556e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364751419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.364751419
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2352357789
Short name T369
Test name
Test status
Simulation time 328846875161 ps
CPU time 831.63 seconds
Started May 02 04:07:04 PM PDT 24
Finished May 02 04:20:57 PM PDT 24
Peak memory 202272 kb
Host smart-524ccf42-3ad9-4231-89e4-142d9e9b47ae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352357789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2352357789
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.183666170
Short name T415
Test name
Test status
Simulation time 161138079475 ps
CPU time 68.29 seconds
Started May 02 04:07:06 PM PDT 24
Finished May 02 04:08:14 PM PDT 24
Peak memory 202256 kb
Host smart-e04c67d3-4a05-4da6-b438-72820e3d1048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183666170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.183666170
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3582386823
Short name T420
Test name
Test status
Simulation time 325980382149 ps
CPU time 186.96 seconds
Started May 02 04:07:06 PM PDT 24
Finished May 02 04:10:13 PM PDT 24
Peak memory 202236 kb
Host smart-056d54ca-03a3-4b22-ad27-a0469fa5d7cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582386823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3582386823
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4181421553
Short name T730
Test name
Test status
Simulation time 421510939644 ps
CPU time 907.42 seconds
Started May 02 04:07:10 PM PDT 24
Finished May 02 04:22:18 PM PDT 24
Peak memory 202332 kb
Host smart-1ad4f498-1e69-4ac2-bbab-16ef6a48e002
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181421553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4181421553
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.259824853
Short name T371
Test name
Test status
Simulation time 583574788241 ps
CPU time 269.54 seconds
Started May 02 04:07:10 PM PDT 24
Finished May 02 04:11:40 PM PDT 24
Peak memory 202312 kb
Host smart-209d3e6a-a542-449d-914e-4a370fc781f8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259824853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.259824853
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1163538688
Short name T627
Test name
Test status
Simulation time 130634650963 ps
CPU time 549.81 seconds
Started May 02 04:07:20 PM PDT 24
Finished May 02 04:16:30 PM PDT 24
Peak memory 202672 kb
Host smart-7cea15bd-e2cf-4787-af92-a0e35ea9ab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163538688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1163538688
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.187695376
Short name T564
Test name
Test status
Simulation time 36909424519 ps
CPU time 9.14 seconds
Started May 02 04:07:18 PM PDT 24
Finished May 02 04:07:28 PM PDT 24
Peak memory 202116 kb
Host smart-0f390d02-6407-4072-a094-1809cbbf8dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187695376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.187695376
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2987384355
Short name T402
Test name
Test status
Simulation time 4330231249 ps
CPU time 4.34 seconds
Started May 02 04:07:17 PM PDT 24
Finished May 02 04:07:22 PM PDT 24
Peak memory 202136 kb
Host smart-61759d33-bdea-4c26-bddc-fa5879f03ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987384355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2987384355
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.866364750
Short name T354
Test name
Test status
Simulation time 5832743866 ps
CPU time 14.06 seconds
Started May 02 04:07:07 PM PDT 24
Finished May 02 04:07:21 PM PDT 24
Peak memory 202136 kb
Host smart-7d64de7f-359c-4a88-be8d-71f7d1bbc255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866364750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.866364750
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3650989776
Short name T775
Test name
Test status
Simulation time 206942539100 ps
CPU time 46.66 seconds
Started May 02 04:07:26 PM PDT 24
Finished May 02 04:08:13 PM PDT 24
Peak memory 202316 kb
Host smart-3e2dbf7d-c0a0-46f6-bf4b-92ed0b48ae30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650989776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3650989776
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1659969895
Short name T501
Test name
Test status
Simulation time 75528140791 ps
CPU time 55.89 seconds
Started May 02 04:07:26 PM PDT 24
Finished May 02 04:08:22 PM PDT 24
Peak memory 210900 kb
Host smart-19eb6441-4291-45b5-a7dd-334715d80f40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659969895 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1659969895
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3005251722
Short name T586
Test name
Test status
Simulation time 413293048 ps
CPU time 1.58 seconds
Started May 02 04:00:24 PM PDT 24
Finished May 02 04:00:26 PM PDT 24
Peak memory 201992 kb
Host smart-d1acb376-0acc-40cb-815a-2098c07e06e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005251722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3005251722
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1221224040
Short name T234
Test name
Test status
Simulation time 538641426014 ps
CPU time 1092.64 seconds
Started May 02 04:00:24 PM PDT 24
Finished May 02 04:18:37 PM PDT 24
Peak memory 202280 kb
Host smart-857c1fec-3665-4d7c-bb1d-ba3f0a202d9c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221224040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1221224040
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2617732134
Short name T724
Test name
Test status
Simulation time 502010468640 ps
CPU time 286.69 seconds
Started May 02 04:00:25 PM PDT 24
Finished May 02 04:05:13 PM PDT 24
Peak memory 202308 kb
Host smart-a163a9c1-bed1-4046-b68c-75afde39407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617732134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2617732134
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1252852931
Short name T268
Test name
Test status
Simulation time 327239725186 ps
CPU time 196.44 seconds
Started May 02 04:00:18 PM PDT 24
Finished May 02 04:03:35 PM PDT 24
Peak memory 202312 kb
Host smart-a274a9e4-8607-4fbc-bf5a-69fd0399f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252852931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1252852931
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1159378669
Short name T749
Test name
Test status
Simulation time 489738382712 ps
CPU time 217.1 seconds
Started May 02 04:00:21 PM PDT 24
Finished May 02 04:03:58 PM PDT 24
Peak memory 202300 kb
Host smart-655dd7c5-9150-43b3-a3cd-c64290f5413e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159378669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1159378669
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.387000855
Short name T159
Test name
Test status
Simulation time 160931058751 ps
CPU time 92.02 seconds
Started May 02 04:00:18 PM PDT 24
Finished May 02 04:01:51 PM PDT 24
Peak memory 202316 kb
Host smart-a9ff53e4-9004-4518-8254-045cbfa27bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387000855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.387000855
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1437050756
Short name T761
Test name
Test status
Simulation time 323949098466 ps
CPU time 50.84 seconds
Started May 02 04:00:20 PM PDT 24
Finished May 02 04:01:11 PM PDT 24
Peak memory 202296 kb
Host smart-40b440bf-14ad-4216-ad27-4fe76c556699
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437050756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1437050756
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2635852449
Short name T127
Test name
Test status
Simulation time 505097183121 ps
CPU time 1208.66 seconds
Started May 02 04:00:25 PM PDT 24
Finished May 02 04:20:35 PM PDT 24
Peak memory 202340 kb
Host smart-125ef218-e65c-41d0-8ae8-4914e746b294
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635852449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2635852449
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3940360720
Short name T528
Test name
Test status
Simulation time 594330325414 ps
CPU time 1435.75 seconds
Started May 02 04:00:26 PM PDT 24
Finished May 02 04:24:23 PM PDT 24
Peak memory 202236 kb
Host smart-7ad00fb9-32f3-4f85-be17-8e3c88d9783b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940360720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3940360720
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3582498326
Short name T191
Test name
Test status
Simulation time 87468716877 ps
CPU time 434.92 seconds
Started May 02 04:00:25 PM PDT 24
Finished May 02 04:07:40 PM PDT 24
Peak memory 202672 kb
Host smart-2cbf9fc7-61b7-43a2-b36a-f779dcfc19e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582498326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3582498326
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.278385676
Short name T701
Test name
Test status
Simulation time 31051411456 ps
CPU time 19.8 seconds
Started May 02 04:00:25 PM PDT 24
Finished May 02 04:00:46 PM PDT 24
Peak memory 202116 kb
Host smart-cae455d6-dade-40d7-8337-2c339cc5e031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278385676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.278385676
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.2076580999
Short name T732
Test name
Test status
Simulation time 3634920729 ps
CPU time 8.63 seconds
Started May 02 04:00:26 PM PDT 24
Finished May 02 04:00:36 PM PDT 24
Peak memory 202088 kb
Host smart-569210ae-863c-4b13-a98d-fbcd6dc6220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076580999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.2076580999
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3616475197
Short name T80
Test name
Test status
Simulation time 8018111520 ps
CPU time 17.72 seconds
Started May 02 04:00:26 PM PDT 24
Finished May 02 04:00:45 PM PDT 24
Peak memory 218820 kb
Host smart-8444d77f-19ce-4f07-8c46-bd6b3119f346
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616475197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3616475197
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1813207297
Short name T410
Test name
Test status
Simulation time 5842103300 ps
CPU time 7.93 seconds
Started May 02 04:00:19 PM PDT 24
Finished May 02 04:00:28 PM PDT 24
Peak memory 202128 kb
Host smart-d21db1ba-dda7-432c-ab09-7fb8e026159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813207297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1813207297
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.687064113
Short name T288
Test name
Test status
Simulation time 150508894638 ps
CPU time 209.31 seconds
Started May 02 04:00:28 PM PDT 24
Finished May 02 04:03:58 PM PDT 24
Peak memory 212024 kb
Host smart-23d0822a-395d-43f2-a2fc-0fe479974324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687064113 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.687064113
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2585925680
Short name T745
Test name
Test status
Simulation time 375004022 ps
CPU time 1.51 seconds
Started May 02 04:07:36 PM PDT 24
Finished May 02 04:07:39 PM PDT 24
Peak memory 201964 kb
Host smart-6a578d1f-cbaf-4ea7-a7ac-c02a485c5832
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585925680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2585925680
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3634385073
Short name T220
Test name
Test status
Simulation time 320272040925 ps
CPU time 757.39 seconds
Started May 02 04:07:27 PM PDT 24
Finished May 02 04:20:05 PM PDT 24
Peak memory 202392 kb
Host smart-e3a55140-9bb2-4144-9643-72eeaabb1bc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634385073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3634385073
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.1633623070
Short name T13
Test name
Test status
Simulation time 163516655854 ps
CPU time 377.39 seconds
Started May 02 04:07:23 PM PDT 24
Finished May 02 04:13:42 PM PDT 24
Peak memory 202292 kb
Host smart-3198b43b-740a-4ec5-a1e6-946b168818c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633623070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.1633623070
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2947673383
Short name T569
Test name
Test status
Simulation time 164398400912 ps
CPU time 176.5 seconds
Started May 02 04:07:26 PM PDT 24
Finished May 02 04:10:23 PM PDT 24
Peak memory 202332 kb
Host smart-5d9c65f5-8c46-4a5d-bbd0-1810410708b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947673383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2947673383
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.1751347848
Short name T426
Test name
Test status
Simulation time 168756098861 ps
CPU time 187.39 seconds
Started May 02 04:07:23 PM PDT 24
Finished May 02 04:10:31 PM PDT 24
Peak memory 202300 kb
Host smart-d86774fb-c4c6-4fba-a292-3e2d668e6f8a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751347848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.1751347848
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.3940837123
Short name T590
Test name
Test status
Simulation time 171106975976 ps
CPU time 388.74 seconds
Started May 02 04:07:27 PM PDT 24
Finished May 02 04:13:57 PM PDT 24
Peak memory 202344 kb
Host smart-760e4ffb-e772-41cf-8a2d-08677143c04c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940837123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.3940837123
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.99516649
Short name T409
Test name
Test status
Simulation time 405267192582 ps
CPU time 248.77 seconds
Started May 02 04:07:29 PM PDT 24
Finished May 02 04:11:39 PM PDT 24
Peak memory 202300 kb
Host smart-bbef70f5-83c6-4e6b-b1a1-c69a41e7a092
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99516649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.a
dc_ctrl_filters_wakeup_fixed.99516649
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2740258449
Short name T55
Test name
Test status
Simulation time 77961359441 ps
CPU time 412.55 seconds
Started May 02 04:07:28 PM PDT 24
Finished May 02 04:14:21 PM PDT 24
Peak memory 202720 kb
Host smart-eea9e2e6-76d0-4e45-92ed-a17abc77e46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740258449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2740258449
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1453938544
Short name T554
Test name
Test status
Simulation time 43495980972 ps
CPU time 18.22 seconds
Started May 02 04:07:29 PM PDT 24
Finished May 02 04:07:48 PM PDT 24
Peak memory 202108 kb
Host smart-0bd82220-e41a-4815-9f57-84942f70139c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453938544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1453938544
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.516318207
Short name T432
Test name
Test status
Simulation time 4067956304 ps
CPU time 5.78 seconds
Started May 02 04:07:29 PM PDT 24
Finished May 02 04:07:36 PM PDT 24
Peak memory 202144 kb
Host smart-0b513e57-7979-409e-acbe-c0c6a44668ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516318207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.516318207
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1667423503
Short name T681
Test name
Test status
Simulation time 5866116565 ps
CPU time 7.38 seconds
Started May 02 04:07:24 PM PDT 24
Finished May 02 04:07:32 PM PDT 24
Peak memory 202108 kb
Host smart-5d3e8664-62af-449f-9992-55a758d69bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667423503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1667423503
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1978087928
Short name T525
Test name
Test status
Simulation time 368667994471 ps
CPU time 404.93 seconds
Started May 02 04:07:34 PM PDT 24
Finished May 02 04:14:19 PM PDT 24
Peak memory 202392 kb
Host smart-ec0c01c6-d1b6-46e5-809f-2c3b6707cb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978087928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1978087928
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.4120530411
Short name T21
Test name
Test status
Simulation time 290559812098 ps
CPU time 301.99 seconds
Started May 02 04:07:29 PM PDT 24
Finished May 02 04:12:32 PM PDT 24
Peak memory 211072 kb
Host smart-718d3924-6058-4574-9d4d-6c37a6c91505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120530411 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.4120530411
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.435275149
Short name T535
Test name
Test status
Simulation time 311804407 ps
CPU time 1.28 seconds
Started May 02 04:07:45 PM PDT 24
Finished May 02 04:07:47 PM PDT 24
Peak memory 201980 kb
Host smart-ebf022bc-3eaf-4acc-9bf6-b543327f8924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435275149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.435275149
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1660441975
Short name T664
Test name
Test status
Simulation time 272092946453 ps
CPU time 504.19 seconds
Started May 02 04:07:41 PM PDT 24
Finished May 02 04:16:06 PM PDT 24
Peak memory 202292 kb
Host smart-daec6996-fe95-49dd-adb2-75f3298facc8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660441975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1660441975
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.532613827
Short name T223
Test name
Test status
Simulation time 327126962862 ps
CPU time 802.32 seconds
Started May 02 04:07:39 PM PDT 24
Finished May 02 04:21:02 PM PDT 24
Peak memory 202264 kb
Host smart-0b7ce6fd-5cba-49a5-affa-a82f89371fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532613827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.532613827
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2416486091
Short name T254
Test name
Test status
Simulation time 492603398455 ps
CPU time 148.32 seconds
Started May 02 04:07:33 PM PDT 24
Finished May 02 04:10:02 PM PDT 24
Peak memory 201444 kb
Host smart-c98c0166-3542-4fbf-8486-0a5229f31369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416486091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2416486091
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.4174271766
Short name T478
Test name
Test status
Simulation time 323998140718 ps
CPU time 747.96 seconds
Started May 02 04:07:39 PM PDT 24
Finished May 02 04:20:09 PM PDT 24
Peak memory 202312 kb
Host smart-5ad31056-5b18-4629-817b-c1dc6ba2e9db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174271766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.4174271766
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4117035172
Short name T716
Test name
Test status
Simulation time 166022944042 ps
CPU time 380.68 seconds
Started May 02 04:07:35 PM PDT 24
Finished May 02 04:13:56 PM PDT 24
Peak memory 202324 kb
Host smart-7dcc26a8-a41b-4639-93c1-fb7af4bb9a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117035172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4117035172
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.653413387
Short name T694
Test name
Test status
Simulation time 324833900147 ps
CPU time 723.28 seconds
Started May 02 04:07:35 PM PDT 24
Finished May 02 04:19:39 PM PDT 24
Peak memory 202264 kb
Host smart-9fd6a071-8354-47a7-831f-f8f6bd043ac4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=653413387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.653413387
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.41343802
Short name T655
Test name
Test status
Simulation time 187949005470 ps
CPU time 128.56 seconds
Started May 02 04:07:34 PM PDT 24
Finished May 02 04:09:43 PM PDT 24
Peak memory 202384 kb
Host smart-93a5c6c3-3eef-4fe6-97e1-c4662fd967ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41343802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_w
akeup.41343802
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3667581539
Short name T481
Test name
Test status
Simulation time 204991660271 ps
CPU time 123.26 seconds
Started May 02 04:07:35 PM PDT 24
Finished May 02 04:09:39 PM PDT 24
Peak memory 202256 kb
Host smart-df0df202-44a3-4e26-a361-8eb69105e821
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667581539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3667581539
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2327373473
Short name T490
Test name
Test status
Simulation time 107737748575 ps
CPU time 566.77 seconds
Started May 02 04:07:41 PM PDT 24
Finished May 02 04:17:08 PM PDT 24
Peak memory 202664 kb
Host smart-2e67c760-0d29-4624-a18f-1fd746ca158d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327373473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2327373473
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.976754682
Short name T550
Test name
Test status
Simulation time 23921947810 ps
CPU time 52.64 seconds
Started May 02 04:07:40 PM PDT 24
Finished May 02 04:08:34 PM PDT 24
Peak memory 202088 kb
Host smart-fb584b5d-14fe-412c-ad7c-f69415466480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976754682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.976754682
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3917115847
Short name T566
Test name
Test status
Simulation time 5330852239 ps
CPU time 6.9 seconds
Started May 02 04:07:39 PM PDT 24
Finished May 02 04:07:47 PM PDT 24
Peak memory 202096 kb
Host smart-9bade898-ec95-4518-8d92-0926e1a32aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917115847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3917115847
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1712303266
Short name T666
Test name
Test status
Simulation time 5763973301 ps
CPU time 9.41 seconds
Started May 02 04:07:34 PM PDT 24
Finished May 02 04:07:44 PM PDT 24
Peak memory 202084 kb
Host smart-2857ec5f-506f-4efd-8e52-02c983dce30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712303266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1712303266
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3915668341
Short name T293
Test name
Test status
Simulation time 270982629328 ps
CPU time 543.04 seconds
Started May 02 04:07:47 PM PDT 24
Finished May 02 04:16:50 PM PDT 24
Peak memory 202748 kb
Host smart-26c2830d-eeee-46c1-9832-cee3b650161c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915668341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3915668341
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1704751551
Short name T178
Test name
Test status
Simulation time 99807559935 ps
CPU time 122.31 seconds
Started May 02 04:07:46 PM PDT 24
Finished May 02 04:09:49 PM PDT 24
Peak memory 210972 kb
Host smart-2ce2e849-2577-42b5-91cb-93843273f73c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704751551 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1704751551
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1635498468
Short name T567
Test name
Test status
Simulation time 461178223 ps
CPU time 0.92 seconds
Started May 02 04:08:00 PM PDT 24
Finished May 02 04:08:01 PM PDT 24
Peak memory 201996 kb
Host smart-bca5c834-433e-44b5-af67-07648171645b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635498468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1635498468
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.924114980
Short name T233
Test name
Test status
Simulation time 327756285374 ps
CPU time 741.52 seconds
Started May 02 04:07:47 PM PDT 24
Finished May 02 04:20:09 PM PDT 24
Peak memory 202260 kb
Host smart-09376fc5-4c2c-4533-afe0-8dcfbd9a7e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924114980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.924114980
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3832602223
Short name T31
Test name
Test status
Simulation time 325928362435 ps
CPU time 129.82 seconds
Started May 02 04:07:52 PM PDT 24
Finished May 02 04:10:02 PM PDT 24
Peak memory 202300 kb
Host smart-5a487bf7-0c51-41ec-980f-d8854cbc1cc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832602223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3832602223
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3884548832
Short name T755
Test name
Test status
Simulation time 327863944085 ps
CPU time 771.38 seconds
Started May 02 04:07:47 PM PDT 24
Finished May 02 04:20:39 PM PDT 24
Peak memory 202312 kb
Host smart-b3aef108-65d1-4b8e-8094-dd4ce0e67868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884548832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3884548832
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2990545889
Short name T370
Test name
Test status
Simulation time 165063417049 ps
CPU time 36.48 seconds
Started May 02 04:07:47 PM PDT 24
Finished May 02 04:08:24 PM PDT 24
Peak memory 202248 kb
Host smart-2ac143bc-92b9-4b9e-ae4a-24674f5b0446
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990545889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2990545889
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.4057525709
Short name T689
Test name
Test status
Simulation time 201832063724 ps
CPU time 259.64 seconds
Started May 02 04:07:55 PM PDT 24
Finished May 02 04:12:15 PM PDT 24
Peak memory 202360 kb
Host smart-c23a4a8e-b674-430f-8721-b7942fd4c0e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057525709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.4057525709
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.1606279957
Short name T323
Test name
Test status
Simulation time 71950495771 ps
CPU time 355.3 seconds
Started May 02 04:07:52 PM PDT 24
Finished May 02 04:13:48 PM PDT 24
Peak memory 202732 kb
Host smart-ecf86c42-edbe-4fe2-a423-7991454bb199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606279957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.1606279957
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1850058239
Short name T631
Test name
Test status
Simulation time 23025697657 ps
CPU time 7.69 seconds
Started May 02 04:07:52 PM PDT 24
Finished May 02 04:08:00 PM PDT 24
Peak memory 202080 kb
Host smart-ff4155df-01b8-4f84-b0c9-edc02ac94671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850058239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1850058239
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3622726981
Short name T362
Test name
Test status
Simulation time 3472613614 ps
CPU time 4.54 seconds
Started May 02 04:07:52 PM PDT 24
Finished May 02 04:07:57 PM PDT 24
Peak memory 202128 kb
Host smart-7ecd2006-60bc-4ed9-a138-4a721dfadf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622726981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3622726981
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.2977124086
Short name T683
Test name
Test status
Simulation time 5781063147 ps
CPU time 14.85 seconds
Started May 02 04:07:48 PM PDT 24
Finished May 02 04:08:04 PM PDT 24
Peak memory 202116 kb
Host smart-268c60b5-b4af-4e23-9ff1-fb807c3ecdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977124086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.2977124086
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3261697855
Short name T709
Test name
Test status
Simulation time 704792016671 ps
CPU time 399.28 seconds
Started May 02 04:08:00 PM PDT 24
Finished May 02 04:14:40 PM PDT 24
Peak memory 202368 kb
Host smart-7adc4bed-8c8f-4bf3-aaf2-e3b8b4aaf4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261697855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3261697855
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3298108109
Short name T634
Test name
Test status
Simulation time 429090198 ps
CPU time 0.87 seconds
Started May 02 04:08:12 PM PDT 24
Finished May 02 04:08:13 PM PDT 24
Peak memory 202024 kb
Host smart-039b7db2-a25b-4b91-b230-bac242dd7fbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298108109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3298108109
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.720111124
Short name T563
Test name
Test status
Simulation time 188608759264 ps
CPU time 407.2 seconds
Started May 02 04:08:05 PM PDT 24
Finished May 02 04:14:53 PM PDT 24
Peak memory 202316 kb
Host smart-c7086a5c-6a5c-45f3-abcf-c0468c764046
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720111124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.720111124
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.2577338776
Short name T493
Test name
Test status
Simulation time 534522992513 ps
CPU time 1204.55 seconds
Started May 02 04:08:05 PM PDT 24
Finished May 02 04:28:11 PM PDT 24
Peak memory 202264 kb
Host smart-1dd123d2-ccc0-4387-977d-09efc0efe2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577338776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.2577338776
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.878996071
Short name T84
Test name
Test status
Simulation time 330798523318 ps
CPU time 187.56 seconds
Started May 02 04:07:58 PM PDT 24
Finished May 02 04:11:06 PM PDT 24
Peak memory 202292 kb
Host smart-dac95789-faa7-4a1c-afee-2e021a59bd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878996071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.878996071
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.633637565
Short name T447
Test name
Test status
Simulation time 167542024317 ps
CPU time 205.6 seconds
Started May 02 04:08:05 PM PDT 24
Finished May 02 04:11:32 PM PDT 24
Peak memory 202308 kb
Host smart-51f6fc68-f86a-43d5-a4cf-dcf1998d20b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=633637565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.633637565
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1702866354
Short name T406
Test name
Test status
Simulation time 163217118840 ps
CPU time 205.18 seconds
Started May 02 04:07:59 PM PDT 24
Finished May 02 04:11:25 PM PDT 24
Peak memory 202292 kb
Host smart-2c778dc8-6911-4717-ab7c-c3dfbc9d69cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702866354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1702866354
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2565653984
Short name T542
Test name
Test status
Simulation time 167040775911 ps
CPU time 189.07 seconds
Started May 02 04:08:00 PM PDT 24
Finished May 02 04:11:10 PM PDT 24
Peak memory 202248 kb
Host smart-a0897ff3-c14e-4e41-9dc8-a62faa59eda8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565653984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2565653984
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.4285701008
Short name T153
Test name
Test status
Simulation time 373934033400 ps
CPU time 213.14 seconds
Started May 02 04:08:06 PM PDT 24
Finished May 02 04:11:40 PM PDT 24
Peak memory 202268 kb
Host smart-63cacd36-db0e-4d98-b1cd-f98d36828c00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285701008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.4285701008
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1861158661
Short name T680
Test name
Test status
Simulation time 393326278055 ps
CPU time 443.59 seconds
Started May 02 04:08:05 PM PDT 24
Finished May 02 04:15:29 PM PDT 24
Peak memory 202312 kb
Host smart-67b71c45-50ef-4df8-80f2-ea9b01d07559
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861158661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1861158661
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.4138768648
Short name T181
Test name
Test status
Simulation time 82469299306 ps
CPU time 304.62 seconds
Started May 02 04:08:13 PM PDT 24
Finished May 02 04:13:18 PM PDT 24
Peak memory 202664 kb
Host smart-66b53ed1-0474-4b8b-9ad7-4b27cfd18f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138768648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.4138768648
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2151387855
Short name T393
Test name
Test status
Simulation time 43848536229 ps
CPU time 54.49 seconds
Started May 02 04:08:14 PM PDT 24
Finished May 02 04:09:09 PM PDT 24
Peak memory 202156 kb
Host smart-edfc9b20-fb31-4a74-972b-a6d065b52941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151387855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2151387855
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.1428050834
Short name T654
Test name
Test status
Simulation time 5481713836 ps
CPU time 1.47 seconds
Started May 02 04:08:06 PM PDT 24
Finished May 02 04:08:09 PM PDT 24
Peak memory 202136 kb
Host smart-a8303217-3998-462e-8b05-23fdc8db93ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428050834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.1428050834
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.933419370
Short name T7
Test name
Test status
Simulation time 6045402020 ps
CPU time 4.97 seconds
Started May 02 04:08:00 PM PDT 24
Finished May 02 04:08:05 PM PDT 24
Peak memory 202160 kb
Host smart-8b894861-a03b-421b-a2b7-c9d306d76ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933419370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.933419370
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.188227153
Short name T425
Test name
Test status
Simulation time 66152064747 ps
CPU time 248.89 seconds
Started May 02 04:08:10 PM PDT 24
Finished May 02 04:12:20 PM PDT 24
Peak memory 202652 kb
Host smart-b85652d0-ee89-41ac-9119-29e35f3fe5cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188227153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
188227153
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3120190491
Short name T25
Test name
Test status
Simulation time 188743254234 ps
CPU time 170.18 seconds
Started May 02 04:08:13 PM PDT 24
Finished May 02 04:11:04 PM PDT 24
Peak memory 218764 kb
Host smart-57d54c1b-06c0-4ef6-af75-98112657b43e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120190491 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3120190491
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1683384296
Short name T522
Test name
Test status
Simulation time 429612928 ps
CPU time 1.6 seconds
Started May 02 04:08:26 PM PDT 24
Finished May 02 04:08:28 PM PDT 24
Peak memory 202052 kb
Host smart-7d796f76-7619-4665-9bf1-4813bcc41ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683384296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1683384296
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3343427615
Short name T208
Test name
Test status
Simulation time 353469312722 ps
CPU time 447.67 seconds
Started May 02 04:08:19 PM PDT 24
Finished May 02 04:15:48 PM PDT 24
Peak memory 202372 kb
Host smart-48e3505e-383a-445a-bdea-e139b65e8007
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343427615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3343427615
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.3509933944
Short name T157
Test name
Test status
Simulation time 341875717798 ps
CPU time 115.93 seconds
Started May 02 04:08:20 PM PDT 24
Finished May 02 04:10:17 PM PDT 24
Peak memory 202324 kb
Host smart-d0287a8b-c734-4b46-a5dd-590528e95a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509933944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.3509933944
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.896488219
Short name T251
Test name
Test status
Simulation time 161928106782 ps
CPU time 107.57 seconds
Started May 02 04:08:21 PM PDT 24
Finished May 02 04:10:09 PM PDT 24
Peak memory 202284 kb
Host smart-319878dc-dcc4-4367-b88a-ef7aed3df007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896488219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.896488219
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.952046691
Short name T44
Test name
Test status
Simulation time 502254322504 ps
CPU time 354.45 seconds
Started May 02 04:08:20 PM PDT 24
Finished May 02 04:14:15 PM PDT 24
Peak memory 202320 kb
Host smart-21a94a69-4a91-4755-b6ad-5a23ce4cc0d4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=952046691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.952046691
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1668121428
Short name T282
Test name
Test status
Simulation time 505381569608 ps
CPU time 285.67 seconds
Started May 02 04:08:12 PM PDT 24
Finished May 02 04:12:58 PM PDT 24
Peak memory 202372 kb
Host smart-e5caab84-2384-4a0f-914c-41aca772d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668121428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1668121428
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.924926164
Short name T435
Test name
Test status
Simulation time 326543402152 ps
CPU time 233.58 seconds
Started May 02 04:08:21 PM PDT 24
Finished May 02 04:12:15 PM PDT 24
Peak memory 202240 kb
Host smart-139bed31-ec42-4009-b86f-d10e4a45fc81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=924926164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.924926164
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3237734615
Short name T784
Test name
Test status
Simulation time 164552329871 ps
CPU time 143.04 seconds
Started May 02 04:08:20 PM PDT 24
Finished May 02 04:10:43 PM PDT 24
Peak memory 202340 kb
Host smart-5a56b9fd-43db-41e8-a029-4f2fb98ffb95
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237734615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3237734615
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1249879336
Short name T461
Test name
Test status
Simulation time 393725131813 ps
CPU time 878.01 seconds
Started May 02 04:08:22 PM PDT 24
Finished May 02 04:23:00 PM PDT 24
Peak memory 202248 kb
Host smart-f50ca772-59ba-422b-b9b5-220ba7e9d028
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249879336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1249879336
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2534747552
Short name T660
Test name
Test status
Simulation time 84990689180 ps
CPU time 465.8 seconds
Started May 02 04:08:21 PM PDT 24
Finished May 02 04:16:08 PM PDT 24
Peak memory 202632 kb
Host smart-023184ce-8cd6-4a12-95a7-858658633f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534747552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2534747552
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.911533064
Short name T734
Test name
Test status
Simulation time 40034879944 ps
CPU time 42.95 seconds
Started May 02 04:08:18 PM PDT 24
Finished May 02 04:09:01 PM PDT 24
Peak memory 202128 kb
Host smart-bb7f7198-c826-457b-bede-47d291999f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911533064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.911533064
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.31810000
Short name T777
Test name
Test status
Simulation time 4002236238 ps
CPU time 3.09 seconds
Started May 02 04:08:21 PM PDT 24
Finished May 02 04:08:24 PM PDT 24
Peak memory 202116 kb
Host smart-7a8121b4-e4a0-481c-90e1-0cda790a5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31810000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.31810000
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.662039231
Short name T624
Test name
Test status
Simulation time 5907169800 ps
CPU time 4.09 seconds
Started May 02 04:08:13 PM PDT 24
Finished May 02 04:08:18 PM PDT 24
Peak memory 202104 kb
Host smart-668cbeaa-5e36-4f56-a9cb-09df12c4103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662039231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.662039231
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.574216948
Short name T630
Test name
Test status
Simulation time 529747902 ps
CPU time 1.56 seconds
Started May 02 04:08:38 PM PDT 24
Finished May 02 04:08:40 PM PDT 24
Peak memory 201948 kb
Host smart-c777f533-0a9e-445b-8a56-e557e9d3b73a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574216948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.574216948
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.989468274
Short name T465
Test name
Test status
Simulation time 326443114804 ps
CPU time 780.57 seconds
Started May 02 04:08:25 PM PDT 24
Finished May 02 04:21:27 PM PDT 24
Peak memory 202280 kb
Host smart-205489a0-aa28-409b-8e4f-5c311902df46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989468274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.989468274
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.1556629629
Short name T374
Test name
Test status
Simulation time 490781610894 ps
CPU time 311.39 seconds
Started May 02 04:08:25 PM PDT 24
Finished May 02 04:13:37 PM PDT 24
Peak memory 202332 kb
Host smart-cf557d03-7420-494b-be42-fd425f2a76e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556629629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.1556629629
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3594472160
Short name T687
Test name
Test status
Simulation time 162041247339 ps
CPU time 345.37 seconds
Started May 02 04:08:26 PM PDT 24
Finished May 02 04:14:12 PM PDT 24
Peak memory 202372 kb
Host smart-5ef4e7a7-0856-4e94-a8b8-97db631ef739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594472160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3594472160
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1686854230
Short name T467
Test name
Test status
Simulation time 487517288410 ps
CPU time 292.29 seconds
Started May 02 04:08:24 PM PDT 24
Finished May 02 04:13:17 PM PDT 24
Peak memory 202288 kb
Host smart-0062cd11-cfef-4406-bd21-605b10d80d52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686854230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1686854230
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2593045653
Short name T158
Test name
Test status
Simulation time 573072050782 ps
CPU time 149.79 seconds
Started May 02 04:08:26 PM PDT 24
Finished May 02 04:10:56 PM PDT 24
Peak memory 202372 kb
Host smart-18701eca-8cb2-4615-b1f1-99625bd110a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593045653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2593045653
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2806974660
Short name T640
Test name
Test status
Simulation time 198847753176 ps
CPU time 209.13 seconds
Started May 02 04:08:33 PM PDT 24
Finished May 02 04:12:03 PM PDT 24
Peak memory 202312 kb
Host smart-69bea5fe-ec3b-4383-b4c9-f1d344f790ef
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806974660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2806974660
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.3036487765
Short name T512
Test name
Test status
Simulation time 35021608408 ps
CPU time 12.26 seconds
Started May 02 04:08:38 PM PDT 24
Finished May 02 04:08:51 PM PDT 24
Peak memory 202108 kb
Host smart-b605f4ac-b976-42eb-8092-442e18fd69bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036487765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.3036487765
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.1350992538
Short name T503
Test name
Test status
Simulation time 4516124696 ps
CPU time 11.15 seconds
Started May 02 04:08:38 PM PDT 24
Finished May 02 04:08:50 PM PDT 24
Peak memory 202080 kb
Host smart-16fea9c6-643d-494f-ab4a-413a241441e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350992538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.1350992538
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.860181105
Short name T790
Test name
Test status
Simulation time 6011435013 ps
CPU time 7.48 seconds
Started May 02 04:08:25 PM PDT 24
Finished May 02 04:08:33 PM PDT 24
Peak memory 202104 kb
Host smart-65b77abf-2142-4c39-b1c3-facae61caedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860181105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.860181105
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2546164309
Short name T473
Test name
Test status
Simulation time 212300869336 ps
CPU time 94.29 seconds
Started May 02 04:08:39 PM PDT 24
Finished May 02 04:10:14 PM PDT 24
Peak memory 202320 kb
Host smart-078090ce-e229-4de2-aa16-ff1858f308ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546164309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2546164309
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3956726259
Short name T15
Test name
Test status
Simulation time 269574396169 ps
CPU time 148.42 seconds
Started May 02 04:08:39 PM PDT 24
Finished May 02 04:11:08 PM PDT 24
Peak memory 211008 kb
Host smart-82a8467c-c4b5-433e-82ed-05bc20dcfaed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956726259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3956726259
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2018252437
Short name T780
Test name
Test status
Simulation time 454057763 ps
CPU time 1.62 seconds
Started May 02 04:08:56 PM PDT 24
Finished May 02 04:08:58 PM PDT 24
Peak memory 202052 kb
Host smart-5c915116-0d3b-4aad-aefc-be73bb5680d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018252437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2018252437
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3817956359
Short name T228
Test name
Test status
Simulation time 343235288415 ps
CPU time 661.11 seconds
Started May 02 04:08:44 PM PDT 24
Finished May 02 04:19:46 PM PDT 24
Peak memory 202320 kb
Host smart-28d0e3af-88de-4e47-9c57-80c129e726da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817956359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3817956359
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3947359437
Short name T531
Test name
Test status
Simulation time 168006409029 ps
CPU time 379.64 seconds
Started May 02 04:08:46 PM PDT 24
Finished May 02 04:15:06 PM PDT 24
Peak memory 202272 kb
Host smart-60c48b89-c330-4d55-b175-a97f4f1f8a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947359437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3947359437
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2894646498
Short name T82
Test name
Test status
Simulation time 339760903215 ps
CPU time 401.66 seconds
Started May 02 04:08:47 PM PDT 24
Finished May 02 04:15:29 PM PDT 24
Peak memory 202252 kb
Host smart-6acd3a8d-d637-4c0a-bac4-3b3b3a2e4f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894646498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2894646498
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.971709872
Short name T769
Test name
Test status
Simulation time 322780455622 ps
CPU time 200.94 seconds
Started May 02 04:08:46 PM PDT 24
Finished May 02 04:12:08 PM PDT 24
Peak memory 202320 kb
Host smart-5f8979f3-b0f8-4b67-9ec1-2fc49f026560
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=971709872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.971709872
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.15972688
Short name T593
Test name
Test status
Simulation time 165493238758 ps
CPU time 369.61 seconds
Started May 02 04:08:39 PM PDT 24
Finished May 02 04:14:50 PM PDT 24
Peak memory 202332 kb
Host smart-7478621f-64b9-41b7-9b7b-6eff5fd89108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15972688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.15972688
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2278053977
Short name T529
Test name
Test status
Simulation time 333471706715 ps
CPU time 200.1 seconds
Started May 02 04:08:39 PM PDT 24
Finished May 02 04:12:00 PM PDT 24
Peak memory 202288 kb
Host smart-0cfdce09-7219-4656-a5c8-8d3f529e534d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278053977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2278053977
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.112266381
Short name T214
Test name
Test status
Simulation time 186292697941 ps
CPU time 348 seconds
Started May 02 04:08:46 PM PDT 24
Finished May 02 04:14:34 PM PDT 24
Peak memory 202428 kb
Host smart-66b4bbd4-9878-4a31-b44c-5d952ab29842
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112266381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.112266381
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1913988113
Short name T151
Test name
Test status
Simulation time 620530702018 ps
CPU time 143.37 seconds
Started May 02 04:08:45 PM PDT 24
Finished May 02 04:11:09 PM PDT 24
Peak memory 202276 kb
Host smart-6306c2ec-b9a4-4871-84f6-a45dba21eee2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913988113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1913988113
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3934359575
Short name T182
Test name
Test status
Simulation time 83185436090 ps
CPU time 363.03 seconds
Started May 02 04:08:54 PM PDT 24
Finished May 02 04:14:58 PM PDT 24
Peak memory 202736 kb
Host smart-01eef0b4-c582-4f28-b92c-1880097913f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934359575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3934359575
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1075759726
Short name T690
Test name
Test status
Simulation time 48083401148 ps
CPU time 56.86 seconds
Started May 02 04:08:45 PM PDT 24
Finished May 02 04:09:43 PM PDT 24
Peak memory 202116 kb
Host smart-62eeaddc-ae89-4c19-93c6-544c59cebac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075759726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1075759726
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.459112652
Short name T378
Test name
Test status
Simulation time 5317570466 ps
CPU time 9.89 seconds
Started May 02 04:08:45 PM PDT 24
Finished May 02 04:08:56 PM PDT 24
Peak memory 202128 kb
Host smart-2e154720-1e4f-4a82-8f2f-5c000046953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459112652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.459112652
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1364946922
Short name T739
Test name
Test status
Simulation time 5681856002 ps
CPU time 4.09 seconds
Started May 02 04:08:37 PM PDT 24
Finished May 02 04:08:42 PM PDT 24
Peak memory 202064 kb
Host smart-1d5dafd1-aa8a-4e3d-a767-177e730349bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364946922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1364946922
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.1100749251
Short name T778
Test name
Test status
Simulation time 241400533128 ps
CPU time 596.49 seconds
Started May 02 04:08:53 PM PDT 24
Finished May 02 04:18:50 PM PDT 24
Peak memory 202264 kb
Host smart-e72f5b74-5c3f-4193-a7b3-81eeb5e32bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100749251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.1100749251
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1161021511
Short name T246
Test name
Test status
Simulation time 492251565828 ps
CPU time 126.74 seconds
Started May 02 04:08:54 PM PDT 24
Finished May 02 04:11:01 PM PDT 24
Peak memory 211092 kb
Host smart-470f6b05-91ff-4f3d-bebf-6975e4d201ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161021511 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1161021511
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2676190947
Short name T727
Test name
Test status
Simulation time 306286729 ps
CPU time 1.06 seconds
Started May 02 04:09:02 PM PDT 24
Finished May 02 04:09:04 PM PDT 24
Peak memory 201948 kb
Host smart-31063ccd-5da5-4c71-98d7-7f71ea774454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676190947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2676190947
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1076367310
Short name T204
Test name
Test status
Simulation time 174028291806 ps
CPU time 406.96 seconds
Started May 02 04:09:04 PM PDT 24
Finished May 02 04:15:51 PM PDT 24
Peak memory 202364 kb
Host smart-0a5a2ed9-82ea-47ef-a191-110eaac89169
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076367310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1076367310
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.2348204603
Short name T706
Test name
Test status
Simulation time 493235819389 ps
CPU time 550.36 seconds
Started May 02 04:08:55 PM PDT 24
Finished May 02 04:18:06 PM PDT 24
Peak memory 202376 kb
Host smart-2cc58057-17cd-47f3-924a-55ab2c0f992a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348204603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.2348204603
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1089766105
Short name T632
Test name
Test status
Simulation time 491534438372 ps
CPU time 80.63 seconds
Started May 02 04:08:56 PM PDT 24
Finished May 02 04:10:17 PM PDT 24
Peak memory 202264 kb
Host smart-880f6da5-5c40-442a-941f-0bc3dbbb9dc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089766105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1089766105
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2397115366
Short name T754
Test name
Test status
Simulation time 494019731431 ps
CPU time 1148.65 seconds
Started May 02 04:08:56 PM PDT 24
Finished May 02 04:28:05 PM PDT 24
Peak memory 202284 kb
Host smart-25b5f6a9-6539-41ae-a52b-05f59fb060e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397115366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2397115366
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.2920933486
Short name T364
Test name
Test status
Simulation time 325073382620 ps
CPU time 189.95 seconds
Started May 02 04:08:55 PM PDT 24
Finished May 02 04:12:06 PM PDT 24
Peak memory 202384 kb
Host smart-7f178c63-81fd-48e3-991a-98e0ead80e16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920933486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.2920933486
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2298604608
Short name T126
Test name
Test status
Simulation time 360474108728 ps
CPU time 178.05 seconds
Started May 02 04:09:01 PM PDT 24
Finished May 02 04:12:00 PM PDT 24
Peak memory 202300 kb
Host smart-a3cc03ee-dc5c-4ac6-a954-0fff8079bb6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298604608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2298604608
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3009965205
Short name T643
Test name
Test status
Simulation time 596890721284 ps
CPU time 1431.83 seconds
Started May 02 04:09:03 PM PDT 24
Finished May 02 04:32:55 PM PDT 24
Peak memory 202280 kb
Host smart-a5a42777-24da-4c73-9552-b5d01baccefb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009965205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3009965205
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3672434589
Short name T57
Test name
Test status
Simulation time 114576491414 ps
CPU time 624.16 seconds
Started May 02 04:09:04 PM PDT 24
Finished May 02 04:19:29 PM PDT 24
Peak memory 202612 kb
Host smart-ddc381d0-77e2-40d6-ad04-f7045af11e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672434589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3672434589
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.35708856
Short name T337
Test name
Test status
Simulation time 25433245810 ps
CPU time 11.26 seconds
Started May 02 04:09:02 PM PDT 24
Finished May 02 04:09:14 PM PDT 24
Peak memory 202152 kb
Host smart-5e9a8922-9a31-4696-be1a-adb61b62abc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35708856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.35708856
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.4025850522
Short name T773
Test name
Test status
Simulation time 5046873122 ps
CPU time 5.61 seconds
Started May 02 04:09:01 PM PDT 24
Finished May 02 04:09:07 PM PDT 24
Peak memory 202056 kb
Host smart-29361fe1-e549-4663-b4a9-ba088e806cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025850522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.4025850522
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3083824461
Short name T430
Test name
Test status
Simulation time 5963721168 ps
CPU time 15.53 seconds
Started May 02 04:08:56 PM PDT 24
Finished May 02 04:09:12 PM PDT 24
Peak memory 202108 kb
Host smart-f5ea196a-759f-4931-807b-6685de581d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083824461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3083824461
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1458505488
Short name T717
Test name
Test status
Simulation time 174785650194 ps
CPU time 104.94 seconds
Started May 02 04:09:02 PM PDT 24
Finished May 02 04:10:47 PM PDT 24
Peak memory 202352 kb
Host smart-d1e73b47-160c-493f-883d-96b1c3351b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458505488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1458505488
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.3884834797
Short name T118
Test name
Test status
Simulation time 66646608150 ps
CPU time 130.17 seconds
Started May 02 04:09:03 PM PDT 24
Finished May 02 04:11:13 PM PDT 24
Peak memory 210996 kb
Host smart-4d5f6244-1284-4e71-89da-0489479d7981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884834797 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.3884834797
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3342357086
Short name T404
Test name
Test status
Simulation time 509161386 ps
CPU time 1.17 seconds
Started May 02 04:09:23 PM PDT 24
Finished May 02 04:09:25 PM PDT 24
Peak memory 201940 kb
Host smart-ba95b58e-07ae-40d9-9294-e4b095fb504c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342357086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3342357086
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.2433316585
Short name T751
Test name
Test status
Simulation time 563922931773 ps
CPU time 547.85 seconds
Started May 02 04:09:15 PM PDT 24
Finished May 02 04:18:24 PM PDT 24
Peak memory 202360 kb
Host smart-d30e7791-f5d5-4bec-af53-71294c889053
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433316585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.2433316585
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.410285064
Short name T772
Test name
Test status
Simulation time 342045169714 ps
CPU time 125.43 seconds
Started May 02 04:09:19 PM PDT 24
Finished May 02 04:11:25 PM PDT 24
Peak memory 202324 kb
Host smart-41d10882-b8d5-4e37-af9a-ac0e8e905057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410285064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.410285064
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1482680711
Short name T236
Test name
Test status
Simulation time 324400048204 ps
CPU time 93.55 seconds
Started May 02 04:09:08 PM PDT 24
Finished May 02 04:10:42 PM PDT 24
Peak memory 202276 kb
Host smart-5083f84b-7b64-43cb-8b61-fd174ce601fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482680711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1482680711
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3682935113
Short name T28
Test name
Test status
Simulation time 324234684124 ps
CPU time 212.8 seconds
Started May 02 04:09:09 PM PDT 24
Finished May 02 04:12:43 PM PDT 24
Peak memory 202264 kb
Host smart-8710b9f7-b74e-47b3-a021-3aafcbf20c19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682935113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3682935113
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.371106974
Short name T394
Test name
Test status
Simulation time 160763949717 ps
CPU time 90.82 seconds
Started May 02 04:09:09 PM PDT 24
Finished May 02 04:10:40 PM PDT 24
Peak memory 202292 kb
Host smart-b71ea131-3e9f-42db-bd6a-55d499ed7e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371106974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.371106974
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.207757181
Short name T692
Test name
Test status
Simulation time 321872428556 ps
CPU time 691.77 seconds
Started May 02 04:09:10 PM PDT 24
Finished May 02 04:20:42 PM PDT 24
Peak memory 202348 kb
Host smart-5d609fd9-044e-4399-99b8-5ed0483e43f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=207757181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.207757181
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.983605319
Short name T532
Test name
Test status
Simulation time 366038107765 ps
CPU time 238.24 seconds
Started May 02 04:09:08 PM PDT 24
Finished May 02 04:13:07 PM PDT 24
Peak memory 202252 kb
Host smart-986542c2-2290-4524-b727-68bc50198610
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983605319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.983605319
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2094079875
Short name T96
Test name
Test status
Simulation time 614458405652 ps
CPU time 876.26 seconds
Started May 02 04:09:16 PM PDT 24
Finished May 02 04:23:53 PM PDT 24
Peak memory 202332 kb
Host smart-91b69b8a-fc83-46ac-a6d4-0440c00595f2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094079875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2094079875
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1111168518
Short name T176
Test name
Test status
Simulation time 94731452542 ps
CPU time 351.15 seconds
Started May 02 04:09:21 PM PDT 24
Finished May 02 04:15:13 PM PDT 24
Peak memory 202708 kb
Host smart-83660c1a-a9cf-43f2-905a-cff1fe52436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111168518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1111168518
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.4046500946
Short name T511
Test name
Test status
Simulation time 30291210977 ps
CPU time 13.54 seconds
Started May 02 04:09:23 PM PDT 24
Finished May 02 04:09:37 PM PDT 24
Peak memory 202156 kb
Host smart-1b099588-868f-413b-85a7-bc2bcc9fd90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046500946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4046500946
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3521955174
Short name T675
Test name
Test status
Simulation time 5117370251 ps
CPU time 4.06 seconds
Started May 02 04:09:17 PM PDT 24
Finished May 02 04:09:22 PM PDT 24
Peak memory 202088 kb
Host smart-30a1c230-dd60-41cb-a017-e5d361b56025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521955174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3521955174
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2261873815
Short name T475
Test name
Test status
Simulation time 6033960192 ps
CPU time 14.09 seconds
Started May 02 04:09:10 PM PDT 24
Finished May 02 04:09:24 PM PDT 24
Peak memory 202116 kb
Host smart-98de5fac-5cc9-48c0-adaf-2c38004e0fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261873815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2261873815
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3926819593
Short name T545
Test name
Test status
Simulation time 40109587277 ps
CPU time 85.39 seconds
Started May 02 04:09:22 PM PDT 24
Finished May 02 04:10:48 PM PDT 24
Peak memory 202144 kb
Host smart-4f25b423-eed6-42e2-8797-a9ef7b7b4c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926819593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3926819593
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3358857461
Short name T300
Test name
Test status
Simulation time 192202844771 ps
CPU time 109.81 seconds
Started May 02 04:09:23 PM PDT 24
Finished May 02 04:11:13 PM PDT 24
Peak memory 210656 kb
Host smart-412ff8ad-8ae9-44d3-b3b6-4391455b736a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358857461 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3358857461
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2480639176
Short name T638
Test name
Test status
Simulation time 353412558 ps
CPU time 1.52 seconds
Started May 02 04:09:43 PM PDT 24
Finished May 02 04:09:46 PM PDT 24
Peak memory 202012 kb
Host smart-de0d9b1a-c1e1-4cb3-a494-d3d3bd46f5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480639176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2480639176
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.103758747
Short name T242
Test name
Test status
Simulation time 490225659008 ps
CPU time 311.31 seconds
Started May 02 04:09:28 PM PDT 24
Finished May 02 04:14:40 PM PDT 24
Peak memory 202356 kb
Host smart-cf127c00-f0c7-4ea2-a95d-ee48dea16afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103758747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.103758747
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2718669913
Short name T768
Test name
Test status
Simulation time 484477171201 ps
CPU time 138.66 seconds
Started May 02 04:09:28 PM PDT 24
Finished May 02 04:11:48 PM PDT 24
Peak memory 202276 kb
Host smart-c125f35d-81e2-4221-9c09-782e69a31f73
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718669913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2718669913
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1646757362
Short name T372
Test name
Test status
Simulation time 164837539996 ps
CPU time 25.44 seconds
Started May 02 04:09:30 PM PDT 24
Finished May 02 04:09:56 PM PDT 24
Peak memory 202328 kb
Host smart-079e1bad-a7a1-4453-939d-f634a50acb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646757362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1646757362
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1177263207
Short name T786
Test name
Test status
Simulation time 326418073460 ps
CPU time 317 seconds
Started May 02 04:09:28 PM PDT 24
Finished May 02 04:14:46 PM PDT 24
Peak memory 202228 kb
Host smart-a9ed5844-a0b3-4815-b461-8381ed5cc3fb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177263207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1177263207
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3866396600
Short name T312
Test name
Test status
Simulation time 362730702390 ps
CPU time 70.04 seconds
Started May 02 04:09:38 PM PDT 24
Finished May 02 04:10:49 PM PDT 24
Peak memory 202368 kb
Host smart-18fda428-6eed-4cf5-a8fe-83c97bce3cfc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866396600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3866396600
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2035752741
Short name T500
Test name
Test status
Simulation time 383578269130 ps
CPU time 460.86 seconds
Started May 02 04:09:37 PM PDT 24
Finished May 02 04:17:19 PM PDT 24
Peak memory 202296 kb
Host smart-47a17f00-caf5-422c-8497-f49231476719
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035752741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2035752741
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.629050290
Short name T710
Test name
Test status
Simulation time 85392308313 ps
CPU time 336.5 seconds
Started May 02 04:09:42 PM PDT 24
Finished May 02 04:15:19 PM PDT 24
Peak memory 202688 kb
Host smart-61dbca3c-225a-4240-acfc-c2b6e0e15a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629050290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.629050290
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3169201631
Short name T341
Test name
Test status
Simulation time 29941269379 ps
CPU time 69.82 seconds
Started May 02 04:09:42 PM PDT 24
Finished May 02 04:10:53 PM PDT 24
Peak memory 202140 kb
Host smart-d2821710-514c-472b-b303-041c3df257c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169201631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3169201631
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2196783545
Short name T546
Test name
Test status
Simulation time 3024759682 ps
CPU time 7.09 seconds
Started May 02 04:09:43 PM PDT 24
Finished May 02 04:09:51 PM PDT 24
Peak memory 202104 kb
Host smart-330c864f-be78-4950-99b2-f3562effe0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196783545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2196783545
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.780158806
Short name T407
Test name
Test status
Simulation time 5975536664 ps
CPU time 7.82 seconds
Started May 02 04:09:23 PM PDT 24
Finished May 02 04:09:31 PM PDT 24
Peak memory 202128 kb
Host smart-c6dd2715-0c47-4977-b03a-87d6159f396d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780158806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.780158806
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2492881164
Short name T33
Test name
Test status
Simulation time 161076083452 ps
CPU time 86.97 seconds
Started May 02 04:09:41 PM PDT 24
Finished May 02 04:11:09 PM PDT 24
Peak memory 202404 kb
Host smart-d07ef890-f914-40fb-8eff-2299fb769c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492881164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2492881164
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3511808227
Short name T309
Test name
Test status
Simulation time 27767668833 ps
CPU time 40.32 seconds
Started May 02 04:09:43 PM PDT 24
Finished May 02 04:10:24 PM PDT 24
Peak memory 210668 kb
Host smart-fa96ba32-ac1e-4952-9345-c3bdfd3aa5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511808227 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3511808227
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1931927406
Short name T91
Test name
Test status
Simulation time 379574558 ps
CPU time 1.6 seconds
Started May 02 04:00:34 PM PDT 24
Finished May 02 04:00:36 PM PDT 24
Peak memory 201996 kb
Host smart-0d22e321-2586-4a88-958b-a1a6257ec106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931927406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1931927406
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.4122555901
Short name T507
Test name
Test status
Simulation time 350392557637 ps
CPU time 404.65 seconds
Started May 02 04:00:32 PM PDT 24
Finished May 02 04:07:17 PM PDT 24
Peak memory 202372 kb
Host smart-53220dde-d3a0-4028-98e6-6f7766726c69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122555901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.4122555901
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.4172063027
Short name T332
Test name
Test status
Simulation time 322181669478 ps
CPU time 208.37 seconds
Started May 02 04:00:23 PM PDT 24
Finished May 02 04:03:52 PM PDT 24
Peak memory 202332 kb
Host smart-6cc785e6-5dd0-4d1e-a2e9-e83e0d2d6912
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172063027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.4172063027
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.884255231
Short name T276
Test name
Test status
Simulation time 500551406906 ps
CPU time 1211.92 seconds
Started May 02 04:00:24 PM PDT 24
Finished May 02 04:20:37 PM PDT 24
Peak memory 202380 kb
Host smart-ed0242e1-bae3-4a28-bb04-837db22bb27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884255231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.884255231
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.3091099824
Short name T484
Test name
Test status
Simulation time 492702672378 ps
CPU time 582.01 seconds
Started May 02 04:00:28 PM PDT 24
Finished May 02 04:10:11 PM PDT 24
Peak memory 202280 kb
Host smart-8b338633-4c1b-4657-98dd-42d21dfdb420
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091099824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.3091099824
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.472914674
Short name T397
Test name
Test status
Simulation time 210024984725 ps
CPU time 232.94 seconds
Started May 02 04:00:33 PM PDT 24
Finished May 02 04:04:27 PM PDT 24
Peak memory 202304 kb
Host smart-fd0a8b4c-49c0-4359-b63d-f063b472c559
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472914674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.472914674
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3391345716
Short name T613
Test name
Test status
Simulation time 81957180253 ps
CPU time 429.91 seconds
Started May 02 04:00:32 PM PDT 24
Finished May 02 04:07:43 PM PDT 24
Peak memory 202684 kb
Host smart-927b80a9-2f58-45a5-a912-19679f4e8e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391345716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3391345716
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.238008461
Short name T45
Test name
Test status
Simulation time 43396116623 ps
CPU time 100.43 seconds
Started May 02 04:00:32 PM PDT 24
Finished May 02 04:02:13 PM PDT 24
Peak memory 202076 kb
Host smart-fb0e5384-f297-4903-8859-44b04d78c6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238008461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.238008461
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4258325385
Short name T94
Test name
Test status
Simulation time 2831372705 ps
CPU time 6.85 seconds
Started May 02 04:00:33 PM PDT 24
Finished May 02 04:00:40 PM PDT 24
Peak memory 202100 kb
Host smart-fe7a5f37-28eb-4c41-98f3-31ca5ff90b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258325385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4258325385
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1716423092
Short name T81
Test name
Test status
Simulation time 7797705836 ps
CPU time 5.59 seconds
Started May 02 04:00:35 PM PDT 24
Finished May 02 04:00:41 PM PDT 24
Peak memory 217796 kb
Host smart-3f51db97-f32e-41e6-9a7d-132b3f134840
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716423092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1716423092
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.4205420739
Short name T715
Test name
Test status
Simulation time 5558032844 ps
CPU time 11.83 seconds
Started May 02 04:00:26 PM PDT 24
Finished May 02 04:00:39 PM PDT 24
Peak memory 202060 kb
Host smart-e7b2399b-b1c1-4e5d-940f-7b835c165722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205420739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.4205420739
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1578822936
Short name T289
Test name
Test status
Simulation time 3336085962215 ps
CPU time 1179.55 seconds
Started May 02 04:00:31 PM PDT 24
Finished May 02 04:20:11 PM PDT 24
Peak memory 213600 kb
Host smart-eeec656e-7bd6-4be3-bb58-b826ec7d12c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578822936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1578822936
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3007955594
Short name T35
Test name
Test status
Simulation time 63916355388 ps
CPU time 135.05 seconds
Started May 02 04:00:33 PM PDT 24
Finished May 02 04:02:49 PM PDT 24
Peak memory 210680 kb
Host smart-4eaa55a2-3771-40ba-99b9-6b73cf52c403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007955594 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3007955594
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3052390968
Short name T353
Test name
Test status
Simulation time 363168823 ps
CPU time 1.41 seconds
Started May 02 04:09:53 PM PDT 24
Finished May 02 04:09:56 PM PDT 24
Peak memory 202024 kb
Host smart-c24a5030-893d-4b26-9fae-28ee131a2b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052390968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3052390968
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2088918475
Short name T304
Test name
Test status
Simulation time 237949806239 ps
CPU time 135.01 seconds
Started May 02 04:09:50 PM PDT 24
Finished May 02 04:12:06 PM PDT 24
Peak memory 202360 kb
Host smart-b452bd53-a77c-4519-8548-47c4a1b799b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088918475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2088918475
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3793879340
Short name T148
Test name
Test status
Simulation time 319193754671 ps
CPU time 692.77 seconds
Started May 02 04:09:49 PM PDT 24
Finished May 02 04:21:23 PM PDT 24
Peak memory 202408 kb
Host smart-59cf60e4-a9e2-4dfc-98bf-deb953efc16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793879340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3793879340
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2012078674
Short name T164
Test name
Test status
Simulation time 327295671986 ps
CPU time 199.98 seconds
Started May 02 04:09:49 PM PDT 24
Finished May 02 04:13:10 PM PDT 24
Peak memory 202304 kb
Host smart-3b83e4d2-c234-4508-9986-f66c3cb6e95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012078674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2012078674
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.3631982349
Short name T366
Test name
Test status
Simulation time 328915488132 ps
CPU time 400.26 seconds
Started May 02 04:09:49 PM PDT 24
Finished May 02 04:16:30 PM PDT 24
Peak memory 202340 kb
Host smart-b0600897-2c4a-49ce-ae0a-bed61bd66267
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631982349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.3631982349
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1555462903
Short name T476
Test name
Test status
Simulation time 488641525065 ps
CPU time 307.39 seconds
Started May 02 04:09:52 PM PDT 24
Finished May 02 04:15:00 PM PDT 24
Peak memory 202280 kb
Host smart-38a1a06b-8ddc-4513-b891-b8ca126b48b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555462903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1555462903
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3114077930
Short name T423
Test name
Test status
Simulation time 334053258073 ps
CPU time 203.23 seconds
Started May 02 04:09:49 PM PDT 24
Finished May 02 04:13:13 PM PDT 24
Peak memory 202240 kb
Host smart-2c159bb5-72c0-4f44-88bd-80daf046fe14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114077930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3114077930
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4011601563
Short name T662
Test name
Test status
Simulation time 175568650443 ps
CPU time 426.95 seconds
Started May 02 04:09:49 PM PDT 24
Finished May 02 04:16:57 PM PDT 24
Peak memory 202336 kb
Host smart-a6f0996d-357d-455e-81c7-51033f788a93
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011601563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4011601563
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1463586503
Short name T612
Test name
Test status
Simulation time 214883716143 ps
CPU time 116.72 seconds
Started May 02 04:09:51 PM PDT 24
Finished May 02 04:11:49 PM PDT 24
Peak memory 202304 kb
Host smart-8900d8ad-d0c0-4f77-a367-4063767ff41a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463586503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1463586503
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1670174582
Short name T482
Test name
Test status
Simulation time 66655468644 ps
CPU time 400.98 seconds
Started May 02 04:09:51 PM PDT 24
Finished May 02 04:16:33 PM PDT 24
Peak memory 202648 kb
Host smart-ef61a72c-0c5d-4fc7-a2dc-f55b35c81006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670174582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1670174582
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.51097653
Short name T575
Test name
Test status
Simulation time 30037872454 ps
CPU time 70.9 seconds
Started May 02 04:09:48 PM PDT 24
Finished May 02 04:11:00 PM PDT 24
Peak memory 202088 kb
Host smart-6e84b709-2e71-4bc3-9b22-df3fd08dc360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51097653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.51097653
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3438318873
Short name T375
Test name
Test status
Simulation time 3198165352 ps
CPU time 7.92 seconds
Started May 02 04:09:51 PM PDT 24
Finished May 02 04:09:59 PM PDT 24
Peak memory 202116 kb
Host smart-25a9d076-4360-4cbb-95ce-eb583dc78e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438318873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3438318873
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1241430691
Short name T142
Test name
Test status
Simulation time 6142360555 ps
CPU time 4.36 seconds
Started May 02 04:09:51 PM PDT 24
Finished May 02 04:09:56 PM PDT 24
Peak memory 202092 kb
Host smart-5f5b3e0b-94a9-4e54-893e-34ebd6006e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241430691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1241430691
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2162209863
Short name T301
Test name
Test status
Simulation time 221469065662 ps
CPU time 248.87 seconds
Started May 02 04:09:53 PM PDT 24
Finished May 02 04:14:03 PM PDT 24
Peak memory 202340 kb
Host smart-139393c7-3e34-4083-9641-690c7b7ba15d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162209863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2162209863
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.488963450
Short name T308
Test name
Test status
Simulation time 113391677656 ps
CPU time 59.67 seconds
Started May 02 04:09:49 PM PDT 24
Finished May 02 04:10:50 PM PDT 24
Peak memory 210984 kb
Host smart-8f4189ef-5ab6-46bf-9de9-ed0c8ac6f0ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488963450 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.488963450
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.414176253
Short name T75
Test name
Test status
Simulation time 475480580 ps
CPU time 1.65 seconds
Started May 02 04:10:17 PM PDT 24
Finished May 02 04:10:19 PM PDT 24
Peak memory 201940 kb
Host smart-3b15616f-53a7-4847-b1c2-853de6fa9f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414176253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.414176253
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.3317616906
Short name T577
Test name
Test status
Simulation time 187678975738 ps
CPU time 114.82 seconds
Started May 02 04:10:17 PM PDT 24
Finished May 02 04:12:13 PM PDT 24
Peak memory 202296 kb
Host smart-c0af2f7d-b3aa-4902-a2b8-895a686da217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317616906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.3317616906
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3835490803
Short name T412
Test name
Test status
Simulation time 165174381226 ps
CPU time 100.08 seconds
Started May 02 04:09:59 PM PDT 24
Finished May 02 04:11:40 PM PDT 24
Peak memory 202312 kb
Host smart-9a66f6f4-6990-4f5e-80a3-0a5cff3859f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835490803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3835490803
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.814090724
Short name T588
Test name
Test status
Simulation time 160388518066 ps
CPU time 197.16 seconds
Started May 02 04:09:53 PM PDT 24
Finished May 02 04:13:11 PM PDT 24
Peak memory 202312 kb
Host smart-a65d67b0-2eff-4245-aee1-aa30ed727978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814090724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.814090724
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1452394685
Short name T434
Test name
Test status
Simulation time 325465186427 ps
CPU time 821.73 seconds
Started May 02 04:10:02 PM PDT 24
Finished May 02 04:23:45 PM PDT 24
Peak memory 202292 kb
Host smart-e1a92d7e-c609-4653-a8c8-9f668a2df32f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452394685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1452394685
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.4065377624
Short name T721
Test name
Test status
Simulation time 358609707398 ps
CPU time 136.96 seconds
Started May 02 04:10:02 PM PDT 24
Finished May 02 04:12:20 PM PDT 24
Peak memory 202348 kb
Host smart-c7adfbae-6021-4df0-9dac-8a333174198a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065377624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.4065377624
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.179827746
Short name T712
Test name
Test status
Simulation time 393312317862 ps
CPU time 490.46 seconds
Started May 02 04:10:01 PM PDT 24
Finished May 02 04:18:13 PM PDT 24
Peak memory 202228 kb
Host smart-b141e2ae-d951-4ea2-819d-e09cee52d938
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179827746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.179827746
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2840483832
Short name T51
Test name
Test status
Simulation time 121243248615 ps
CPU time 483.27 seconds
Started May 02 04:10:18 PM PDT 24
Finished May 02 04:18:22 PM PDT 24
Peak memory 202712 kb
Host smart-c166bf75-1b83-4a10-9e1a-846fac1fbcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840483832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2840483832
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3822958905
Short name T606
Test name
Test status
Simulation time 24875248110 ps
CPU time 58.24 seconds
Started May 02 04:10:17 PM PDT 24
Finished May 02 04:11:16 PM PDT 24
Peak memory 202156 kb
Host smart-c37a9397-165a-4525-9cdf-c24fc8c6503e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822958905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3822958905
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.513220574
Short name T351
Test name
Test status
Simulation time 5418032737 ps
CPU time 14.23 seconds
Started May 02 04:10:18 PM PDT 24
Finished May 02 04:10:33 PM PDT 24
Peak memory 202112 kb
Host smart-4bc51656-cdd8-49dc-bea1-81328fe903ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513220574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.513220574
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.2457139722
Short name T762
Test name
Test status
Simulation time 6131803857 ps
CPU time 4.15 seconds
Started May 02 04:09:54 PM PDT 24
Finished May 02 04:09:59 PM PDT 24
Peak memory 202140 kb
Host smart-9ab92cfc-4d33-404b-af51-9039d2c8ee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457139722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.2457139722
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.507391539
Short name T140
Test name
Test status
Simulation time 339714163242 ps
CPU time 249.13 seconds
Started May 02 04:10:17 PM PDT 24
Finished May 02 04:14:28 PM PDT 24
Peak memory 218792 kb
Host smart-0de4b5e2-7f13-4ec9-884f-d1c52c5b39a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507391539 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.507391539
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2034002862
Short name T514
Test name
Test status
Simulation time 433803165 ps
CPU time 1.14 seconds
Started May 02 04:10:27 PM PDT 24
Finished May 02 04:10:29 PM PDT 24
Peak memory 202012 kb
Host smart-2d6c3cb3-10c7-4cb4-97ca-078a39c70d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034002862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2034002862
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2466840452
Short name T175
Test name
Test status
Simulation time 338706428902 ps
CPU time 68.57 seconds
Started May 02 04:10:20 PM PDT 24
Finished May 02 04:11:29 PM PDT 24
Peak memory 202380 kb
Host smart-e97af67e-16a6-4c6b-9e21-581193babe40
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466840452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2466840452
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.177666069
Short name T313
Test name
Test status
Simulation time 197794786329 ps
CPU time 113.23 seconds
Started May 02 04:10:20 PM PDT 24
Finished May 02 04:12:14 PM PDT 24
Peak memory 202264 kb
Host smart-8237e117-4929-473a-b7dc-26946ed87d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177666069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.177666069
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2765529069
Short name T346
Test name
Test status
Simulation time 499386139952 ps
CPU time 1136.15 seconds
Started May 02 04:10:20 PM PDT 24
Finished May 02 04:29:17 PM PDT 24
Peak memory 202304 kb
Host smart-62460d42-c80e-443a-9fda-eb0efb41e375
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765529069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2765529069
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2345486849
Short name T240
Test name
Test status
Simulation time 161465979781 ps
CPU time 362.9 seconds
Started May 02 04:10:17 PM PDT 24
Finished May 02 04:16:21 PM PDT 24
Peak memory 202380 kb
Host smart-cf89035f-2b26-4a44-9377-caba730dfc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345486849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2345486849
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1375736987
Short name T719
Test name
Test status
Simulation time 323622334870 ps
CPU time 111.2 seconds
Started May 02 04:10:21 PM PDT 24
Finished May 02 04:12:13 PM PDT 24
Peak memory 202356 kb
Host smart-cae64453-b955-4f97-bca9-eba3e566cb55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375736987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1375736987
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3587365076
Short name T380
Test name
Test status
Simulation time 603721397399 ps
CPU time 694.87 seconds
Started May 02 04:10:22 PM PDT 24
Finished May 02 04:21:58 PM PDT 24
Peak memory 202300 kb
Host smart-823fcf76-6636-4e51-abfe-068166d29be9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587365076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3587365076
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.461639571
Short name T319
Test name
Test status
Simulation time 119996329121 ps
CPU time 609.41 seconds
Started May 02 04:10:21 PM PDT 24
Finished May 02 04:20:31 PM PDT 24
Peak memory 202604 kb
Host smart-bf783592-cf95-4ad5-bda2-0e69c2b261ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461639571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.461639571
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2191898045
Short name T480
Test name
Test status
Simulation time 34503160307 ps
CPU time 82.96 seconds
Started May 02 04:10:20 PM PDT 24
Finished May 02 04:11:44 PM PDT 24
Peak memory 202100 kb
Host smart-7dcd76a2-71a8-4b4d-a67b-943a7ab96678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191898045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2191898045
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3328639742
Short name T530
Test name
Test status
Simulation time 3219064979 ps
CPU time 1.06 seconds
Started May 02 04:10:22 PM PDT 24
Finished May 02 04:10:24 PM PDT 24
Peak memory 202148 kb
Host smart-59a1e5e5-1013-4b23-b01c-b12777db2004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328639742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3328639742
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.593558299
Short name T385
Test name
Test status
Simulation time 5933345303 ps
CPU time 13.5 seconds
Started May 02 04:10:18 PM PDT 24
Finished May 02 04:10:33 PM PDT 24
Peak memory 202124 kb
Host smart-9ea8a8dc-8321-44bd-af4e-367827d9507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593558299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.593558299
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.4282265735
Short name T285
Test name
Test status
Simulation time 369318379151 ps
CPU time 672.33 seconds
Started May 02 04:10:28 PM PDT 24
Finished May 02 04:21:41 PM PDT 24
Peak memory 202328 kb
Host smart-fc184199-339e-4a42-97bf-417511ea5e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282265735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.4282265735
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1152880561
Short name T540
Test name
Test status
Simulation time 459093475 ps
CPU time 1.68 seconds
Started May 02 04:10:32 PM PDT 24
Finished May 02 04:10:35 PM PDT 24
Peak memory 202028 kb
Host smart-884f77ce-5c8f-4100-9c29-939889f89f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152880561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1152880561
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.2936517282
Short name T759
Test name
Test status
Simulation time 505077554070 ps
CPU time 1226.1 seconds
Started May 02 04:10:33 PM PDT 24
Finished May 02 04:31:00 PM PDT 24
Peak memory 202332 kb
Host smart-88b34e71-ba0a-4aec-8bec-cffbb1927a1d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936517282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.2936517282
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.1047779665
Short name T483
Test name
Test status
Simulation time 167844291703 ps
CPU time 196.29 seconds
Started May 02 04:10:27 PM PDT 24
Finished May 02 04:13:44 PM PDT 24
Peak memory 202296 kb
Host smart-1f56e4e4-3fc6-4249-9c61-823aa1419c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047779665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.1047779665
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2762320959
Short name T539
Test name
Test status
Simulation time 159803792849 ps
CPU time 195.35 seconds
Started May 02 04:10:26 PM PDT 24
Finished May 02 04:13:43 PM PDT 24
Peak memory 202248 kb
Host smart-bc5d34b8-8c1e-4e6b-8aa0-ec06358d2b5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762320959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2762320959
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3045974965
Short name T648
Test name
Test status
Simulation time 161809981390 ps
CPU time 94.05 seconds
Started May 02 04:10:26 PM PDT 24
Finished May 02 04:12:00 PM PDT 24
Peak memory 202268 kb
Host smart-975a32e3-2cf3-4a17-8b62-b5cdab207a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045974965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3045974965
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2968217050
Short name T150
Test name
Test status
Simulation time 168309312993 ps
CPU time 102.14 seconds
Started May 02 04:10:26 PM PDT 24
Finished May 02 04:12:09 PM PDT 24
Peak memory 202276 kb
Host smart-ef1da44b-f355-4e8d-abb4-35ef67e489c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968217050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2968217050
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.764613824
Short name T756
Test name
Test status
Simulation time 175291114163 ps
CPU time 108.07 seconds
Started May 02 04:10:34 PM PDT 24
Finished May 02 04:12:22 PM PDT 24
Peak memory 202256 kb
Host smart-251f6311-22f1-4c82-9234-1604394f2b6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764613824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.764613824
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1166087147
Short name T703
Test name
Test status
Simulation time 209727511476 ps
CPU time 67.61 seconds
Started May 02 04:10:34 PM PDT 24
Finished May 02 04:11:42 PM PDT 24
Peak memory 202260 kb
Host smart-b346b4d4-821f-46be-8f15-045087d7bd75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166087147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1166087147
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.92435669
Short name T56
Test name
Test status
Simulation time 98539373287 ps
CPU time 553.49 seconds
Started May 02 04:10:33 PM PDT 24
Finished May 02 04:19:47 PM PDT 24
Peak memory 202664 kb
Host smart-97b39488-82a7-4a98-b50b-85a0ba326af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92435669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.92435669
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.2050833347
Short name T99
Test name
Test status
Simulation time 33875990934 ps
CPU time 8.59 seconds
Started May 02 04:10:32 PM PDT 24
Finished May 02 04:10:41 PM PDT 24
Peak memory 202104 kb
Host smart-3651b310-940b-4823-9b14-1f28cb77127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050833347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.2050833347
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3591293105
Short name T515
Test name
Test status
Simulation time 2913284835 ps
CPU time 7.58 seconds
Started May 02 04:10:32 PM PDT 24
Finished May 02 04:10:40 PM PDT 24
Peak memory 202148 kb
Host smart-390c8f9b-63d0-40ce-b8e7-523573899434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591293105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3591293105
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.4241096429
Short name T558
Test name
Test status
Simulation time 5841254708 ps
CPU time 3.55 seconds
Started May 02 04:10:27 PM PDT 24
Finished May 02 04:10:31 PM PDT 24
Peak memory 202132 kb
Host smart-ab698196-b2bb-4514-b8fb-736296bcdfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241096429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.4241096429
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2658316624
Short name T533
Test name
Test status
Simulation time 1178322213 ps
CPU time 1.37 seconds
Started May 02 04:10:34 PM PDT 24
Finished May 02 04:10:36 PM PDT 24
Peak memory 202004 kb
Host smart-067eef5e-8783-49df-b62c-91c3f0a851c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658316624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2658316624
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2314705926
Short name T303
Test name
Test status
Simulation time 227155548222 ps
CPU time 130.45 seconds
Started May 02 04:10:33 PM PDT 24
Finished May 02 04:12:44 PM PDT 24
Peak memory 210584 kb
Host smart-931fb159-b285-4490-842c-a9f14efd034f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314705926 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2314705926
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1524165966
Short name T345
Test name
Test status
Simulation time 330168663 ps
CPU time 0.8 seconds
Started May 02 04:10:52 PM PDT 24
Finished May 02 04:10:53 PM PDT 24
Peak memory 202036 kb
Host smart-13431aed-e0d6-4422-a1e8-39bd758033e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524165966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1524165966
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2750843039
Short name T416
Test name
Test status
Simulation time 321081401713 ps
CPU time 768.96 seconds
Started May 02 04:10:38 PM PDT 24
Finished May 02 04:23:27 PM PDT 24
Peak memory 202292 kb
Host smart-d29147a2-5aa5-4ccb-95b6-b12e72965137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750843039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2750843039
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.412309587
Short name T340
Test name
Test status
Simulation time 162422994384 ps
CPU time 103.87 seconds
Started May 02 04:10:39 PM PDT 24
Finished May 02 04:12:23 PM PDT 24
Peak memory 202300 kb
Host smart-00440220-57ef-41d3-b8f2-6187d83d60c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412309587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.412309587
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3100081382
Short name T280
Test name
Test status
Simulation time 163821173586 ps
CPU time 209.15 seconds
Started May 02 04:10:41 PM PDT 24
Finished May 02 04:14:10 PM PDT 24
Peak memory 202308 kb
Host smart-3c26f25c-4b68-44e5-8a33-2c14c8313394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100081382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3100081382
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.498877015
Short name T499
Test name
Test status
Simulation time 161804299685 ps
CPU time 392.59 seconds
Started May 02 04:10:39 PM PDT 24
Finished May 02 04:17:12 PM PDT 24
Peak memory 202304 kb
Host smart-d6dd1e18-012c-4744-9248-2d612688f273
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=498877015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.498877015
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.2494411952
Short name T135
Test name
Test status
Simulation time 528243290044 ps
CPU time 1142.07 seconds
Started May 02 04:10:40 PM PDT 24
Finished May 02 04:29:42 PM PDT 24
Peak memory 202272 kb
Host smart-13153974-4edf-42c0-8066-1d930d22ca2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494411952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.2494411952
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.794239374
Short name T431
Test name
Test status
Simulation time 605017232233 ps
CPU time 734.93 seconds
Started May 02 04:10:47 PM PDT 24
Finished May 02 04:23:02 PM PDT 24
Peak memory 202380 kb
Host smart-f303f7df-de31-4158-a9bb-4f45578d5327
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794239374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.794239374
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4125937495
Short name T783
Test name
Test status
Simulation time 108341587609 ps
CPU time 367.2 seconds
Started May 02 04:10:53 PM PDT 24
Finished May 02 04:17:01 PM PDT 24
Peak memory 202656 kb
Host smart-eaec22b9-0d6e-4011-b3c2-bdf0fd63e63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125937495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4125937495
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1187112112
Short name T391
Test name
Test status
Simulation time 40296713684 ps
CPU time 11.12 seconds
Started May 02 04:10:52 PM PDT 24
Finished May 02 04:11:03 PM PDT 24
Peak memory 202112 kb
Host smart-8dc0387d-5838-49b6-8df2-fbde58131650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187112112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1187112112
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2563481691
Short name T454
Test name
Test status
Simulation time 5421027690 ps
CPU time 3.65 seconds
Started May 02 04:10:45 PM PDT 24
Finished May 02 04:10:49 PM PDT 24
Peak memory 202132 kb
Host smart-e3b9786c-cf7a-4e36-ba30-8b4c0a0501ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563481691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2563481691
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.338587623
Short name T358
Test name
Test status
Simulation time 5577530985 ps
CPU time 8.08 seconds
Started May 02 04:10:39 PM PDT 24
Finished May 02 04:10:47 PM PDT 24
Peak memory 202140 kb
Host smart-6e6b2807-b105-4979-8da9-7df6ef62f9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338587623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.338587623
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.746435242
Short name T279
Test name
Test status
Simulation time 228377066664 ps
CPU time 115.94 seconds
Started May 02 04:10:53 PM PDT 24
Finished May 02 04:12:50 PM PDT 24
Peak memory 210688 kb
Host smart-3e8a345a-4325-497e-9f88-b055e3cc2ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746435242 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.746435242
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3573823747
Short name T702
Test name
Test status
Simulation time 303706842 ps
CPU time 1.26 seconds
Started May 02 04:11:05 PM PDT 24
Finished May 02 04:11:07 PM PDT 24
Peak memory 202012 kb
Host smart-e9f12609-c9ce-40ce-b8d1-5bb5c7e8b154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573823747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3573823747
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2805801028
Short name T168
Test name
Test status
Simulation time 368464076330 ps
CPU time 92.46 seconds
Started May 02 04:10:58 PM PDT 24
Finished May 02 04:12:31 PM PDT 24
Peak memory 202268 kb
Host smart-8fd4d2ad-a524-44b5-95d4-4ed4791343f1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805801028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2805801028
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3420293800
Short name T263
Test name
Test status
Simulation time 524930751822 ps
CPU time 758.15 seconds
Started May 02 04:11:00 PM PDT 24
Finished May 02 04:23:39 PM PDT 24
Peak memory 202320 kb
Host smart-bfd714f8-13b0-4ddf-a595-d00be191ff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420293800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3420293800
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.373463228
Short name T677
Test name
Test status
Simulation time 160638011222 ps
CPU time 139.74 seconds
Started May 02 04:10:57 PM PDT 24
Finished May 02 04:13:18 PM PDT 24
Peak memory 202336 kb
Host smart-16a507fc-2e15-41de-a03c-ef1031b71fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373463228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.373463228
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2008863603
Short name T344
Test name
Test status
Simulation time 485642203740 ps
CPU time 1125.15 seconds
Started May 02 04:10:58 PM PDT 24
Finished May 02 04:29:44 PM PDT 24
Peak memory 202320 kb
Host smart-a4ea6d9c-5a89-4c4e-881f-9bca099d3860
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008863603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2008863603
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.820539794
Short name T197
Test name
Test status
Simulation time 502222447074 ps
CPU time 579.9 seconds
Started May 02 04:10:53 PM PDT 24
Finished May 02 04:20:34 PM PDT 24
Peak memory 202324 kb
Host smart-6f3e0919-5e1d-4463-82ba-2bd5afe02a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820539794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.820539794
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.964386670
Short name T502
Test name
Test status
Simulation time 492807282671 ps
CPU time 1138.21 seconds
Started May 02 04:10:57 PM PDT 24
Finished May 02 04:29:56 PM PDT 24
Peak memory 202252 kb
Host smart-6e812249-f6f5-4e30-b435-85ce62fe0a58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=964386670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.964386670
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1698960733
Short name T217
Test name
Test status
Simulation time 357449264287 ps
CPU time 868.87 seconds
Started May 02 04:10:59 PM PDT 24
Finished May 02 04:25:28 PM PDT 24
Peak memory 202268 kb
Host smart-a833472a-634e-4b77-8b54-982af25bd011
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698960733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1698960733
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4208753030
Short name T334
Test name
Test status
Simulation time 622221146285 ps
CPU time 730.86 seconds
Started May 02 04:10:58 PM PDT 24
Finished May 02 04:23:09 PM PDT 24
Peak memory 202264 kb
Host smart-783c2355-e537-4623-a5d2-48b9d544782e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208753030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4208753030
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.699661919
Short name T386
Test name
Test status
Simulation time 103175100210 ps
CPU time 425.1 seconds
Started May 02 04:11:06 PM PDT 24
Finished May 02 04:18:12 PM PDT 24
Peak memory 202716 kb
Host smart-971d70be-1e08-4cde-9c8d-0ac62dd61adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699661919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.699661919
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1185297077
Short name T519
Test name
Test status
Simulation time 44179193075 ps
CPU time 52.24 seconds
Started May 02 04:10:57 PM PDT 24
Finished May 02 04:11:50 PM PDT 24
Peak memory 202084 kb
Host smart-acb672b3-ee6b-46f8-b265-23a95afcbe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185297077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1185297077
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1837255815
Short name T527
Test name
Test status
Simulation time 2917102425 ps
CPU time 3.6 seconds
Started May 02 04:10:57 PM PDT 24
Finished May 02 04:11:02 PM PDT 24
Peak memory 202112 kb
Host smart-9d88d891-1f41-4bbf-b322-75b206f1cba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837255815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1837255815
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1308847252
Short name T464
Test name
Test status
Simulation time 5661550562 ps
CPU time 6.79 seconds
Started May 02 04:10:51 PM PDT 24
Finished May 02 04:10:59 PM PDT 24
Peak memory 202140 kb
Host smart-de01780b-eeab-4413-8271-b9bbaf48378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308847252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1308847252
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.324067832
Short name T647
Test name
Test status
Simulation time 179633910700 ps
CPU time 137.6 seconds
Started May 02 04:11:04 PM PDT 24
Finished May 02 04:13:22 PM PDT 24
Peak memory 202312 kb
Host smart-1d3b3656-1c8d-4d3c-aacc-72920988f122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324067832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all.
324067832
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.634929305
Short name T708
Test name
Test status
Simulation time 41554552764 ps
CPU time 116.32 seconds
Started May 02 04:11:07 PM PDT 24
Finished May 02 04:13:04 PM PDT 24
Peak memory 211052 kb
Host smart-083a0e0c-ca17-477a-943d-fd7ab884216c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634929305 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.634929305
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2641267429
Short name T419
Test name
Test status
Simulation time 506557564 ps
CPU time 0.87 seconds
Started May 02 04:11:19 PM PDT 24
Finished May 02 04:11:21 PM PDT 24
Peak memory 202024 kb
Host smart-c711c464-87d5-4aaa-b8d4-1c65ee75099a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641267429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2641267429
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.463268964
Short name T269
Test name
Test status
Simulation time 327663938571 ps
CPU time 728.3 seconds
Started May 02 04:11:12 PM PDT 24
Finished May 02 04:23:21 PM PDT 24
Peak memory 202320 kb
Host smart-fd3e678a-6fdc-4ad7-8efa-25a66e3f1bf4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463268964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.463268964
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1343620790
Short name T210
Test name
Test status
Simulation time 335678341582 ps
CPU time 182.84 seconds
Started May 02 04:11:13 PM PDT 24
Finished May 02 04:14:17 PM PDT 24
Peak memory 202300 kb
Host smart-404b13e2-0cd7-4232-80d4-f8d177a0ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343620790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1343620790
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.954405227
Short name T92
Test name
Test status
Simulation time 169364824846 ps
CPU time 195.03 seconds
Started May 02 04:11:12 PM PDT 24
Finished May 02 04:14:28 PM PDT 24
Peak memory 202280 kb
Host smart-45e5b3dc-81b0-406b-b46d-e32a2db1c981
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=954405227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.954405227
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.1450433906
Short name T738
Test name
Test status
Simulation time 321370262461 ps
CPU time 190.38 seconds
Started May 02 04:11:04 PM PDT 24
Finished May 02 04:14:15 PM PDT 24
Peak memory 202332 kb
Host smart-981b6c73-244a-45f8-af30-121e0551eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450433906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.1450433906
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2748902737
Short name T576
Test name
Test status
Simulation time 487664192663 ps
CPU time 257.52 seconds
Started May 02 04:11:05 PM PDT 24
Finished May 02 04:15:23 PM PDT 24
Peak memory 202284 kb
Host smart-06754030-e0d1-4edc-922e-f61e2940f840
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748902737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2748902737
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1409995976
Short name T523
Test name
Test status
Simulation time 459793363745 ps
CPU time 199.06 seconds
Started May 02 04:11:11 PM PDT 24
Finished May 02 04:14:31 PM PDT 24
Peak memory 202388 kb
Host smart-6f89fafe-9cd5-4af8-9673-6da94368926e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409995976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1409995976
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3377643092
Short name T698
Test name
Test status
Simulation time 596464225123 ps
CPU time 1393.94 seconds
Started May 02 04:11:11 PM PDT 24
Finished May 02 04:34:25 PM PDT 24
Peak memory 202244 kb
Host smart-0d93a5fc-0d1c-4b13-8f32-434fe508587c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377643092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3377643092
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1749252077
Short name T468
Test name
Test status
Simulation time 131374797754 ps
CPU time 451.65 seconds
Started May 02 04:11:11 PM PDT 24
Finished May 02 04:18:43 PM PDT 24
Peak memory 202640 kb
Host smart-db8e9671-8b4d-464f-a789-e1e1343103d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749252077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1749252077
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.546504948
Short name T667
Test name
Test status
Simulation time 24547165613 ps
CPU time 14.92 seconds
Started May 02 04:11:12 PM PDT 24
Finished May 02 04:11:28 PM PDT 24
Peak memory 202148 kb
Host smart-01f48558-217f-441b-affd-f71274a14370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546504948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.546504948
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3961265957
Short name T668
Test name
Test status
Simulation time 4053722134 ps
CPU time 2.99 seconds
Started May 02 04:11:12 PM PDT 24
Finished May 02 04:11:16 PM PDT 24
Peak memory 202120 kb
Host smart-9e177341-c021-463f-bbca-c24036efd45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961265957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3961265957
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2244709669
Short name T557
Test name
Test status
Simulation time 5938542355 ps
CPU time 4.11 seconds
Started May 02 04:11:08 PM PDT 24
Finished May 02 04:11:12 PM PDT 24
Peak memory 202124 kb
Host smart-6fe96c9d-9a9d-45cc-a023-b9339709864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244709669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2244709669
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1638088965
Short name T252
Test name
Test status
Simulation time 24289973442 ps
CPU time 57.92 seconds
Started May 02 04:11:17 PM PDT 24
Finished May 02 04:12:16 PM PDT 24
Peak memory 202412 kb
Host smart-ee8efeb6-f031-4920-8c85-610d8d0d00ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638088965 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1638088965
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2696026502
Short name T518
Test name
Test status
Simulation time 412550109 ps
CPU time 1.59 seconds
Started May 02 04:11:25 PM PDT 24
Finished May 02 04:11:27 PM PDT 24
Peak memory 201984 kb
Host smart-240ce4fe-370c-48b3-87fe-b8fb934123d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696026502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2696026502
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1391817534
Short name T174
Test name
Test status
Simulation time 454280001949 ps
CPU time 255.95 seconds
Started May 02 04:11:25 PM PDT 24
Finished May 02 04:15:42 PM PDT 24
Peak memory 202304 kb
Host smart-62d57728-954f-423b-9de2-d0f0460a1be1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391817534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1391817534
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3633669368
Short name T145
Test name
Test status
Simulation time 194716081011 ps
CPU time 470.89 seconds
Started May 02 04:11:23 PM PDT 24
Finished May 02 04:19:15 PM PDT 24
Peak memory 202296 kb
Host smart-ceabd3f6-91c4-4cec-b793-184f82e5e8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633669368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3633669368
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1913684761
Short name T505
Test name
Test status
Simulation time 495380281806 ps
CPU time 982.04 seconds
Started May 02 04:11:18 PM PDT 24
Finished May 02 04:27:41 PM PDT 24
Peak memory 202244 kb
Host smart-0d91bf03-4a11-432c-9efc-5be1e6f88222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913684761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1913684761
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1142170546
Short name T628
Test name
Test status
Simulation time 167290590476 ps
CPU time 258.51 seconds
Started May 02 04:11:18 PM PDT 24
Finished May 02 04:15:37 PM PDT 24
Peak memory 202252 kb
Host smart-14d35e15-2e86-4be3-9aaa-fd3aa6495310
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142170546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1142170546
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3295506684
Short name T561
Test name
Test status
Simulation time 163042161625 ps
CPU time 377.22 seconds
Started May 02 04:11:17 PM PDT 24
Finished May 02 04:17:35 PM PDT 24
Peak memory 202316 kb
Host smart-c1f8381b-53ff-4bb8-89a2-d52a5507b027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295506684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3295506684
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.4213314330
Short name T333
Test name
Test status
Simulation time 162405615426 ps
CPU time 365.25 seconds
Started May 02 04:11:19 PM PDT 24
Finished May 02 04:17:25 PM PDT 24
Peak memory 202280 kb
Host smart-47904559-6c7a-4c01-a572-5e937ed9ee58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213314330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.4213314330
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.689392180
Short name T646
Test name
Test status
Simulation time 407389068157 ps
CPU time 507.92 seconds
Started May 02 04:11:17 PM PDT 24
Finished May 02 04:19:46 PM PDT 24
Peak memory 202260 kb
Host smart-fbd11267-f70b-45a9-9c7f-aa06f185283e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689392180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.689392180
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.3304222405
Short name T779
Test name
Test status
Simulation time 107024588504 ps
CPU time 402.03 seconds
Started May 02 04:11:23 PM PDT 24
Finished May 02 04:18:06 PM PDT 24
Peak memory 202696 kb
Host smart-0fde7c8e-de59-494c-a860-e2337e4bea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304222405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.3304222405
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.906705039
Short name T342
Test name
Test status
Simulation time 34112040015 ps
CPU time 74.12 seconds
Started May 02 04:11:25 PM PDT 24
Finished May 02 04:12:39 PM PDT 24
Peak memory 202144 kb
Host smart-17f5f4db-e5b6-4158-9327-8b404186a9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906705039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.906705039
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2887590322
Short name T771
Test name
Test status
Simulation time 3178504651 ps
CPU time 9.12 seconds
Started May 02 04:11:24 PM PDT 24
Finished May 02 04:11:34 PM PDT 24
Peak memory 202116 kb
Host smart-9dee91d5-38ea-44a1-8e5e-ad4f5ee6df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887590322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2887590322
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2978239906
Short name T789
Test name
Test status
Simulation time 5813700071 ps
CPU time 4.34 seconds
Started May 02 04:11:18 PM PDT 24
Finished May 02 04:11:22 PM PDT 24
Peak memory 202104 kb
Host smart-8399c7f4-c9de-40a1-a670-dfacef855279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978239906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2978239906
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.468174573
Short name T190
Test name
Test status
Simulation time 524033702661 ps
CPU time 668.9 seconds
Started May 02 04:11:25 PM PDT 24
Finished May 02 04:22:34 PM PDT 24
Peak memory 202680 kb
Host smart-48d9a0a6-d669-47db-ba11-3051afb318fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468174573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
468174573
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.4250325724
Short name T23
Test name
Test status
Simulation time 131891578374 ps
CPU time 75.44 seconds
Started May 02 04:11:25 PM PDT 24
Finished May 02 04:12:41 PM PDT 24
Peak memory 212172 kb
Host smart-6021236e-8b45-421a-aa2c-780f3abe218d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250325724 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.4250325724
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3622577570
Short name T714
Test name
Test status
Simulation time 516121360 ps
CPU time 1.9 seconds
Started May 02 04:11:45 PM PDT 24
Finished May 02 04:11:48 PM PDT 24
Peak memory 201964 kb
Host smart-7464f48e-4301-4199-aaac-6331eb21aa70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622577570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3622577570
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.3703463925
Short name T122
Test name
Test status
Simulation time 364470369086 ps
CPU time 216.47 seconds
Started May 02 04:11:37 PM PDT 24
Finished May 02 04:15:14 PM PDT 24
Peak memory 202304 kb
Host smart-4b6fd4f7-9650-4292-817e-3b176a6bf9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703463925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.3703463925
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.159817441
Short name T307
Test name
Test status
Simulation time 490503483258 ps
CPU time 887.84 seconds
Started May 02 04:11:35 PM PDT 24
Finished May 02 04:26:24 PM PDT 24
Peak memory 202316 kb
Host smart-e6e0c054-9b1d-497e-8b96-2681a8b292d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159817441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.159817441
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.2544803386
Short name T328
Test name
Test status
Simulation time 504336755785 ps
CPU time 1212.74 seconds
Started May 02 04:11:32 PM PDT 24
Finished May 02 04:31:45 PM PDT 24
Peak memory 202308 kb
Host smart-fc8645f9-46b9-4237-90eb-d96d96fd4daf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544803386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.2544803386
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.521271534
Short name T469
Test name
Test status
Simulation time 164503531315 ps
CPU time 225.32 seconds
Started May 02 04:11:31 PM PDT 24
Finished May 02 04:15:17 PM PDT 24
Peak memory 202400 kb
Host smart-9647dde0-0ec3-42b2-b8fc-3a8b217c039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521271534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.521271534
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2708911570
Short name T458
Test name
Test status
Simulation time 165486707427 ps
CPU time 53.74 seconds
Started May 02 04:11:31 PM PDT 24
Finished May 02 04:12:26 PM PDT 24
Peak memory 202396 kb
Host smart-f20c6840-e59e-43f5-a4f7-10bbd61f9b90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708911570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2708911570
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4165899458
Short name T649
Test name
Test status
Simulation time 328316249815 ps
CPU time 763.14 seconds
Started May 02 04:11:31 PM PDT 24
Finished May 02 04:24:15 PM PDT 24
Peak memory 202300 kb
Host smart-bc921b3c-98d8-4583-8366-c0742207a5a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165899458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4165899458
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.1679040717
Short name T498
Test name
Test status
Simulation time 410761136728 ps
CPU time 174.5 seconds
Started May 02 04:11:30 PM PDT 24
Finished May 02 04:14:25 PM PDT 24
Peak memory 202328 kb
Host smart-7e4d3d0f-f134-4fd9-9b8d-e31c45565d27
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679040717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.1679040717
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1299180122
Short name T417
Test name
Test status
Simulation time 122864272106 ps
CPU time 427.56 seconds
Started May 02 04:11:35 PM PDT 24
Finished May 02 04:18:43 PM PDT 24
Peak memory 202732 kb
Host smart-cfa36748-f8a9-4826-94e0-5915b75e9c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299180122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1299180122
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.306995811
Short name T520
Test name
Test status
Simulation time 28188702367 ps
CPU time 32.5 seconds
Started May 02 04:11:41 PM PDT 24
Finished May 02 04:12:15 PM PDT 24
Peak memory 202092 kb
Host smart-199ede0e-4514-4171-ae27-6859462ac58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306995811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.306995811
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1896671800
Short name T331
Test name
Test status
Simulation time 3594054713 ps
CPU time 4.9 seconds
Started May 02 04:11:37 PM PDT 24
Finished May 02 04:11:43 PM PDT 24
Peak memory 202132 kb
Host smart-42874d12-387e-4cc8-94d0-833f20fb03d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896671800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1896671800
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1599847644
Short name T456
Test name
Test status
Simulation time 5685831504 ps
CPU time 14.75 seconds
Started May 02 04:11:32 PM PDT 24
Finished May 02 04:11:48 PM PDT 24
Peak memory 202096 kb
Host smart-aa60d862-5e66-4f82-91ed-604b0e0e0f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599847644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1599847644
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.302370404
Short name T619
Test name
Test status
Simulation time 173462775816 ps
CPU time 229.02 seconds
Started May 02 04:11:36 PM PDT 24
Finished May 02 04:15:26 PM PDT 24
Peak memory 202296 kb
Host smart-addb1f47-bd3f-46b3-bf39-934102a16fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302370404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
302370404
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2161764883
Short name T746
Test name
Test status
Simulation time 135845417211 ps
CPU time 40.95 seconds
Started May 02 04:11:36 PM PDT 24
Finished May 02 04:12:18 PM PDT 24
Peak memory 210644 kb
Host smart-4872a08b-8cf7-477d-9fbd-e0124a8dae50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161764883 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2161764883
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.172064567
Short name T725
Test name
Test status
Simulation time 477580551 ps
CPU time 0.78 seconds
Started May 02 04:11:49 PM PDT 24
Finished May 02 04:11:51 PM PDT 24
Peak memory 201956 kb
Host smart-61f8deff-224a-45cc-9d5b-a0c98a219706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172064567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.172064567
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3809242884
Short name T283
Test name
Test status
Simulation time 487192145912 ps
CPU time 155.13 seconds
Started May 02 04:11:48 PM PDT 24
Finished May 02 04:14:24 PM PDT 24
Peak memory 202188 kb
Host smart-ca2f728d-9d89-4ca7-9675-e835a01da871
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809242884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3809242884
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2921019411
Short name T534
Test name
Test status
Simulation time 189671393228 ps
CPU time 208.2 seconds
Started May 02 04:11:49 PM PDT 24
Finished May 02 04:15:18 PM PDT 24
Peak memory 202320 kb
Host smart-a5b6ae9b-cf4c-4c83-b431-04fd7ed4657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921019411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2921019411
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.1180942989
Short name T202
Test name
Test status
Simulation time 336441316784 ps
CPU time 793.21 seconds
Started May 02 04:11:49 PM PDT 24
Finished May 02 04:25:03 PM PDT 24
Peak memory 202280 kb
Host smart-32f945bf-cb82-4fab-96cd-73bbb7856f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180942989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.1180942989
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2054055736
Short name T466
Test name
Test status
Simulation time 169012207925 ps
CPU time 105.79 seconds
Started May 02 04:11:48 PM PDT 24
Finished May 02 04:13:35 PM PDT 24
Peak memory 202260 kb
Host smart-3cd7cfae-d029-477e-aa52-46c24323f0e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054055736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2054055736
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.130353027
Short name T639
Test name
Test status
Simulation time 337639749171 ps
CPU time 326.83 seconds
Started May 02 04:11:41 PM PDT 24
Finished May 02 04:17:09 PM PDT 24
Peak memory 202388 kb
Host smart-4e554389-ce08-4c07-8b4c-c25c270b6a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130353027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.130353027
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.9499632
Short name T424
Test name
Test status
Simulation time 484041333341 ps
CPU time 274.13 seconds
Started May 02 04:11:48 PM PDT 24
Finished May 02 04:16:23 PM PDT 24
Peak memory 202340 kb
Host smart-fd1b9ce6-2cf9-45de-82aa-2e789cc2d53b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=9499632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fixed.9499632
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.659380549
Short name T134
Test name
Test status
Simulation time 359164442526 ps
CPU time 852.88 seconds
Started May 02 04:11:40 PM PDT 24
Finished May 02 04:25:54 PM PDT 24
Peak memory 202376 kb
Host smart-72be064e-5dfb-432a-ad62-f50da219ce15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659380549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.659380549
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.3308883318
Short name T582
Test name
Test status
Simulation time 600625884534 ps
CPU time 346.43 seconds
Started May 02 04:11:42 PM PDT 24
Finished May 02 04:17:29 PM PDT 24
Peak memory 202308 kb
Host smart-73c7fec7-a4b1-455a-a171-0f0c75d1c999
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308883318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.3308883318
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2290146822
Short name T470
Test name
Test status
Simulation time 69529246063 ps
CPU time 371.91 seconds
Started May 02 04:11:48 PM PDT 24
Finished May 02 04:18:01 PM PDT 24
Peak memory 202600 kb
Host smart-460013ff-60a6-48d8-bff1-100ac60ad363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290146822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2290146822
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2759042849
Short name T388
Test name
Test status
Simulation time 26945308799 ps
CPU time 27.62 seconds
Started May 02 04:11:47 PM PDT 24
Finished May 02 04:12:15 PM PDT 24
Peak memory 202128 kb
Host smart-a133ae00-41e1-415e-a8a6-2d1cf6503ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759042849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2759042849
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2488038407
Short name T653
Test name
Test status
Simulation time 4116776742 ps
CPU time 2.33 seconds
Started May 02 04:11:47 PM PDT 24
Finished May 02 04:11:51 PM PDT 24
Peak memory 202128 kb
Host smart-f7fd3d56-ae15-4e87-87c5-1ad404c79a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488038407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2488038407
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1541251230
Short name T595
Test name
Test status
Simulation time 5848728323 ps
CPU time 4.14 seconds
Started May 02 04:11:45 PM PDT 24
Finished May 02 04:11:50 PM PDT 24
Peak memory 202104 kb
Host smart-40440fe7-b173-4379-bdee-86f074b9c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541251230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1541251230
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2280913471
Short name T237
Test name
Test status
Simulation time 373556975919 ps
CPU time 793.2 seconds
Started May 02 04:11:50 PM PDT 24
Finished May 02 04:25:04 PM PDT 24
Peak memory 202404 kb
Host smart-9d37fb45-f997-41c1-a39d-9eb8a17434fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280913471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2280913471
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.4234834598
Short name T97
Test name
Test status
Simulation time 189690253456 ps
CPU time 431.08 seconds
Started May 02 04:11:48 PM PDT 24
Finished May 02 04:19:00 PM PDT 24
Peak memory 211072 kb
Host smart-ed5f45a6-1f1c-42f7-820c-08a3153f9238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234834598 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.4234834598
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2717631910
Short name T382
Test name
Test status
Simulation time 488957725 ps
CPU time 1.74 seconds
Started May 02 04:00:37 PM PDT 24
Finished May 02 04:00:40 PM PDT 24
Peak memory 201948 kb
Host smart-f2d53a7f-0c39-4b8d-972a-13faa4554a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717631910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2717631910
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3616766790
Short name T238
Test name
Test status
Simulation time 173095573769 ps
CPU time 222.85 seconds
Started May 02 04:00:38 PM PDT 24
Finished May 02 04:04:21 PM PDT 24
Peak memory 202356 kb
Host smart-f0302d9a-aa2f-4ea6-9965-727479ee8672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616766790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3616766790
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2306593861
Short name T776
Test name
Test status
Simulation time 487645491487 ps
CPU time 561.56 seconds
Started May 02 04:00:34 PM PDT 24
Finished May 02 04:09:56 PM PDT 24
Peak memory 202316 kb
Host smart-3b77661b-d0f2-412b-b82b-5e5719f97433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306593861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2306593861
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2884056972
Short name T403
Test name
Test status
Simulation time 165930676110 ps
CPU time 391.3 seconds
Started May 02 04:00:36 PM PDT 24
Finished May 02 04:07:08 PM PDT 24
Peak memory 202308 kb
Host smart-2ca16095-5734-48d2-a872-e4985f312657
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884056972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2884056972
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2150714138
Short name T494
Test name
Test status
Simulation time 163236569739 ps
CPU time 354.07 seconds
Started May 02 04:00:32 PM PDT 24
Finished May 02 04:06:27 PM PDT 24
Peak memory 202320 kb
Host smart-3802f76a-c463-4948-b7f3-de9b120d52c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150714138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2150714138
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3198443089
Short name T526
Test name
Test status
Simulation time 328045277860 ps
CPU time 720.58 seconds
Started May 02 04:00:32 PM PDT 24
Finished May 02 04:12:34 PM PDT 24
Peak memory 202292 kb
Host smart-ef1098d7-343c-4baa-afa5-0a616f3727f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198443089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3198443089
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1634486149
Short name T125
Test name
Test status
Simulation time 187574873786 ps
CPU time 424 seconds
Started May 02 04:00:32 PM PDT 24
Finished May 02 04:07:36 PM PDT 24
Peak memory 202288 kb
Host smart-0fc1a673-83a4-477d-8174-684f4e1ebdb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634486149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1634486149
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2122735515
Short name T392
Test name
Test status
Simulation time 189687007761 ps
CPU time 124.61 seconds
Started May 02 04:00:31 PM PDT 24
Finished May 02 04:02:36 PM PDT 24
Peak memory 202280 kb
Host smart-790e528c-e2ca-4fd9-b9a1-196a084d27f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122735515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2122735515
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.168739443
Short name T607
Test name
Test status
Simulation time 84040217870 ps
CPU time 318.76 seconds
Started May 02 04:00:39 PM PDT 24
Finished May 02 04:05:58 PM PDT 24
Peak memory 202736 kb
Host smart-45dcde5f-1da3-4f34-8340-6289282fb2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168739443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.168739443
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2718223548
Short name T356
Test name
Test status
Simulation time 42816050951 ps
CPU time 14.52 seconds
Started May 02 04:00:41 PM PDT 24
Finished May 02 04:00:56 PM PDT 24
Peak memory 202108 kb
Host smart-07d0eda2-6312-4a74-b87a-c9bcfc438e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718223548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2718223548
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3637305397
Short name T620
Test name
Test status
Simulation time 4641982320 ps
CPU time 11.77 seconds
Started May 02 04:00:39 PM PDT 24
Finished May 02 04:00:51 PM PDT 24
Peak memory 202108 kb
Host smart-a593122b-61ce-40fc-92e3-d5b1798f2db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637305397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3637305397
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3386236827
Short name T442
Test name
Test status
Simulation time 5540384356 ps
CPU time 14.74 seconds
Started May 02 04:00:31 PM PDT 24
Finished May 02 04:00:47 PM PDT 24
Peak memory 202100 kb
Host smart-3cd37c14-cfef-4070-aaf4-b7f3a0f50640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386236827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3386236827
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2181665535
Short name T691
Test name
Test status
Simulation time 493009344555 ps
CPU time 306.23 seconds
Started May 02 04:00:38 PM PDT 24
Finished May 02 04:05:45 PM PDT 24
Peak memory 202332 kb
Host smart-ab4c4ac3-3fe4-4fe9-a11e-633f96edd6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181665535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2181665535
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1755282792
Short name T18
Test name
Test status
Simulation time 58369912891 ps
CPU time 68.68 seconds
Started May 02 04:00:37 PM PDT 24
Finished May 02 04:01:47 PM PDT 24
Peak memory 210708 kb
Host smart-1808bc8f-7d50-49b8-85a7-bd5030690bd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755282792 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1755282792
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.4149296226
Short name T491
Test name
Test status
Simulation time 508742751 ps
CPU time 1.73 seconds
Started May 02 04:00:51 PM PDT 24
Finished May 02 04:00:53 PM PDT 24
Peak memory 202008 kb
Host smart-f69bef65-b0c6-43b5-ae38-57eabc8714d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149296226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.4149296226
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3357344909
Short name T95
Test name
Test status
Simulation time 329624851914 ps
CPU time 392.16 seconds
Started May 02 04:00:46 PM PDT 24
Finished May 02 04:07:19 PM PDT 24
Peak memory 202360 kb
Host smart-82a26a72-7a6d-4553-bd44-827002836207
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357344909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3357344909
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1146933888
Short name T765
Test name
Test status
Simulation time 332156646097 ps
CPU time 405.23 seconds
Started May 02 04:00:51 PM PDT 24
Finished May 02 04:07:37 PM PDT 24
Peak memory 202308 kb
Host smart-fdd1c4a4-a732-4d96-bb36-f3ee1815a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146933888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1146933888
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2417230593
Short name T156
Test name
Test status
Simulation time 331958416184 ps
CPU time 187.94 seconds
Started May 02 04:00:38 PM PDT 24
Finished May 02 04:03:47 PM PDT 24
Peak memory 202368 kb
Host smart-e3ac816f-b5d6-42a7-9e57-5bd6ead8dd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417230593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2417230593
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1271247882
Short name T729
Test name
Test status
Simulation time 330792654147 ps
CPU time 752.59 seconds
Started May 02 04:00:46 PM PDT 24
Finished May 02 04:13:20 PM PDT 24
Peak memory 202336 kb
Host smart-fe7f63cf-20aa-4c39-a058-b25d2ae8d5cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271247882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1271247882
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3595880696
Short name T583
Test name
Test status
Simulation time 164767743954 ps
CPU time 60.54 seconds
Started May 02 04:00:38 PM PDT 24
Finished May 02 04:01:40 PM PDT 24
Peak memory 202404 kb
Host smart-ed6a389d-8552-4482-8fa2-fdcfe1bebf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595880696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3595880696
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1628161749
Short name T657
Test name
Test status
Simulation time 165846733595 ps
CPU time 200.1 seconds
Started May 02 04:00:39 PM PDT 24
Finished May 02 04:04:00 PM PDT 24
Peak memory 202328 kb
Host smart-412d4295-b3a3-4ac5-961f-009c29887b22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628161749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1628161749
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3095905692
Short name T787
Test name
Test status
Simulation time 560395074698 ps
CPU time 1311.71 seconds
Started May 02 04:00:44 PM PDT 24
Finished May 02 04:22:37 PM PDT 24
Peak memory 202400 kb
Host smart-1c001e1c-3499-4c32-96a9-2b2c337c19bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095905692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3095905692
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4291729195
Short name T513
Test name
Test status
Simulation time 397493370942 ps
CPU time 238.07 seconds
Started May 02 04:00:45 PM PDT 24
Finished May 02 04:04:44 PM PDT 24
Peak memory 202260 kb
Host smart-95c24294-0a76-4a7f-af1e-40dd1b413b0b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291729195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4291729195
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.3897427211
Short name T517
Test name
Test status
Simulation time 115551796100 ps
CPU time 568.59 seconds
Started May 02 04:00:51 PM PDT 24
Finished May 02 04:10:20 PM PDT 24
Peak memory 202660 kb
Host smart-d464d5bc-4182-410b-a7af-d51dd6d5e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897427211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.3897427211
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2163207146
Short name T757
Test name
Test status
Simulation time 39241488692 ps
CPU time 15.42 seconds
Started May 02 04:00:50 PM PDT 24
Finished May 02 04:01:06 PM PDT 24
Peak memory 202144 kb
Host smart-1eed3573-db52-4c30-9ff8-02fb58a72d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163207146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2163207146
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.720984207
Short name T752
Test name
Test status
Simulation time 3205743279 ps
CPU time 4.29 seconds
Started May 02 04:00:51 PM PDT 24
Finished May 02 04:00:56 PM PDT 24
Peak memory 202100 kb
Host smart-dac45a84-f686-4f25-9d4f-430cf6f4cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720984207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.720984207
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3145953617
Short name T429
Test name
Test status
Simulation time 5878741472 ps
CPU time 7.93 seconds
Started May 02 04:00:37 PM PDT 24
Finished May 02 04:00:46 PM PDT 24
Peak memory 202124 kb
Host smart-a292ab51-d68c-4fb5-9b92-dbfce3299533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145953617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3145953617
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2398860397
Short name T700
Test name
Test status
Simulation time 362596477 ps
CPU time 1.46 seconds
Started May 02 04:01:12 PM PDT 24
Finished May 02 04:01:14 PM PDT 24
Peak memory 201996 kb
Host smart-ea75e14e-8859-45fe-99bf-5de3f5960d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398860397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2398860397
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1209506827
Short name T266
Test name
Test status
Simulation time 161038400612 ps
CPU time 121.39 seconds
Started May 02 04:00:58 PM PDT 24
Finished May 02 04:03:00 PM PDT 24
Peak memory 202320 kb
Host smart-bf8193ac-aa8e-4b7d-b5b1-c6917e186857
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209506827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1209506827
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.639820567
Short name T479
Test name
Test status
Simulation time 170305241644 ps
CPU time 395.38 seconds
Started May 02 04:01:04 PM PDT 24
Finished May 02 04:07:41 PM PDT 24
Peak memory 202364 kb
Host smart-8ba66809-f756-4449-9712-1a367610c912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639820567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.639820567
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.326714944
Short name T297
Test name
Test status
Simulation time 489299045798 ps
CPU time 888.94 seconds
Started May 02 04:00:58 PM PDT 24
Finished May 02 04:15:47 PM PDT 24
Peak memory 202312 kb
Host smart-b117556d-dba4-4b9a-a44e-0c964a150115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326714944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.326714944
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2511681900
Short name T488
Test name
Test status
Simulation time 488824910983 ps
CPU time 1155.11 seconds
Started May 02 04:00:59 PM PDT 24
Finished May 02 04:20:15 PM PDT 24
Peak memory 202288 kb
Host smart-dd733691-9a1f-4234-becf-bb9fb63c2343
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511681900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2511681900
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1783465017
Short name T602
Test name
Test status
Simulation time 488459954486 ps
CPU time 464.64 seconds
Started May 02 04:00:59 PM PDT 24
Finished May 02 04:08:44 PM PDT 24
Peak memory 202268 kb
Host smart-2bc4b773-8d4f-417b-bbc9-3420ca3c2d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783465017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1783465017
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.303870757
Short name T536
Test name
Test status
Simulation time 330130733398 ps
CPU time 63.38 seconds
Started May 02 04:00:58 PM PDT 24
Finished May 02 04:02:02 PM PDT 24
Peak memory 202284 kb
Host smart-c2deb6c4-a1e1-4c51-bbe8-d7df6493e470
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=303870757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.303870757
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1569981260
Short name T165
Test name
Test status
Simulation time 565213780777 ps
CPU time 289.81 seconds
Started May 02 04:01:00 PM PDT 24
Finished May 02 04:05:51 PM PDT 24
Peak memory 202268 kb
Host smart-2f6944f5-ab9e-4915-b1f8-7162dad9b1ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569981260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1569981260
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3036913896
Short name T623
Test name
Test status
Simulation time 619858842539 ps
CPU time 1375.13 seconds
Started May 02 04:01:00 PM PDT 24
Finished May 02 04:23:57 PM PDT 24
Peak memory 202228 kb
Host smart-64fbaf02-c0e5-4d13-b456-6dd2189ced2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036913896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3036913896
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1367913193
Short name T594
Test name
Test status
Simulation time 66766632514 ps
CPU time 258.53 seconds
Started May 02 04:01:04 PM PDT 24
Finished May 02 04:05:24 PM PDT 24
Peak memory 202696 kb
Host smart-97587489-a939-47f5-aaee-03d228360085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367913193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1367913193
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1488292040
Short name T355
Test name
Test status
Simulation time 38729564060 ps
CPU time 19.53 seconds
Started May 02 04:01:10 PM PDT 24
Finished May 02 04:01:30 PM PDT 24
Peak memory 202144 kb
Host smart-24d0ba6f-63c7-4015-8942-17a63c31518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488292040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1488292040
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.2634778478
Short name T618
Test name
Test status
Simulation time 4993614148 ps
CPU time 3.47 seconds
Started May 02 04:01:05 PM PDT 24
Finished May 02 04:01:09 PM PDT 24
Peak memory 202144 kb
Host smart-1db6bcce-aaf5-4f41-9d68-6592bc20972e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634778478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.2634778478
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.1410131535
Short name T635
Test name
Test status
Simulation time 5900994195 ps
CPU time 14.66 seconds
Started May 02 04:01:00 PM PDT 24
Finished May 02 04:01:16 PM PDT 24
Peak memory 202092 kb
Host smart-d616bc76-6f6b-4198-a7c9-6ecc20ba3868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410131535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.1410131535
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1906102744
Short name T644
Test name
Test status
Simulation time 291611648130 ps
CPU time 874.83 seconds
Started May 02 04:01:13 PM PDT 24
Finished May 02 04:15:48 PM PDT 24
Peak memory 202680 kb
Host smart-552c0a97-eb38-4273-89e1-99029890393e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906102744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1906102744
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3684013513
Short name T192
Test name
Test status
Simulation time 93252735402 ps
CPU time 188.08 seconds
Started May 02 04:01:05 PM PDT 24
Finished May 02 04:04:14 PM PDT 24
Peak memory 210968 kb
Host smart-529a7927-5c8f-43e4-9c31-50a84f323b8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684013513 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3684013513
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.922105206
Short name T573
Test name
Test status
Simulation time 533449990 ps
CPU time 1.92 seconds
Started May 02 04:01:26 PM PDT 24
Finished May 02 04:01:29 PM PDT 24
Peak memory 201944 kb
Host smart-b5547a04-145f-42a2-9051-2506dfe34b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922105206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.922105206
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2581332200
Short name T243
Test name
Test status
Simulation time 322144766228 ps
CPU time 405.06 seconds
Started May 02 04:01:15 PM PDT 24
Finished May 02 04:08:01 PM PDT 24
Peak memory 202280 kb
Host smart-a4247924-9953-4a01-a2ed-cffc3f27a169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581332200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2581332200
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2603288527
Short name T365
Test name
Test status
Simulation time 484061840930 ps
CPU time 553.73 seconds
Started May 02 04:01:12 PM PDT 24
Finished May 02 04:10:27 PM PDT 24
Peak memory 202380 kb
Host smart-3812d665-32f8-455c-ad8e-6589655f3f81
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603288527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2603288527
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2477830880
Short name T130
Test name
Test status
Simulation time 326281498972 ps
CPU time 207.46 seconds
Started May 02 04:01:12 PM PDT 24
Finished May 02 04:04:40 PM PDT 24
Peak memory 202404 kb
Host smart-8f916ed9-60c7-47cf-8f04-74adae33cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477830880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2477830880
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.226692528
Short name T411
Test name
Test status
Simulation time 501773161900 ps
CPU time 648.56 seconds
Started May 02 04:01:12 PM PDT 24
Finished May 02 04:12:01 PM PDT 24
Peak memory 202312 kb
Host smart-10784fdc-1313-4349-af5c-c6628d4aceb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=226692528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixed
.226692528
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.166689067
Short name T306
Test name
Test status
Simulation time 346208470028 ps
CPU time 375.11 seconds
Started May 02 04:01:14 PM PDT 24
Finished May 02 04:07:30 PM PDT 24
Peak memory 202284 kb
Host smart-02f1ae3b-88af-4149-8c91-c4c269740c0c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166689067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_w
akeup.166689067
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2565951118
Short name T711
Test name
Test status
Simulation time 618081800843 ps
CPU time 1367.49 seconds
Started May 02 04:01:12 PM PDT 24
Finished May 02 04:24:00 PM PDT 24
Peak memory 202268 kb
Host smart-0b8cfd51-f793-49be-9c36-c7aadc91c0ec
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565951118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2565951118
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2913509245
Short name T188
Test name
Test status
Simulation time 98286340092 ps
CPU time 590.11 seconds
Started May 02 04:01:19 PM PDT 24
Finished May 02 04:11:10 PM PDT 24
Peak memory 202660 kb
Host smart-c7ff225d-9f14-4105-b3bd-e3fa7ee91ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913509245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2913509245
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.796875129
Short name T129
Test name
Test status
Simulation time 27438319071 ps
CPU time 66.67 seconds
Started May 02 04:01:18 PM PDT 24
Finished May 02 04:02:25 PM PDT 24
Peak memory 202080 kb
Host smart-691f0131-8bb3-4fdd-bf03-6a722ce3c761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796875129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.796875129
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.4274943536
Short name T684
Test name
Test status
Simulation time 4827084989 ps
CPU time 5.78 seconds
Started May 02 04:01:19 PM PDT 24
Finished May 02 04:01:25 PM PDT 24
Peak memory 202100 kb
Host smart-faf95a2a-a63f-4527-bce5-0848b6278c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274943536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.4274943536
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.3450457317
Short name T672
Test name
Test status
Simulation time 5934093667 ps
CPU time 14.18 seconds
Started May 02 04:01:14 PM PDT 24
Finished May 02 04:01:29 PM PDT 24
Peak memory 202100 kb
Host smart-2e269d37-ad44-4d83-bbfc-7d5df601a7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450457317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.3450457317
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.317725095
Short name T132
Test name
Test status
Simulation time 372358706381 ps
CPU time 826.48 seconds
Started May 02 04:01:18 PM PDT 24
Finished May 02 04:15:05 PM PDT 24
Peak memory 202368 kb
Host smart-e447f48c-1b82-4306-afbf-8d7646a700bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317725095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.317725095
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1575625364
Short name T609
Test name
Test status
Simulation time 73058210643 ps
CPU time 129.01 seconds
Started May 02 04:01:18 PM PDT 24
Finished May 02 04:03:28 PM PDT 24
Peak memory 218512 kb
Host smart-a97ec86e-42e5-4c11-b3b6-996cf2ac03aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575625364 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1575625364
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1591827812
Short name T552
Test name
Test status
Simulation time 646557380 ps
CPU time 0.72 seconds
Started May 02 04:01:37 PM PDT 24
Finished May 02 04:01:39 PM PDT 24
Peak memory 201976 kb
Host smart-d80c790b-45b6-46e9-8a4f-32a1ca67acbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591827812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1591827812
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2999226905
Short name T720
Test name
Test status
Simulation time 355124614385 ps
CPU time 110.36 seconds
Started May 02 04:01:34 PM PDT 24
Finished May 02 04:03:25 PM PDT 24
Peak memory 202312 kb
Host smart-39261935-44c4-47a3-ae9f-95b0ac127d30
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999226905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2999226905
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.936846749
Short name T253
Test name
Test status
Simulation time 328503878988 ps
CPU time 833.2 seconds
Started May 02 04:01:30 PM PDT 24
Finished May 02 04:15:24 PM PDT 24
Peak memory 202404 kb
Host smart-0522b314-dfb6-41ad-82e2-532745dc46b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936846749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.936846749
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3552965715
Short name T418
Test name
Test status
Simulation time 161738383481 ps
CPU time 189.79 seconds
Started May 02 04:01:25 PM PDT 24
Finished May 02 04:04:35 PM PDT 24
Peak memory 202308 kb
Host smart-da5bbd47-0d23-4260-afe1-24f89f9df7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552965715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3552965715
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.535749249
Short name T439
Test name
Test status
Simulation time 323088429956 ps
CPU time 108.62 seconds
Started May 02 04:01:26 PM PDT 24
Finished May 02 04:03:15 PM PDT 24
Peak memory 202312 kb
Host smart-08cd3664-4ca6-4323-99b9-a2175d777d2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=535749249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.535749249
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2506037026
Short name T199
Test name
Test status
Simulation time 324644931435 ps
CPU time 698.64 seconds
Started May 02 04:01:28 PM PDT 24
Finished May 02 04:13:07 PM PDT 24
Peak memory 202396 kb
Host smart-a1a1a45f-aae5-4da4-a5ac-ca6a3b2dc4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506037026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2506037026
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.605170802
Short name T396
Test name
Test status
Simulation time 332628341655 ps
CPU time 88.29 seconds
Started May 02 04:01:25 PM PDT 24
Finished May 02 04:02:54 PM PDT 24
Peak memory 202272 kb
Host smart-d8ff275b-d552-43da-9cb3-93e1ec8da816
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=605170802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.605170802
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4139230866
Short name T248
Test name
Test status
Simulation time 428784209051 ps
CPU time 933.17 seconds
Started May 02 04:01:26 PM PDT 24
Finished May 02 04:17:00 PM PDT 24
Peak memory 202316 kb
Host smart-9ce5cb46-45c4-47b0-96a7-d5596dc28cbc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139230866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4139230866
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.3012032456
Short name T740
Test name
Test status
Simulation time 598743113015 ps
CPU time 337.73 seconds
Started May 02 04:01:32 PM PDT 24
Finished May 02 04:07:10 PM PDT 24
Peak memory 202276 kb
Host smart-78b5441b-84e8-4aff-b324-5ff1c0e7bb7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012032456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.3012032456
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3925325522
Short name T782
Test name
Test status
Simulation time 97828112976 ps
CPU time 296.11 seconds
Started May 02 04:01:33 PM PDT 24
Finished May 02 04:06:30 PM PDT 24
Peak memory 202644 kb
Host smart-58d425ef-626a-42df-b6a7-f5afb03025c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925325522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3925325522
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2058521847
Short name T605
Test name
Test status
Simulation time 31307827102 ps
CPU time 35.32 seconds
Started May 02 04:01:29 PM PDT 24
Finished May 02 04:02:05 PM PDT 24
Peak memory 202108 kb
Host smart-6d18a689-8a46-4e7a-b1b6-80272558d210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058521847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2058521847
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1810354073
Short name T326
Test name
Test status
Simulation time 5194027946 ps
CPU time 13.29 seconds
Started May 02 04:01:29 PM PDT 24
Finished May 02 04:01:43 PM PDT 24
Peak memory 202120 kb
Host smart-23696694-4c85-49e0-871d-977c7060bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810354073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1810354073
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3629373948
Short name T636
Test name
Test status
Simulation time 5682212550 ps
CPU time 7.16 seconds
Started May 02 04:01:25 PM PDT 24
Finished May 02 04:01:33 PM PDT 24
Peak memory 202160 kb
Host smart-52bff62e-d6a4-47a7-99e2-7579c7ce0e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629373948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3629373948
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2527119604
Short name T449
Test name
Test status
Simulation time 72206800075 ps
CPU time 110.63 seconds
Started May 02 04:01:31 PM PDT 24
Finished May 02 04:03:23 PM PDT 24
Peak memory 210976 kb
Host smart-d91a4575-ba6a-4bf1-8119-1e9a4addbb1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527119604 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2527119604
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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