Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7548	1			T1	8		T2	62		T3	20
testmodes[AdcCtrlTestmodeNormal]	6017	1			T1	5		T2	49		T5	1
testmodes[AdcCtrlTestmodeLowpower]	6227	1			T2	35		T6	1		T8	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	4004	1			T1	4		T2	27		T3	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1896	1			T1	3		T2	21		T43	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1536	1			T2	13		T43	16		T55	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1924	1			T1	4		T2	21		T43	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2178	1			T1	1		T2	13		T10	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1582	1			T2	15		T6	1		T15	1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1492	1			T2	14		T43	17		T55	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1614	1			T2	14		T15	1		T43	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2867	1			T2	7		T8	2		T11	1