Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24317

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3708

1

T6

24

T10

1

T11

40

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22109

1

T1

13

T2

146

T3

20

auto[1]

5916

1

T6

24

T7

14

T8

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T240	1		-	-		-	-
values[0]	49	1			T184	19		T241	1		T25	4
values[1]	625	1			T6	12		T7	14		T10	1
values[2]	813	1			T12	1		T39	4		T151	20
values[3]	756	1			T12	1		T15	13		T53	9
values[4]	649	1			T12	1		T45	13		T46	15
values[5]	2827	1			T8	38		T11	10		T13	39
values[6]	739	1			T6	24		T11	30		T51	21
values[7]	697	1			T161	12		T164	1		T165	22
values[8]	705	1			T10	1		T51	6		T149	5
values[9]	1300	1			T5	1		T51	22		T149	29
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	863	1			T6	12		T7	14		T10	1
values[1]	849	1			T12	1		T15	13		T150	23
values[2]	673	1			T53	9		T151	12		T187	3
values[3]	2958	1			T8	38		T12	2		T13	39
values[4]	535	1			T11	40		T51	21		T169	11
values[5]	839	1			T6	24		T161	12		T165	20
values[6]	520	1			T164	1		T165	22		T153	2
values[7]	854	1			T10	1		T51	6		T149	19
values[8]	882	1			T5	1		T51	22		T149	15
values[9]	188	1			T242	24		T185	12		T167	10
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	7		T7	1		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T64	13		T161	12		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T15	6		T151	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T150	11		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T53	1		T151	1		T187	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T152	12		T154	1		T244	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1565	1			T8	38		T12	2		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T165	12		T154	1		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T169	11		T152	10		T166	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	19		T51	9		T187	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T161	12		T242	11		T167	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	13		T165	11		T41	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T165	12		T153	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T164	1		T153	1		T246	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T51	3		T149	5		T161	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T10	1		T149	14		T65	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	1		T51	13		T169	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T149	15		T173	15		T247	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T185	6		T167	10		T157	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T242	24		T248	1		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T6	5		T7	13		T39	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T64	10		T39	2		T152	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T15	7		T151	10		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T150	12		T191	4		T249	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T53	8		T151	11		T244	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T152	11		T244	4		T209	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T46	14		T52	16		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T165	4		T170	2		T250	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T152	10		T40	14		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	21		T51	12		T187	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T190	2		T217	12		T50	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T6	11		T165	9		T41	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T165	10		T243	15		T184	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T246	9		T251	7		T252	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T51	3		T173	1		T247	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T65	9		T185	14		T253	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T51	9		T187	17		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T173	5		T247	8		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T185	6		T254	1		T194	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T38	5		T255	5		T256	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T240	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T25	2		T257	11		T258	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T184	8		T241	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	7		T7	1		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T64	13		T161	12		T152	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T151	2		T170	5		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T12	1		T39	2		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	1		T15	6		T53	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T150	11		T163	1		T152	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	1		T45	13		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T165	12		T154	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1525	1			T8	38		T13	39		T14	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	1		T187	8		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T152	10		T166	13		T242	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T6	13		T11	18		T51	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T161	12		T165	12		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T164	1		T153	1		T41	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T51	3		T149	5		T161	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	1		T65	13		T224	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T5	1		T51	13		T169	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T149	29		T164	1		T169	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T25	2		T257	5		T258	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T184	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T6	5		T7	13		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T64	10		T152	9		T260	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T151	18		T170	13		T17	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T39	2		T191	4		T261	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	7		T53	8		T151	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	12		T152	11		T244	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	14		T40	14		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T165	4		T170	2		T209	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	903	1			T52	16		T158	8		T64	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	9		T187	6		T190	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T152	10		T217	10		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	11		T11	12		T51	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T165	10		T243	15		T184	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T41	6		T262	13		T251	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T51	3		T173	1		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T65	9		T185	14		T246	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T51	9		T187	17		T185	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T173	5		T247	8		T93	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	6		T7	14		T10	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T64	11		T161	1		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T15	12		T151	11		T243	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	1		T150	13		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T53	9		T151	12		T187	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T152	12		T154	1		T244	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T8	3		T12	2		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T165	5		T154	1		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T169	1		T152	11		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	23		T51	13		T187	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T161	1		T242	1		T167	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	12		T165	10		T41	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T165	11		T153	1		T243	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T164	1		T153	1		T246	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T51	4		T149	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	1		T149	1		T65	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T51	10		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T149	1		T173	6		T247	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T185	7		T167	1		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T242	1		T248	1		T38	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	6		T150	3		T263	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T64	12		T161	11		T152	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	1		T170	4		T157	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T150	10		T166	9		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T187	2		T166	2		T244	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T152	11		T244	13		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T8	35		T13	36		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T165	11		T155	2		T170	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T169	10		T152	9		T166	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	17		T51	8		T187	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T161	11		T242	10		T167	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	12		T165	10		T41	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T165	11		T56	8		T264	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T265	6		T251	3		T266	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T51	2		T149	4		T161	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T149	13		T65	12		T169	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T51	12		T169	12		T187	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T149	14		T173	14		T247	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T185	5		T167	9		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T242	23		T255	4		T256	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T240	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T25	4		T257	6		T258	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T184	12		T241	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	6		T7	14		T10	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T64	11		T161	1		T152	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T151	20		T170	14		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	1		T39	4		T154	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	1		T15	12		T53	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T150	13		T163	1		T152	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T45	1		T46	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T165	5		T154	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T8	3		T13	3		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	10		T187	7		T259	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T152	11		T166	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	12		T11	13		T51	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T161	1		T165	11		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T164	1		T153	1		T41	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T51	4		T149	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	1		T65	10		T224	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T5	1		T51	10		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T149	2		T164	1		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T257	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T184	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	6		T150	3		T263	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T64	12		T161	11		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T170	4		T157	2		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T156	13		T251	11		T249	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	1		T166	2		T244	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T150	10		T152	11		T244	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T45	12		T187	2		T40	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T165	11		T242	8		T170	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1187	1			T8	35		T13	36		T14	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T187	7		T155	2		T268	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T152	9		T166	12		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	12		T11	17		T51	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T161	11		T165	11		T56	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T41	5		T91	1		T262	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T51	2		T149	4		T161	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T65	12		T224	15		T185	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T51	12		T169	12		T187	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T149	27		T169	16		T224	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24484

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3541

1

T5

1

T6

12

T7

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21755

1

T1

13

T2

146

T3

20

auto[1]

6270

1

T6

36

T7

14

T8

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T269	1		-	-		-	-
values[0]	135	1			T167	10		T36	6		T270	15
values[1]	982	1			T51	6		T64	23		T152	23
values[2]	778	1			T64	2		T165	22		T154	1
values[3]	595	1			T5	1		T7	14		T10	1
values[4]	741	1			T11	30		T12	1		T15	13
values[5]	2846	1			T8	38		T12	1		T13	39
values[6]	561	1			T6	36		T12	1		T65	2
values[7]	535	1			T10	1		T11	10		T46	15
values[8]	861	1			T51	43		T65	22		T169	13
values[9]	1126	1			T53	9		T150	4		T161	3
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1275	1			T51	6		T64	25		T165	22
values[1]	674	1			T5	1		T152	23		T154	1
values[2]	759	1			T7	14		T10	1		T12	1
values[3]	2936	1			T8	38		T11	30		T13	39
values[4]	659	1			T12	2		T149	5		T151	11
values[5]	500	1			T6	24		T11	10		T46	15
values[6]	565	1			T6	12		T10	1		T51	21
values[7]	715	1			T51	22		T150	4		T169	13
values[8]	803	1			T53	9		T164	1		T169	11
values[9]	262	1			T161	3		T169	17		T187	31
minimum	18877	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T64	1		T165	12		T243	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T51	3		T64	13		T185	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T154	1		T245	2		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	1		T152	12		T244	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T15	6		T187	8		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T7	1		T10	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1666	1			T8	38		T11	18		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	13		T149	14		T161	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T149	5		T166	10		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	2		T151	1		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	13		T11	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T46	1		T39	2		T187	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	1		T65	13		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	7		T51	9		T149	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T169	13		T153	1		T271	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T51	13		T150	4		T166	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T53	1		T224	9		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T164	1		T169	11		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T161	3		T187	14		T192	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T169	17		T40	15		T18	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18746	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T64	1		T165	10		T243	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T51	3		T64	10		T185	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T59	11		T270	10		T272	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T152	11		T244	4		T184	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T15	7		T187	6		T185	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T7	13		T150	12		T273	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T11	12		T52	16		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T165	4		T152	10		T173	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T89	11		T273	16		T274	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T151	10		T165	9		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	11		T11	9		T152	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T46	14		T39	2		T173	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T65	9		T268	17		T275	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	5		T51	12		T65	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T191	5		T276	3		T277	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T51	9		T41	6		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T53	8		T243	2		T184	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T151	8		T243	15		T56	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T187	17		T192	16		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T40	14		T18	1		T49	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T167	10		T36	1		T270	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T278	1		T279	5		T280	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T243	1		T170	7		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T51	3		T64	13		T152	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T64	1		T165	12		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T244	14		T184	8		T247	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T187	8		T153	1		T166	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	1		T7	1		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	18		T15	6		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T45	13		T149	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1592	1			T8	38		T13	39		T14	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T12	1		T161	12		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	13		T152	10		T166	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T6	7		T12	1		T65	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	1		T11	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T46	1		T149	15		T39	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T65	13		T169	13		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T51	22		T151	1		T166	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T53	1		T161	3		T187	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T150	4		T164	1		T169	28
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T36	5		T270	14		T281	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T279	3		T282	6		T283	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T243	9		T170	2		T253	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T51	3		T64	10		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T64	1		T165	10		T185	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T244	4		T184	11		T247	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T187	6		T284	5		T250	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	13		T150	12		T273	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	12		T15	7		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T165	4		T152	10		T173	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T52	16		T158	8		T285	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T151	10		T165	9		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	11		T152	9		T286	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T6	5		T65	1		T246	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T11	9		T268	17		T275	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T46	14		T39	2		T173	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T65	9		T276	3		T277	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T51	21		T151	11		T41	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T53	8		T187	17		T243	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T151	8		T40	14		T243	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4