Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24291

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3734

1

T5

1

T6

24

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22137

1

T1

13

T2

146

T3

20

auto[1]

5888

1

T5

1

T6

36

T7

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T154	1		T38	6		T347	14
values[0]	73	1			T46	15		T156	21		T338	1
values[1]	765	1			T11	30		T149	15		T161	12
values[2]	634	1			T5	1		T11	10		T64	23
values[3]	844	1			T7	14		T12	1		T161	3
values[4]	600	1			T12	1		T150	4		T153	1
values[5]	653	1			T51	6		T149	5		T187	3
values[6]	678	1			T45	13		T53	9		T164	1
values[7]	760	1			T6	12		T10	1		T12	1
values[8]	640	1			T51	21		T64	2		T39	4
values[9]	3491	1			T6	24		T8	38		T10	1
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	857	1			T11	40		T46	15		T149	15
values[1]	807	1			T5	1		T64	23		T161	3
values[2]	650	1			T7	14		T12	1		T187	31
values[3]	765	1			T12	1		T149	5		T150	4
values[4]	684	1			T165	16		T152	23		T154	1
values[5]	635	1			T6	12		T10	1		T45	13
values[6]	2946	1			T8	38		T13	39		T14	10
values[7]	619	1			T12	1		T51	21		T64	2
values[8]	884	1			T6	24		T10	1		T15	13
values[9]	260	1			T151	21		T243	16		T168	15
minimum	18918	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	1		T46	1		T149	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	18		T65	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T169	13		T173	8		T190	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T5	1		T64	13		T161	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	1		T263	5		T157	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T187	14		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T149	5		T150	4		T263	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T187	3		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T154	1		T184	1		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T165	12		T152	12		T173	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	7		T45	13		T150	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T10	1		T51	3		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T8	38		T13	39		T14	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	13		T39	5		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T64	1		T40	15		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	1		T51	9		T169	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	1		T161	12		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T6	13		T15	6		T149	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T19	2		T261	10		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T151	2		T243	1		T168	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18742	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T303	7		T340	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	9		T46	14		T151	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	12		T65	1		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T173	7		T190	2		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T64	10		T165	10		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	13		T260	17		T253	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T187	17		T37	7		T265	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T185	6		T209	10		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T244	12		T217	12		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T184	13		T17	4		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T165	4		T152	11		T173	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	5		T150	12		T41	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T51	3		T53	8		T152	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	997	1			T52	16		T158	8		T65	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T51	9		T39	2		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T64	1		T40	14		T260	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T51	12		T243	9		T246	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T243	2		T184	11		T56	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T6	11		T15	7		T176	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T261	7		T38	5		T335	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T151	19		T243	15		T273	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T15	1		T39	5		T41	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T303	6		T340	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T38	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T154	1		T347	14		T95	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T46	1		T156	21		T338	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T294	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T149	15		T161	12		T151	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T11	18		T39	1		T169	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	1		T169	13		T173	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T64	13		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T263	5		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T161	3		T187	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T150	4		T155	12		T185	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T153	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T149	5		T154	1		T263	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T51	3		T187	3		T165	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T45	13		T166	10		T41	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T53	1		T164	1		T173	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	7		T150	11		T65	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	1		T12	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T64	1		T166	3		T40	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T51	9		T39	2		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1730	1			T8	38		T10	1		T13	39
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	442	1			T6	13		T15	6		T149	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T38	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T46	14		T229	10		T348	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T151	10		T217	11		T295	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	12		T39	1		T187	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	9		T173	7		T190	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T64	10		T65	1		T165	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	13		T260	17		T253	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T187	17		T176	7		T177	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T185	6		T48	1		T286	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T244	12		T217	12		T253	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T184	13		T170	2		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	3		T165	4		T152	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T41	6		T190	9		T284	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T53	8		T173	1		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	5		T150	12		T65	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T51	9		T152	10		T173	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T64	1		T40	14		T177	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T51	12		T39	2		T243	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1019	1			T52	16		T158	8		T285	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T6	11		T15	7		T151	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	10		T46	15		T149	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T11	13		T65	2		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T169	1		T173	8		T190	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	1		T64	11		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	14		T263	1		T157	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T187	18		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T149	1		T150	1		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T12	1		T187	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T154	1		T184	14		T17	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T165	5		T152	12		T173	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	6		T45	1		T150	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	1		T51	4		T53	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T8	3		T13	3		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T51	10		T39	6		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T64	2		T40	16		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T51	13		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	1		T161	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	12		T15	12		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T19	2		T261	8		T38	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T151	21		T243	16		T168	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18880	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T303	7		T340	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T149	14		T161	11		T167	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	17		T169	10		T187	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T169	12		T173	7		T349	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T64	12		T161	2		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T263	4		T157	2		T260	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T187	13		T37	7		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T149	4		T150	3		T263	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T187	2		T244	8		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T17	3		T275	7		T350	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T165	11		T152	11		T242	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	6		T45	12		T150	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T51	2		T152	9		T166	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T8	35		T13	36		T14	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T51	12		T39	1		T242	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T40	13		T260	9		T92	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T51	8		T169	16		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T161	11		T242	23		T184	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	12		T15	1		T149	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T261	9		T351	10		T314	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T168	14		T273	13		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T352	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T303	6		T340	7		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T38	6		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T154	1		T347	1		T95	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T46	15		T156	1		T338	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T294	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T149	1		T161	1		T151	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T11	13		T39	2		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	10		T169	1		T173	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	1		T64	11		T65	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	14		T263	1		T248	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T12	1		T161	1		T187	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T150	1		T155	1		T185	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T153	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T149	1		T154	1		T263	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T51	4		T187	1		T165	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T45	1		T166	1		T41	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	9		T164	1		T173	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	6		T150	13		T65	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	1		T12	1		T51	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T64	2		T166	1		T40	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	13		T39	4		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T8	3		T10	1		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	385	1			T6	12		T15	12		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T347	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T156	20		T229	9		T348	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T149	14		T161	11		T167	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	17		T169	10		T187	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T169	12		T173	7		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T64	12		T165	11		T152	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T263	4		T260	9		T253	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T161	2		T187	13		T155	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T150	3		T155	11		T185	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T244	8		T167	9		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T149	4		T263	18		T170	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T51	2		T187	2		T165	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T45	12		T166	9		T41	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T244	13		T353	7		T316	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	6		T150	10		T65	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T51	12		T39	1		T152	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T166	2		T40	13		T92	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T51	8		T271	17		T198	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1378	1			T8	35		T13	36		T14	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	357	1			T6	12		T15	1		T149	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17