Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24729

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3296

1

T7

14

T12

2

T45

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21987

1

T1

13

T2

144

T3

20

auto[1]

6038

1

T2

2

T6

24

T7

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	670	1			T2	2		T43	1		T55	1
values[0]	33	1			T154	1		T317	31		T315	1
values[1]	750	1			T11	10		T45	13		T39	6
values[2]	2833	1			T8	38		T12	1		T13	39
values[3]	581	1			T5	1		T6	12		T51	28
values[4]	617	1			T10	1		T15	13		T161	12
values[5]	540	1			T6	24		T7	14		T12	2
values[6]	856	1			T161	3		T163	1		T242	24
values[7]	808	1			T64	25		T164	1		T165	36
values[8]	811	1			T11	30		T53	9		T161	12
values[9]	1067	1			T10	1		T51	21		T149	14
minimum	18459	1			T1	13		T2	144		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	769	1			T11	10		T45	13		T46	15
values[1]	2874	1			T6	12		T8	38		T12	1
values[2]	546	1			T5	1		T51	28		T150	23
values[3]	552	1			T10	1		T12	1		T15	13
values[4]	685	1			T6	24		T7	14		T12	1
values[5]	742	1			T164	1		T163	1		T165	20
values[6]	855	1			T64	23		T161	12		T165	16
values[7]	763	1			T11	30		T53	9		T64	2
values[8]	1056	1			T10	1		T51	21		T149	14
values[9]	122	1			T151	11		T175	1		T296	5
minimum	19061	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T11	1		T149	15		T39	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T45	13		T46	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1654	1			T6	7		T8	38		T13	39
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	1		T150	4		T65	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T150	11		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T51	16		T151	1		T18	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	1		T15	6		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	1		T187	3		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	13		T12	1		T263	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T7	1		T161	3		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T163	1		T152	10		T242	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T164	1		T165	11		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T161	12		T165	12		T166	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T64	13		T91	3		T93	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	18		T53	1		T64	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T187	14		T152	10		T224	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	1		T149	14		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T51	9		T164	1		T244	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T151	1		T296	1		T307	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T175	1		T179	1		T314	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18812	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T242	9		T155	3		T288	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	9		T39	2		T187	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T46	14		T39	1		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T6	5		T52	16		T158	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T65	1		T173	7		T265	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T150	12		T303	6		T199	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T51	12		T151	8		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	7		T41	6		T295	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T243	9		T190	2		T253	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	11		T36	5		T191	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	13		T152	11		T176	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T152	9		T185	6		T246	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T165	9		T17	4		T37	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T165	4		T40	14		T217	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T64	10		T93	10		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T11	12		T53	8		T64	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T187	17		T152	10		T173	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T173	1		T170	2		T209	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T51	12		T244	12		T190	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T151	10		T296	4		T307	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T314	9		T225	3		T354	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T15	1		T39	5		T41	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T288	10		T336	3		T299	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	453	1			T2	2		T43	1		T55	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T164	1		T273	14		T296	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T154	1		T317	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T315	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T11	1		T39	2		T165	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T45	13		T39	1		T169	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1602	1			T8	38		T13	39		T14	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T46	1		T150	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T6	7		T150	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T51	16		T18	5		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	1		T15	6		T161	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T151	1		T187	3		T190	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T6	13		T12	1		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	1		T12	1		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T163	1		T242	24		T263	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T161	3		T167	8		T17	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T64	1		T165	12		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T64	13		T164	1		T165	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	18		T53	1		T161	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T187	14		T152	10		T173	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	1		T149	14		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T51	9		T224	9		T244	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18328	1			T1	13		T2	144		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T151	10		T296	4		T314	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T273	16		T296	16		T335	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T317	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	9		T39	2		T165	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T39	1		T151	11		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T52	16		T158	8		T65	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T46	14		T65	1		T173	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	5		T150	12		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T51	12		T18	1		T59	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T15	7		T41	6		T337	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T151	8		T190	2		T253	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T6	11		T295	9		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T7	13		T152	11		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T185	6		T246	9		T260	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T17	4		T192	9		T249	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T64	1		T165	4		T152	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T64	10		T165	9		T37	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	12		T53	8		T262	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T187	17		T152	10		T173	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T173	1		T243	2		T170	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T51	12		T244	12		T185	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	10		T149	1		T39	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T45	1		T46	15		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T6	6		T8	3		T13	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T150	1		T65	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T150	13		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T51	14		T151	9		T18	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	1		T15	12		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T187	1		T243	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	12		T12	1		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T7	14		T161	1		T152	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T163	1		T152	10		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T164	1		T165	10		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T161	1		T165	5		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T64	11		T91	2		T93	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	13		T53	9		T64	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T187	18		T152	11		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T10	1		T149	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T51	13		T164	1		T244	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T151	11		T296	5		T307	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T175	1		T179	1		T314	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18941	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T242	1		T155	1		T288	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T149	14		T187	7		T165	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	12		T169	10		T170	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T6	6		T8	35		T13	36
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T150	3		T173	7		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T150	10		T242	10		T167	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T51	14		T176	1		T326	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T15	1		T161	11		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T187	2		T168	14		T253	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	12		T263	12		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T161	2		T152	11		T276	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T152	9		T242	23		T185	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T165	10		T155	11		T167	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T161	11		T165	11		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T64	12		T91	1		T262	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	17		T169	16		T267	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T187	13		T152	9		T224	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T149	13		T170	6		T251	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T51	8		T244	8		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T307	1		T320	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T225	10		T354	9		T321	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T184	7		T268	13		T289	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T242	8		T155	2		T288	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	483	1			T2	2		T43	1		T55	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T164	1		T273	17		T296	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T154	1		T317	18		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T315	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	10		T39	4		T165	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T45	1		T39	2		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T8	3		T13	3		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T46	15		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T6	6		T150	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T51	14		T18	6		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	1		T15	12		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T151	9		T187	1		T190	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	12		T12	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	14		T12	1		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T163	1		T242	1		T263	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T161	1		T167	1		T17	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T64	2		T165	5		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T64	11		T164	1		T165	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T11	13		T53	9		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T187	18		T152	11		T173	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T10	1		T149	1		T173	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T51	13		T224	1		T244	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18459	1			T1	13		T2	144		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T314	4		T316	11		T340	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T273	13		T22	1		T225	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T317	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T165	11		T244	13		T263	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	12		T169	10		T242	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T8	35		T13	36		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T150	3		T173	7		T265	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	6		T150	10		T166	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T51	14		T289	4		T349	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T15	1		T161	11		T169	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T187	2		T168	14		T253	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T6	12		T39	1		T167	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T152	11		T276	8		T350	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T242	23		T263	12		T185	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T161	2		T167	7		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T165	11		T152	9		T166	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T64	12		T165	10		T155	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	17		T161	11		T169	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T187	13		T152	9		T173	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T149	13		T170	6		T253	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T51	8		T224	8		T244	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17