Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24208

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3817

1

T5

1

T6

24

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22177

1

T1

13

T2

146

T3

20

auto[1]

5848

1

T5

1

T6

36

T7

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	166	1			T10	1		T154	1		T184	19
values[0]	27	1			T156	21		T355	1		T180	1
values[1]	771	1			T11	30		T46	15		T149	15
values[2]	684	1			T5	1		T11	10		T64	23
values[3]	806	1			T7	14		T12	1		T161	3
values[4]	620	1			T12	1		T149	5		T150	4
values[5]	626	1			T187	3		T165	16		T173	2
values[6]	740	1			T45	13		T51	6		T53	9
values[7]	693	1			T6	12		T10	1		T12	1
values[8]	601	1			T51	21		T64	2		T39	7
values[9]	3427	1			T6	24		T8	38		T13	39
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	602	1			T11	40		T149	15		T161	12
values[1]	771	1			T5	1		T64	23		T161	3
values[2]	732	1			T7	14		T12	1		T187	31
values[3]	694	1			T12	1		T149	5		T187	3
values[4]	664	1			T45	13		T150	4		T165	16
values[5]	712	1			T6	12		T10	1		T51	6
values[6]	2857	1			T8	38		T12	1		T13	39
values[7]	644	1			T51	21		T64	2		T169	17
values[8]	993	1			T6	24		T10	1		T15	13
values[9]	180	1			T168	15		T19	2		T273	30
minimum	19176	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	1		T149	15		T161	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	18		T65	1		T39	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T173	8		T190	1		T18	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T5	1		T64	13		T161	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T7	1		T263	5		T185	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T187	14		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T149	5		T155	12		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T187	3		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T45	13		T150	4		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T165	12		T173	1		T242	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	7		T150	11		T166	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T10	1		T51	3		T53	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T8	38		T13	39		T14	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	1		T51	13		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T64	1		T40	15		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	9		T169	17		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	1		T161	12		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T6	13		T15	6		T149	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T19	2		T38	1		T335	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T168	15		T273	14		T20	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18804	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T187	8		T217	8		T247	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	9		T151	10		T217	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	12		T65	1		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T173	7		T190	2		T18	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T64	10		T165	10		T152	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	13		T185	6		T253	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T187	17		T260	17		T37	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T209	10		T48	1		T253	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T244	12		T217	12		T286	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T184	13		T170	2		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T165	4		T173	1		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	5		T150	12		T41	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	3		T53	8		T152	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	970	1			T52	16		T158	8		T65	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T51	9		T49	4		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T64	1		T40	14		T324	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T51	12		T243	9		T36	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T243	2		T56	7		T260	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T6	11		T15	7		T151	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T38	5		T335	10		T351	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T273	16		T20	1		T288	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	1		T46	14		T39	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T187	6		T217	10		T247	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T10	1		T38	1		T354	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T154	1		T184	8		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T156	21		T355	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T180	1		T294	3		T356	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T46	1		T149	15		T161	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	18		T39	1		T187	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	1		T173	8		T190	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	1		T64	13		T65	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	1		T263	5		T157	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T161	3		T187	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T149	5		T150	4		T155	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T153	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T263	19		T184	1		T170	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T187	3		T165	12		T173	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T45	13		T166	10		T41	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	3		T53	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T6	7		T150	11		T65	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	1		T12	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T64	1		T39	5		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T51	9		T163	1		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1719	1			T8	38		T13	39		T14	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	411	1			T6	13		T15	6		T149	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T38	5		T354	8		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T184	11		T276	3		T20	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T46	14		T151	10		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	12		T39	1		T187	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	9		T173	7		T190	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T64	10		T65	1		T165	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	13		T253	19		T268	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T187	17		T260	17		T176	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T185	6		T48	1		T253	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T244	12		T217	12		T286	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T184	13		T170	2		T209	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T165	4		T173	1		T17	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T41	6		T190	9		T247	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T51	3		T53	8		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	5		T150	12		T65	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T51	9		T152	10		T209	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T64	1		T39	2		T177	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T51	12		T243	9		T207	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1009	1			T52	16		T158	8		T285	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	11		T15	7		T151	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	10		T149	1		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	13		T65	2		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T173	8		T190	3		T18	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T5	1		T64	11		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	14		T263	1		T185	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T12	1		T187	18		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T149	1		T155	1		T209	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T12	1		T187	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T45	1		T150	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T165	5		T173	2		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T6	6		T150	13		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T51	4		T53	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T8	3		T13	3		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T12	1		T51	10		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T64	2		T40	16		T29	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T51	13		T169	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T10	1		T161	1		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T6	12		T15	12		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T19	2		T38	6		T335	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T168	1		T273	17		T20	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18954	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T187	7		T217	11		T247	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T149	14		T161	11		T217	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	17		T165	10		T224	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T173	7		T192	1		T343	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T64	12		T161	2		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T263	4		T185	5		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T187	13		T260	9		T37	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T149	4		T155	11		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T187	2		T244	8		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	12		T150	3		T263	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T165	11		T242	10		T157	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	6		T150	10		T166	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T51	2		T152	20		T166	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T8	35		T13	36		T14	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T51	12		T242	8		T49	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T40	13		T92	9		T273	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T51	8		T169	16		T91	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	11		T242	23		T56	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	12		T15	1		T149	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T351	10		T328	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T168	14		T273	13		T20	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T169	10		T167	7		T156	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T187	7		T217	7		T247	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T10	1		T38	6		T354	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T154	1		T184	12		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T156	1		T355	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T180	1		T294	1		T356	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T46	15		T149	1		T161	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	13		T39	2		T187	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	10		T173	8		T190	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T5	1		T64	11		T65	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T7	14		T263	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T12	1		T161	1		T187	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T149	1		T150	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T12	1		T153	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T263	1		T184	14		T170	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T187	1		T165	5		T173	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T45	1		T166	1		T41	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T51	4		T53	9		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T6	6		T150	13		T65	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	1		T12	1		T51	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T64	2		T39	6		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T51	13		T163	1		T245	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T8	3		T13	3		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T6	12		T15	12		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T354	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T184	7		T276	8		T20	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T156	20		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T294	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T149	14		T161	11		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	17		T187	7		T165	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T173	7		T343	14		T225	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T64	12		T169	12		T165	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T263	4		T157	2		T253	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T161	2		T187	13		T155	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T149	4		T150	3		T155	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T244	8		T167	9		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T263	18		T170	6		T350	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T187	2		T165	11		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	12		T166	9		T41	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	2		T152	11		T166	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	6		T150	10		T65	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T51	12		T152	9		T224	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T39	1		T92	9		T177	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T51	8		T271	17		T357	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T8	35		T13	36		T14	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T6	12		T15	1		T149	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17