Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24477

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3548

1

T5

1

T6

12

T7

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21772

1

T1

13

T2

146

T3

20

auto[1]

6253

1

T6

36

T7

14

T8

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T53	9		T161	3		T164	1
values[0]	123	1			T167	10		T36	6		T270	15
values[1]	934	1			T51	6		T64	23		T243	10
values[2]	805	1			T5	1		T64	2		T165	22
values[3]	638	1			T10	1		T150	23		T187	14
values[4]	669	1			T7	14		T11	30		T12	1
values[5]	2920	1			T8	38		T12	1		T13	39
values[6]	534	1			T6	24		T12	1		T65	2
values[7]	569	1			T6	12		T10	1		T11	10
values[8]	843	1			T51	43		T65	22		T169	13
values[9]	877	1			T150	4		T187	31		T40	29
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1025	1			T64	2		T165	22		T170	9
values[1]	661	1			T5	1		T152	23		T154	1
values[2]	705	1			T7	14		T10	1		T12	1
values[3]	2952	1			T8	38		T11	30		T13	39
values[4]	614	1			T12	2		T149	5		T151	11
values[5]	539	1			T6	24		T11	10		T46	15
values[6]	554	1			T6	12		T10	1		T51	21
values[7]	792	1			T51	22		T150	4		T169	13
values[8]	883	1			T53	9		T164	1		T169	11
values[9]	142	1			T161	3		T169	17		T49	10
minimum	19158	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T64	1		T165	12		T170	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T217	20		T157	10		T247	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T154	1		T245	2		T263	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T152	12		T244	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T15	6		T187	8		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	1		T10	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T8	38		T11	18		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T45	13		T149	14		T161	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T149	5		T166	10		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	2		T151	1		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T6	13		T11	1		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T46	1		T65	1		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	1		T65	13		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	7		T51	9		T149	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T169	13		T153	1		T184	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T51	13		T150	4		T166	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T53	1		T187	14		T224	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T164	1		T169	11		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T161	3		T192	3		T358	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T169	17		T49	6		T38	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18782	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T51	3		T64	13		T185	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T64	1		T165	10		T170	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T217	22		T247	8		T260	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T185	6		T270	10		T272	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T152	11		T244	4		T184	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	7		T187	6		T284	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	13		T150	12		T273	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T11	12		T52	16		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T165	4		T152	10		T173	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T89	11		T274	10		T193	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T151	10		T165	9		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T6	11		T11	9		T152	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T46	14		T65	1		T39	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T65	9		T268	17		T275	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	5		T51	12		T151	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T184	13		T191	5		T276	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	9		T41	6		T244	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T53	8		T187	17		T243	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T151	8		T40	14		T243	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T192	16		T359	6		T360	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T49	4		T38	5		T229	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T15	1		T39	5		T41	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T51	3		T64	10		T185	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T53	1		T161	3		T287	15
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T164	1		T169	28		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T167	10		T36	1		T270	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T278	1		T279	5		T280	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T243	1		T170	7		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T51	3		T64	13		T185	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T64	1		T165	12		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T152	12		T244	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T187	8		T153	1		T166	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	1		T150	11		T224	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	18		T15	6		T39	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T12	1		T45	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T8	38		T13	39		T14	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T161	12		T165	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T6	13		T152	10		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T12	1		T65	1		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	1		T11	1		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	7		T46	1		T149	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T65	13		T169	13		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T51	22		T166	13		T41	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T187	14		T224	9		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T150	4		T40	15		T243	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T53	8		T324	10		T192	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T151	8		T49	4		T38	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T36	5		T270	14		T361	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T279	3		T283	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T243	9		T170	2		T253	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T51	3		T64	10		T185	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T64	1		T165	10		T185	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T152	11		T244	4		T184	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T187	6		T284	5		T262	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T150	12		T273	14		T202	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	12		T15	7		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T7	13		T165	4		T173	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T52	16		T158	8		T285	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T165	9		T152	10		T217	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T6	11		T152	9		T286	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T65	1		T151	10		T190	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	9		T268	17		T275	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T6	5		T46	14		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T65	9		T276	3		T277	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	21		T41	6		T260	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T187	17		T243	2		T184	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	14		T243	15		T244	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T64	2		T165	11		T170	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T217	24		T157	1		T247	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T154	1		T245	2		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	1		T152	12		T244	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T15	12		T187	7		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	14		T10	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T8	3		T11	13		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T45	1		T149	1		T161	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T149	1		T166	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T12	2		T151	11		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T6	12		T11	10		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T46	15		T65	2		T39	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	1		T65	10		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	6		T51	13		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T169	1		T153	1		T184	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T51	10		T150	1		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T53	9		T187	18		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T164	1		T169	1		T151	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T161	1		T192	18		T358	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T169	1		T49	7		T38	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18948	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T51	4		T64	11		T185	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T165	11		T170	6		T167	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T217	18		T157	9		T247	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T263	18		T185	5		T287	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T152	11		T244	13		T184	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	1		T187	7		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T150	10		T224	15		T156	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1307	1			T8	35		T11	17		T13	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T45	12		T149	13		T161	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T149	4		T166	9		T263	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T165	10		T242	23		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	12		T152	9		T155	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T187	2		T173	14		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T65	12		T156	13		T91	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T6	6		T51	8		T149	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T169	12		T271	17		T276	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T51	12		T150	3		T166	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T187	13		T224	8		T287	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T169	10		T40	13		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T161	2		T192	1		T358	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T169	16		T49	3		T229	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T253	15		T176	1		T289	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T51	2		T64	12		T185	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T53	9		T161	1		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T164	1		T169	2		T151	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T167	1		T36	6		T270	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T278	1		T279	4		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T243	10		T170	3		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T51	4		T64	11		T185	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T64	2		T165	11		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T5	1		T152	12		T244	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T187	7		T153	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	1		T150	13		T224	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	13		T15	12		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	14		T12	1		T45	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T8	3		T13	3		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	1		T161	1		T165	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T6	12		T152	10		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T12	1		T65	2		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	1		T11	10		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	6		T46	15		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T65	10		T169	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T51	23		T166	1		T41	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T187	18		T224	1		T259	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T150	1		T40	16		T243	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T161	2		T287	14		T192	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T169	26		T49	3		T362	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T167	9		T290	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T279	4		T280	10		T283	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T170	6		T267	7		T253	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T51	2		T64	12		T185	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T165	11		T263	18		T185	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T152	11		T244	13		T184	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T187	7		T166	2		T92	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	10		T224	15		T156	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	17		T15	1		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T45	12		T149	13		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T8	35		T13	36		T14	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T161	11		T165	10		T152	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T6	12		T152	9		T155	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T187	2		T157	4		T309	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T156	13		T91	1		T268	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	6		T149	14		T173	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T65	12		T169	12		T271	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T51	20		T166	12		T41	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T187	13		T224	8		T288	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T150	3		T40	13		T244	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17