Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24115

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3910

1

T5

1

T6

12

T7

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21711

1

T1

13

T2

146

T3

20

auto[1]

6314

1

T8

38

T11

30

T12

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	278	1			T169	17		T170	18		T157	5
values[0]	70	1			T187	31		T338	1		T305	23
values[1]	851	1			T10	1		T149	29		T64	23
values[2]	715	1			T6	24		T7	14		T51	21
values[3]	686	1			T51	22		T161	12		T173	20
values[4]	2919	1			T8	38		T13	39		T14	10
values[5]	521	1			T5	1		T11	30		T161	3
values[6]	693	1			T6	12		T15	13		T46	15
values[7]	778	1			T12	1		T53	9		T64	2
values[8]	576	1			T11	10		T12	1		T45	13
values[9]	1074	1			T10	1		T12	1		T150	4
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	894	1			T6	24		T10	1		T149	29
values[1]	708	1			T7	14		T51	43		T161	12
values[2]	647	1			T184	19		T185	29		T156	21
values[3]	2813	1			T8	38		T11	30		T13	39
values[4]	667	1			T5	1		T15	13		T65	2
values[5]	679	1			T6	12		T46	15		T51	6
values[6]	713	1			T12	2		T64	2		T187	3
values[7]	646	1			T11	10		T45	13		T150	4
values[8]	974	1			T10	1		T12	1		T39	7
values[9]	163	1			T56	16		T260	19		T176	3
minimum	19121	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T6	13		T149	29		T65	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T10	1		T161	12		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T51	13		T156	14		T253	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	1		T51	9		T161	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T247	12		T273	17		T318	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T184	8		T185	15		T156	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T8	38		T11	18		T13	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T149	5		T161	3		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T65	1		T245	1		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T5	1		T15	6		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T46	1		T51	3		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	7		T53	1		T150	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T40	15		T59	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T64	1		T187	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	1		T150	4		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	13		T151	1		T166	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T39	2		T151	1		T170	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T10	1		T12	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T260	10		T265	12		T264	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T56	9		T176	2		T264	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18781	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T64	13		T245	1		T246	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T6	11		T65	9		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T217	12		T286	11		T37	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T51	9		T253	29		T284	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	13		T51	12		T173	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T247	8		T273	14		T318	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T184	11		T185	14		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	962	1			T11	12		T52	16		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T151	8		T165	9		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T65	1		T243	9		T261	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T15	7		T243	2		T247	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T46	14		T51	3		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T6	5		T53	8		T150	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T40	14		T59	11		T262	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T64	1		T165	10		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	9		T152	9		T324	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T151	11		T41	6		T173	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T39	2		T151	10		T170	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T187	6		T170	2		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T260	9		T265	13		T264	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T56	7		T176	1		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T15	1		T39	5		T187	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T64	10		T246	9		T261	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T170	5		T157	5		T265	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T169	17		T174	1		T192	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T187	14		T338	1		T325	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T305	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T149	29		T242	11		T155	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	1		T64	13		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	13		T65	13		T156	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	1		T51	9		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T51	13		T253	2		T273	31
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T161	12		T173	15		T184	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T8	38		T13	39		T14	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T149	5		T151	1		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	18		T65	1		T166	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	1		T161	3		T173	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T46	1		T51	3		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T6	7		T15	6		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	15		T59	1		T262	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T12	1		T53	1		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T11	1		T12	1		T263	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	13		T166	3		T173	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T150	4		T39	2		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T10	1		T12	1		T39	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T170	13		T265	13		T345	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T192	7		T363	11		T364	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T187	17		T325	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T305	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T217	10		T209	11		T253	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T64	10		T217	12		T246	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	11		T65	9		T253	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	13		T51	12		T244	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T51	9		T253	10		T273	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T173	5		T184	11		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T52	16		T158	8		T285	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T151	8		T165	9		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T11	12		T65	1		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T173	7		T243	2		T326	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T46	14		T51	3		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T6	5		T15	7		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T40	14		T59	11		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T53	8		T64	1		T165	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T11	9		T254	1		T288	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T173	1		T260	17		T262	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T39	2		T151	10		T152	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T151	11		T187	6		T41	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T6	12		T149	2		T65	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	1		T161	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T51	10		T156	1		T253	31
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T7	14		T51	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T247	9		T273	15		T318	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T184	12		T185	15		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T8	3		T11	13		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T149	1		T161	1		T151	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T65	2		T245	1		T243	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T15	12		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T46	15		T51	4		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	6		T53	9		T150	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T40	16		T59	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T64	2		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	10		T150	1		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T45	1		T151	12		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T39	4		T151	11		T170	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T10	1		T12	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T260	10		T265	14		T264	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T56	8		T176	2		T264	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18916	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T64	11		T245	1		T246	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	12		T149	27		T65	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T161	11		T167	7		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T51	12		T156	13		T253	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T51	8		T161	11		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T247	11		T273	16		T318	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T184	7		T185	14		T156	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T8	35		T11	17		T13	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T149	4		T161	2		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T242	23		T287	14		T289	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T15	1		T224	15		T263	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T51	2		T165	11		T185	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	6		T150	10		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	13		T262	12		T271	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T187	2		T165	11		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T150	3		T152	9		T263	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T45	12		T166	2		T41	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T170	4		T157	4		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T39	1		T169	26		T187	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T260	9		T265	11		T264	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T56	8		T176	1		T264	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T187	13		T226	9		T325	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T64	12		T261	9		T303	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T170	14		T157	1		T265	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T169	1		T174	1		T192	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T187	18		T338	1		T325	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T305	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T149	2		T242	1		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	1		T64	11		T164	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T6	12		T65	10		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	14		T51	13		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T51	10		T253	11		T273	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T161	1		T173	6		T184	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T8	3		T13	3		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T149	1		T151	9		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	13		T65	2		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	1		T161	1		T173	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	15		T51	4		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	6		T15	12		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T40	16		T59	12		T262	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T12	1		T53	9		T64	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	10		T12	1		T263	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T45	1		T166	1		T173	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T150	1		T39	4		T151	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T10	1		T12	1		T39	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T170	4		T157	4		T265	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T169	16		T192	1		T256	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T187	13		T325	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T305	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T149	27		T242	10		T155	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T64	12		T167	7		T217	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T6	12		T65	12		T156	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T51	8		T161	11		T169	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T51	12		T253	1		T273	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T161	11		T173	14		T184	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T8	35		T13	36		T14	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	4		T165	10		T152	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	17		T166	9		T242	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T161	2		T173	7		T263	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T51	2		T165	11		T185	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	6		T15	1		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T40	13		T262	12		T271	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T187	2		T165	11		T152	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T263	12		T254	1		T288	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T45	12		T166	2		T167	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T150	3		T152	9		T167	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T39	1		T169	10		T187	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17