Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24410

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3615

1

T5

1

T6

24

T11

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21669

1

T1

13

T2

146

T3

20

auto[1]

6356

1

T6

24

T7

14

T8

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	375	1			T51	22		T39	4		T209	11
values[0]	101	1			T152	19		T340	17		T341	5
values[1]	675	1			T10	1		T12	1		T15	13
values[2]	2990	1			T5	1		T8	38		T13	39
values[3]	530	1			T53	9		T151	11		T152	23
values[4]	582	1			T149	15		T169	30		T165	20
values[5]	571	1			T12	1		T164	1		T163	1
values[6]	769	1			T6	24		T7	14		T10	1
values[7]	857	1			T12	1		T64	2		T161	15
values[8]	718	1			T46	15		T39	2		T164	1
values[9]	993	1			T6	12		T45	13		T51	21
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	829	1			T10	1		T51	6		T149	14
values[1]	2944	1			T5	1		T8	38		T13	39
values[2]	467	1			T151	11		T167	15		T217	23
values[3]	555	1			T149	15		T169	30		T163	1
values[4]	661	1			T11	10		T12	1		T164	1
values[5]	805	1			T6	24		T7	14		T10	1
values[6]	812	1			T12	1		T64	2		T161	15
values[7]	731	1			T46	15		T65	22		T165	38
values[8]	1061	1			T6	12		T45	13		T51	43
values[9]	118	1			T39	4		T170	18		T209	11
minimum	19042	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	1		T51	3		T64	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T149	14		T154	1		T263	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T8	38		T13	39		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	1		T53	1		T173	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T151	1		T167	8		T217	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T167	7		T342	1		T324	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T245	1		T251	1		T309	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T149	15		T169	30		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T12	1		T164	1		T242	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	1		T153	1		T224	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T7	1		T10	1		T11	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T6	13		T187	3		T166	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T64	1		T161	15		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T151	1		T187	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T46	1		T165	12		T41	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T65	13		T165	12		T166	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	312	1			T6	7		T45	13		T51	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T51	13		T149	5		T169	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T39	2		T170	5		T176	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T209	1		T330	1		T294	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18794	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T152	10		T259	1		T174	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T51	3		T64	10		T260	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T262	13		T265	13		T276	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T52	16		T158	8		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T53	8		T173	5		T247	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T151	10		T217	11		T247	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T324	10		T191	5		T192	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T343	12		T330	15		T365	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T165	9		T243	9		T244	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T170	2		T18	1		T50	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T11	9		T93	13		T310	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	13		T11	12		T187	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T6	11		T49	4		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T64	1		T39	1		T244	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T151	11		T187	6		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T46	14		T165	4		T41	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T65	9		T165	10		T243	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T6	5		T51	12		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T51	9		T151	8		T40	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T39	2		T170	13		T176	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T209	10		T330	1		T256	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T15	8		T39	5		T41	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T152	9		T314	10		T341	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T39	2		T48	5		T253	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	13		T209	1		T332	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T340	7		T118	12		T290	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T152	10		T341	1		T366	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	1		T12	1		T15	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T154	1		T259	1		T263	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T8	38		T13	39		T14	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	1		T149	14		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T151	1		T152	12		T173	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T53	1		T173	15		T167	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T217	12		T31	1		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T149	15		T169	30		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	1		T164	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T163	1		T153	1		T224	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T7	1		T10	1		T11	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	13		T11	1		T166	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T64	1		T161	15		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	1		T187	11		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T46	1		T39	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T151	1		T165	12		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T6	7		T45	13		T51	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T149	5		T65	13		T169	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T39	2		T48	1		T253	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T51	9		T209	10		T303	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T340	10		T118	11		T290	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T152	9		T341	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T15	7		T51	3		T64	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T262	13		T265	13		T268	28
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T52	16		T158	8		T285	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T247	7		T324	16		T276	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T151	10		T152	11		T173	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T53	8		T173	5		T59	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T217	11		T274	10		T335	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T165	9		T286	11		T337	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T18	1		T50	1		T36	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T243	9		T244	12		T93	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	13		T11	12		T243	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	11		T11	9		T49	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T64	1		T187	17		T244	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T187	6		T152	10		T190	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T46	14		T39	1		T165	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T151	11		T165	10		T243	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T6	5		T51	12		T150	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T65	9		T151	8		T40	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T10	1		T51	4		T64	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T149	1		T154	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T8	3		T13	3		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T5	1		T53	9		T173	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T151	11		T167	1		T217	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T167	1		T342	1		T324	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T245	1		T251	1		T309	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T149	1		T169	2		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T164	1		T242	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	10		T153	1		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T7	14		T10	1		T11	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	12		T187	1		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T64	2		T161	2		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T12	1		T151	12		T187	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T46	15		T165	5		T41	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T65	10		T165	11		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T6	6		T45	1		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T51	10		T149	1		T169	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T39	4		T170	14		T176	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T209	11		T330	2		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18941	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T152	10		T259	1		T174	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T51	2		T64	12		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T149	13		T263	4		T262	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T8	35		T13	36		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T173	14		T157	9		T168	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T167	7		T217	11		T247	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T167	6		T178	8		T192	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T309	6		T198	18		T343	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	14		T169	28		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T242	8		T155	11		T170	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T224	8		T287	14		T310	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	17		T150	3		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	12		T187	2		T166	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T161	13		T244	13		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T187	7		T152	9		T166	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T165	11		T41	5		T173	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T65	12		T165	11		T166	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	6		T45	12		T51	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	12		T149	4		T169	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T170	4		T176	1		T346	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T294	11		T256	3		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T15	1		T21	2		T118	23
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T152	9		T349	12		T314	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T39	4		T48	5		T253	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T51	10		T209	11		T332	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T340	11		T118	12		T290	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T152	10		T341	5		T366	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T12	1		T15	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T154	1		T259	1		T263	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T8	3		T13	3		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T149	1		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T151	11		T152	12		T173	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T53	9		T173	6		T167	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T217	12		T31	1		T251	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T149	1		T169	2		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T12	1		T164	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T163	1		T153	1		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	14		T10	1		T11	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	12		T11	10		T166	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T64	2		T161	2		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T12	1		T187	8		T152	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T46	15		T39	2		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T151	12		T165	11		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T6	6		T45	1		T51	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T149	1		T65	10		T169	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T48	1		T253	10		T176	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T51	12		T332	16		T303	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T340	6		T118	11		T290	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T152	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T15	1		T51	2		T64	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T263	4		T262	12		T265	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T8	35		T13	36		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T149	13		T157	9		T168	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	11		T167	7		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T173	14		T167	6		T192	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T217	11		T309	6		T274	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	14		T169	28		T165	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T242	8		T155	11		T367	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T224	8		T244	8		T310	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	17		T150	3		T184	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	12		T166	2		T287	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T161	13		T39	1		T187	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T187	9		T152	9		T166	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T165	11		T242	10		T185	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T165	11		T166	9		T263	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	6		T45	12		T51	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T149	4		T65	12		T169	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17