Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T64	2		T165	11		T243	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T51	4		T64	11		T185	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T154	1		T245	2		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	1		T152	12		T244	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T15	12		T187	7		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	14		T10	1		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1333	1			T8	3		T11	13		T13	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T45	1		T149	1		T161	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T149	1		T166	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T12	2		T151	11		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T6	12		T11	10		T152	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T46	15		T39	4		T187	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	1		T65	10		T164	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	6		T51	13		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T169	1		T153	1		T271	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T51	10		T150	1		T166	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T53	9		T224	1		T259	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T164	1		T169	1		T151	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T161	1		T187	18		T192	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T169	1		T40	16		T18	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18865	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T165	11		T170	6		T167	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T51	2		T64	12		T185	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T287	14		T265	6		T270	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T152	11		T244	13		T184	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T15	1		T187	7		T166	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T150	10		T224	15		T156	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T8	35		T11	17		T13	36
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T45	12		T149	13		T161	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T149	4		T166	9		T263	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T165	10		T242	23		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T6	12		T152	9		T155	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T187	2		T173	14		T170	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T65	12		T156	13		T91	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T6	6		T51	8		T149	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T169	12		T271	17		T276	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T51	12		T150	3		T166	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T224	8		T287	14		T288	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T169	10		T155	2		T56	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T161	2		T187	13		T192	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T169	16		T40	13		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T289	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T269	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T167	1		T36	6		T270	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T278	1		T279	4		T280	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T243	10		T170	3		T196	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T51	4		T64	11		T152	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T64	2		T165	11		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T244	5		T184	12		T247	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T187	7		T153	1		T166	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T7	14		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	13		T15	12		T39	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T45	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T8	3		T13	3		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T161	1		T151	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	12		T152	10		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	6		T12	1		T65	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T10	1		T11	10		T164	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T46	15		T149	1		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T65	10		T169	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T51	23		T151	12		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T53	9		T161	1		T187	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T150	1		T164	1		T169	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T167	9		T281	2		T290	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T279	4		T280	10		T282	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T170	6		T267	7		T253	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T51	2		T64	12		T152	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T165	11		T263	18		T185	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T244	13		T184	7		T247	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T187	7		T166	2		T242	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T150	10		T224	15		T156	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	17		T15	1		T265	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T45	12		T149	13		T161	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T8	35		T13	36		T14	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T161	11		T165	10		T242	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	12		T152	9		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T6	6		T187	2		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T156	13		T91	1		T268	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	14		T173	14		T263	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T65	12		T169	12		T271	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T51	20		T166	12		T41	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T161	2		T187	13		T224	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T150	3		T169	26		T40	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17