Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24813

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3212

1

T5

1

T6

12

T7

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21837

1

T1

13

T2

146

T3

20

auto[1]

6188

1

T6

24

T8

38

T11

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T242	9		T276	12		T291	13
values[0]	102	1			T167	10		T270	23		T292	15
values[1]	850	1			T11	10		T39	6		T151	12
values[2]	557	1			T6	24		T10	1		T46	15
values[3]	509	1			T7	14		T11	30		T65	22
values[4]	745	1			T10	1		T51	6		T149	15
values[5]	551	1			T6	12		T12	1		T161	3
values[6]	784	1			T12	1		T15	13		T45	13
values[7]	782	1			T53	9		T169	11		T165	16
values[8]	2923	1			T5	1		T8	38		T13	39
values[9]	1317	1			T12	1		T51	21		T149	14
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1168	1			T10	1		T11	10		T39	6
values[1]	447	1			T6	24		T149	5		T65	2
values[2]	596	1			T11	30		T46	15		T65	22
values[3]	733	1			T7	14		T10	1		T12	1
values[4]	552	1			T6	12		T161	3		T39	3
values[5]	827	1			T12	1		T15	13		T45	13
values[6]	2842	1			T8	38		T13	39		T14	10
values[7]	827	1			T5	1		T51	21		T150	23
values[8]	945	1			T12	1		T150	4		T64	23
values[9]	224	1			T149	14		T64	2		T167	7
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T39	1		T169	17		T152	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T10	1		T11	1		T39	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T6	13		T65	1		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T149	5		T187	8		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	18		T166	10		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T46	1		T65	13		T224	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	1		T51	3		T152	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	1		T12	1		T149	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T245	1		T185	15		T156	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T6	7		T161	3		T39	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T45	13		T153	1		T242	24
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	1		T15	6		T51	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1572	1			T8	38		T13	39		T14	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T53	1		T161	12		T169	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T150	11		T165	12		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T5	1		T51	9		T161	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T12	1		T150	4		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T64	13		T164	1		T242	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T149	14		T64	1		T167	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T179	1		T293	1		T294	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T39	1		T152	9		T41	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T11	9		T39	2		T151	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	11		T65	1		T295	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T187	6		T243	2		T201	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	12		T260	17		T261	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T46	14		T65	9		T173	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T51	3		T152	21		T209	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	13		T151	10		T165	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T185	14		T93	13		T176	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	5		T217	10		T262	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T59	11		T191	4		T261	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T15	7		T51	9		T243	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T52	16		T158	8		T285	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T53	8		T165	4		T296	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T150	12		T165	10		T217	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T51	12		T37	7		T273	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T151	8		T40	14		T173	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T64	10		T247	8		T253	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T64	1		T89	14		T276	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T297	1		T255	5		T210	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T242	9		T276	9		T291	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	1		T226	10		T299	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T167	10		T270	13		T292	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T39	1		T152	10		T41	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T39	2		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	13		T65	1		T169	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	1		T46	1		T149	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	18		T166	10		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T7	1		T65	13		T187	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	1		T51	3		T152	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T149	15		T224	16		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T153	1		T166	3		T155	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T6	7		T12	1		T161	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T45	13		T245	1		T242	24
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T12	1		T15	6		T51	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T263	5		T155	12		T284	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T53	1		T169	11		T165	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1648	1			T8	38		T13	39		T14	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T161	24		T37	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	449	1			T12	1		T149	14		T150	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T51	9		T64	13		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T276	3		T291	12		T300	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T226	10		T299	3		T301	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T270	10		T302	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T39	1		T152	9		T41	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	9		T39	2		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	11		T65	1		T170	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T46	14		T243	2		T209	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T11	12		T260	17		T276	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	13		T65	9		T187	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	3		T152	21		T209	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T173	1		T243	9		T184	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T49	4		T93	13		T176	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	5		T151	10		T165	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T185	14		T59	11		T191	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T15	7		T51	9		T243	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T284	5		T177	9		T273	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	8		T165	4		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1006	1			T52	16		T158	8		T150	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T37	7		T273	14		T303	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T64	1		T151	8		T40	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T51	12		T64	10		T247	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T39	2		T169	1		T152	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T10	1		T11	10		T39	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T6	12		T65	2		T163	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T149	1		T187	7		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	13		T166	1		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T46	15		T65	10		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T10	1		T51	4		T152	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	14		T12	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T245	1		T185	15		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T6	6		T161	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T45	1		T153	1		T242	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T12	1		T15	12		T51	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1241	1			T8	3		T13	3		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T53	9		T161	1		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T150	13		T165	11		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T51	13		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T12	1		T150	1		T164	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T64	11		T164	1		T242	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T149	1		T64	2		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T179	1		T293	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T169	16		T152	9		T41	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T187	15		T224	8		T263	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T6	12		T295	6		T225	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T149	4		T187	7		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	17		T166	9		T260	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T65	12		T224	15		T173	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T51	2		T152	20		T166	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T149	14		T165	10		T244	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T185	14		T156	20		T287	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T6	6		T161	2		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	12		T242	23		T263	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T15	1		T51	12		T244	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T8	35		T13	36		T14	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T161	11		T169	10		T165	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T150	10		T165	11		T217	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T51	8		T161	11		T37	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T150	3		T169	12		T40	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T64	12		T242	10		T157	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T149	13		T167	6		T276	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T294	12		T297	4		T255	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T242	1		T276	4		T291	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T298	1		T226	11		T299	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T167	1		T270	11		T292	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T39	2		T152	10		T41	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	10		T39	4		T151	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	12		T65	2		T169	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	1		T46	15		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	13		T166	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	14		T65	10		T187	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	1		T51	4		T152	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T149	1		T224	1		T154	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	1		T166	1		T155	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T6	6		T12	1		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T45	1		T245	1		T242	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	1		T15	12		T51	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T263	1		T155	1		T284	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T53	9		T169	1		T165	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T8	3		T13	3		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	1		T161	2		T37	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T12	1		T149	1		T150	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T51	13		T64	11		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T242	8		T276	8		T300	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T226	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T167	9		T270	12		T292	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T152	9		T41	5		T170	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T187	15		T260	9		T262	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T6	12		T169	16		T170	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T149	4		T166	12		T224	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	17		T166	9		T260	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T65	12		T187	7		T173	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T51	2		T152	20		T286	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T149	14		T224	15		T168	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T166	2		T155	2		T156	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T6	6		T161	2		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T45	12		T242	23		T185	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T15	1		T51	12		T244	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T263	4		T155	11		T177	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T169	10		T165	11		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T8	35		T13	36		T14	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T161	22		T37	7		T273	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	368	1			T149	13		T150	3		T169	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T51	8		T64	12		T242	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17