Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22283

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

5742

1

T5

1

T6

36

T7

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22087

1

T1

13

T2

146

T3

20

auto[1]

5938

1

T5

1

T7

14

T8

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	46	1			T167	7		T304	6		T305	14
values[0]	2	1			T306	1		T108	1		-	-
values[1]	631	1			T5	1		T11	30		T187	14
values[2]	804	1			T51	22		T164	1		T243	13
values[3]	699	1			T11	10		T164	1		T151	11
values[4]	721	1			T10	1		T51	21		T149	5
values[5]	744	1			T45	13		T149	14		T64	2
values[6]	835	1			T6	24		T12	1		T51	6
values[7]	729	1			T7	14		T12	1		T150	23
values[8]	641	1			T6	12		T15	13		T161	12
values[9]	3309	1			T8	38		T10	1		T12	1
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	829	1			T5	1		T11	30		T51	22
values[1]	2965	1			T8	38		T11	10		T13	39
values[2]	759	1			T51	21		T64	23		T164	1
values[3]	667	1			T10	1		T149	5		T64	2
values[4]	727	1			T6	24		T45	13		T149	14
values[5]	902	1			T7	14		T12	1		T51	6
values[6]	653	1			T6	12		T150	23		T39	3
values[7]	676	1			T12	1		T15	13		T149	15
values[8]	840	1			T10	1		T12	1		T46	15
values[9]	137	1			T161	3		T170	18		T167	7
minimum	18870	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T51	13		T152	10		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T5	1		T11	18		T187	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T164	1		T166	3		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1616	1			T8	38		T11	1		T13	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T64	13		T151	1		T173	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T51	9		T164	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T149	5		T64	1		T169	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	1		T65	1		T169	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T149	14		T150	4		T165	23
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T6	13		T45	13		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T65	13		T224	9		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T7	1		T12	1		T51	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T151	1		T295	7		T89	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	7		T150	11		T39	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T149	15		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T15	6		T161	12		T267	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T53	1		T39	2		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	1		T12	1		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T167	7		T174	1		T193	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T161	3		T170	5		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18734	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T91	2		T25	1		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T51	9		T152	9		T243	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T11	12		T187	6		T165	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T243	2		T244	4		T170	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	951	1			T11	9		T52	16		T158	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T64	10		T151	10		T173	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T51	12		T243	9		T217	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T64	1		T173	5		T185	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T65	1		T247	8		T262	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T165	19		T209	11		T262	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T6	11		T39	1		T190	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T65	9		T246	9		T17	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T7	13		T51	3		T187	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T151	11		T295	9		T89	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	5		T150	12		T40	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T152	11		T190	9		T260	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T15	7		T260	17		T268	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T53	8		T39	2		T184	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T46	14		T151	8		T270	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T193	10		T256	4		T118	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T170	13		T307	2		T308	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T25	1		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T167	7		T305	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T304	1		T308	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T306	1		T108	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T152	10		T166	3		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	1		T11	18		T187	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T51	13		T164	1		T243	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T243	1		T244	9		T263	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T151	1		T173	1		T157	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	1		T164	1		T152	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T149	5		T64	13		T169	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T10	1		T51	9		T65	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T149	14		T64	1		T173	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T45	13		T39	1		T169	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T150	4		T65	13		T165	23
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	13		T12	1		T51	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	1		T151	1		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T7	1		T150	11		T187	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T259	1		T157	5		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	7		T15	6		T161	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	362	1			T53	1		T149	15		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1687	1			T8	38		T10	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T305	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T304	5		T308	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T152	9		T243	15		T244	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	12		T187	6		T165	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T51	9		T243	2		T184	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T243	9		T244	12		T217	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T151	10		T173	1		T284	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T11	9		T152	10		T41	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T64	10		T185	14		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T51	12		T65	1		T247	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T64	1		T173	5		T265	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T39	1		T190	2		T50	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T65	9		T165	19		T246	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T6	11		T51	3		T217	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T151	11		T89	14		T93	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	13		T150	12		T187	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T260	9		T295	9		T176	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	5		T15	7		T173	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T53	8		T39	2		T152	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	984	1			T46	14		T52	16		T158	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T51	10		T152	10		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T11	13		T187	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T164	1		T166	1		T243	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1294	1			T8	3		T11	10		T13	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T64	11		T151	11		T173	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T51	13		T164	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T149	1		T64	2		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	1		T65	2		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T149	1		T150	1		T165	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T6	12		T45	1		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T65	10		T224	1		T245	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	14		T12	1		T51	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T151	12		T295	10		T89	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T6	6		T150	13		T39	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T149	1		T152	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T15	12		T161	1		T267	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T53	9		T39	4		T163	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	1		T12	1		T46	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T167	1		T174	1		T193	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T161	1		T170	14		T29	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18865	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T91	2		T25	2		T306	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T51	12		T152	9		T263	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	17		T187	7		T165	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T166	2		T244	13		T170	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1273	1			T8	35		T13	36		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T64	12		T157	9		T265	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T51	8		T242	8		T155	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T149	4		T169	12		T173	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T169	16		T242	10		T247	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T149	13		T150	3		T165	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T6	12		T45	12		T155	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T65	12		T224	8		T263	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T51	2		T169	10		T187	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T295	6		T192	1		T309	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T6	6		T150	10		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T149	14		T152	11		T157	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	1		T161	11		T267	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T184	7		T56	8		T168	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T161	11		T187	2		T224	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T167	6		T193	5		T256	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T161	2		T170	4		T271	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T167	1		T305	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T304	6		T308	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T306	1		T108	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T152	10		T166	1		T154	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	1		T11	13		T187	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T51	10		T164	1		T243	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T243	10		T244	13		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T151	11		T173	2		T157	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	10		T164	1		T152	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T149	1		T64	11		T169	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	1		T51	13		T65	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T149	1		T64	2		T173	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T45	1		T39	2		T169	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T150	1		T65	10		T165	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	12		T12	1		T51	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T151	12		T245	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	14		T150	13		T187	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T259	1		T157	1		T175	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T6	6		T15	12		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T53	9		T149	1		T39	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1360	1			T8	3		T10	1		T12	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T167	6		T305	6		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T308	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T152	9		T166	2		T244	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	17		T187	7		T165	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	12		T263	4		T170	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T244	8		T263	12		T156	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T157	9		T176	1		T265	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T152	9		T166	9		T41	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T149	4		T64	12		T169	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T51	8		T242	8		T247	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T149	13		T173	14		T265	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T45	12		T169	16		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T150	3		T65	12		T165	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T6	12		T51	2		T169	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T263	18		T310	12		T192	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T150	10		T187	13		T40	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T157	4		T260	9		T295	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	6		T15	1		T161	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T149	14		T152	11		T184	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1311	1			T8	35		T13	36		T14	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17