Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24749

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3276

1

T6

12

T7

14

T10

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21702

1

T1

13

T2

144

T3

20

auto[1]

6323

1

T2

2

T6

24

T7

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	433	1			T2	2		T43	1		T55	1
values[0]	64	1			T154	1		T245	1		T288	21
values[1]	795	1			T11	10		T45	13		T39	6
values[2]	2818	1			T8	38		T12	1		T13	39
values[3]	526	1			T5	1		T6	12		T51	28
values[4]	626	1			T10	1		T15	13		T161	12
values[5]	571	1			T6	24		T7	14		T12	2
values[6]	845	1			T161	3		T163	1		T242	24
values[7]	770	1			T64	2		T164	1		T165	36
values[8]	797	1			T11	30		T53	9		T64	23
values[9]	1321	1			T10	1		T51	21		T149	14
minimum	18459	1			T1	13		T2	144		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	908	1			T11	10		T45	13		T46	15
values[1]	2876	1			T8	38		T12	1		T13	39
values[2]	559	1			T5	1		T6	12		T51	28
values[3]	557	1			T10	1		T12	1		T15	13
values[4]	711	1			T6	24		T12	1		T161	3
values[5]	795	1			T7	14		T164	1		T163	1
values[6]	823	1			T64	23		T161	12		T165	16
values[7]	730	1			T11	30		T53	9		T64	2
values[8]	1003	1			T10	1		T149	14		T164	1
values[9]	184	1			T51	21		T151	11		T175	1
minimum	18879	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T151	1		T165	12		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	1		T45	13		T46	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1669	1			T8	38		T13	39		T14	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T150	4		T224	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T51	16		T150	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T6	7		T163	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T15	6		T161	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T12	1		T190	1		T168	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T6	13		T12	1		T263	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T161	3		T152	12		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T164	1		T163	1		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	1		T152	10		T185	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T161	12		T165	12		T166	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T64	13		T154	1		T217	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	18		T64	1		T169	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T53	1		T187	14		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T149	14		T153	1		T173	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T10	1		T164	1		T244	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T151	1		T296	1		T203	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T51	9		T175	1		T19	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18747	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T151	11		T165	10		T184	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	9		T46	14		T39	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T52	16		T158	8		T65	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T184	13		T56	7		T311	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T51	12		T150	12		T151	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	5		T18	1		T59	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T15	7		T41	6		T243	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T190	2		T177	24		T312	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	11		T191	4		T276	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T152	11		T36	5		T176	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T165	9		T246	9		T260	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T152	9		T185	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T165	4		T40	14		T262	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T64	10		T217	11		T93	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	12		T64	1		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T53	8		T187	17		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T173	1		T170	2		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T244	12		T185	14		T190	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T151	10		T296	4		T203	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T51	12		T313	11		T314	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	417	1			T2	2		T43	1		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T154	1		T245	1		T272	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T288	11		T315	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T39	2		T151	1		T165	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T45	13		T39	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T8	38		T13	39		T14	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T46	1		T149	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T51	16		T150	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T6	7		T163	1		T18	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	1		T15	6		T161	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T190	1		T168	15		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	13		T12	1		T243	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	1		T12	1		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T163	1		T242	24		T263	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T161	3		T185	6		T17	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T64	1		T164	1		T165	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T152	10		T154	1		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T11	18		T161	12		T169	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T53	1		T64	13		T187	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T149	14		T151	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	366	1			T10	1		T51	9		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18328	1			T1	13		T2	144		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T316	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T272	3		T317	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T288	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T39	2		T151	11		T165	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T11	9		T39	1		T244	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T52	16		T158	8		T65	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	14		T184	13		T56	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T51	12		T150	12		T217	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T6	5		T18	1		T59	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T15	7		T151	8		T41	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T190	2		T176	1		T177	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T6	11		T243	9		T191	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	13		T152	11		T36	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T246	9		T260	9		T93	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T185	6		T17	4		T276	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T64	1		T165	13		T40	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T152	9		T217	11		T49	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	12		T50	1		T262	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T53	8		T64	10		T187	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T151	10		T173	1		T170	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	411	1			T51	12		T243	2		T244	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T151	12		T165	11		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	10		T45	1		T46	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T8	3		T13	3		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T12	1		T150	1		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	1		T51	14		T150	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T6	6		T163	1		T174	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	1		T15	12		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	1		T190	3		T168	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	12		T12	1		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T161	1		T152	12		T31	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T164	1		T163	1		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	14		T152	10		T185	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T161	1		T165	5		T166	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T64	11		T154	1		T217	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	13		T64	2		T169	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T53	9		T187	18		T152	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T149	1		T153	1		T173	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T10	1		T164	1		T244	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T151	11		T296	5		T203	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T51	13		T175	1		T19	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18866	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T306	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T165	11		T263	4		T184	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T45	12		T149	14		T169	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T8	35		T13	36		T14	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T150	3		T224	15		T56	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T51	14		T150	10		T187	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T6	6		T287	14		T176	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T15	1		T161	11		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T168	14		T177	31		T318	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	12		T263	12		T167	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T161	2		T152	11		T261	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T165	10		T242	23		T155	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T152	9		T185	5		T167	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T161	11		T165	11		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T64	12		T217	11		T287	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	17		T169	16		T262	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T187	13		T152	9		T224	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T149	13		T170	6		T268	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T244	8		T185	14		T157	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T203	11		T307	1		T319	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T51	8		T320	3		T321	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T289	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	422	1			T2	2		T43	1		T55	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T154	1		T245	1		T272	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T288	11		T315	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T39	4		T151	12		T165	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	10		T45	1		T39	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T8	3		T13	3		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	1		T46	15		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T51	14		T150	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T6	6		T163	1		T18	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	1		T15	12		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T190	3		T168	1		T174	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	12		T12	1		T243	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	14		T12	1		T152	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T163	1		T242	1		T263	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T161	1		T185	7		T17	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T64	2		T164	1		T165	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T152	10		T154	1		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	13		T161	1		T169	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T53	9		T64	11		T187	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T149	1		T151	11		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	493	1			T10	1		T51	13		T164	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18459	1			T1	13		T2	144		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T316	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T272	5		T317	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T288	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T165	11		T263	4		T184	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T45	12		T169	10		T244	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T8	35		T13	36		T14	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T149	14		T150	3		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T51	14		T150	10		T166	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T6	6		T287	14		T294	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T15	1		T161	11		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T168	14		T176	1		T177	31
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	12		T167	9		T276	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T152	11		T167	7		T322	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T242	23		T263	12		T260	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T161	2		T185	5		T17	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T165	21		T166	9		T40	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T152	9		T217	11		T287	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	17		T161	11		T169	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T64	12		T187	13		T152	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T149	13		T170	6		T268	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T51	8		T224	8		T244	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17