Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28025

1

T1

13

T2

146

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

24085

1

T1

13

T2

146

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3940

1

T5

1

T6

12

T7

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21723

1

T1

13

T2

146

T3

20

auto[1]

6302

1

T8

38

T11

30

T12

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23948

1

T1

13

T2

146

T3

20

auto[1]

4077

1

T6

16

T7

13

T11

21

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T217	23		-	-		-	-
values[0]	110	1			T64	23		T187	31		T323	5
values[1]	737	1			T10	1		T149	29		T164	1
values[2]	750	1			T6	24		T51	21		T161	12
values[3]	728	1			T7	14		T51	22		T161	12
values[4]	2937	1			T8	38		T13	39		T14	10
values[5]	458	1			T5	1		T11	30		T161	3
values[6]	713	1			T6	12		T15	13		T46	15
values[7]	835	1			T12	1		T53	9		T64	2
values[8]	575	1			T11	10		T12	1		T45	13
values[9]	1295	1			T10	1		T12	1		T150	4
minimum	18864	1			T1	13		T2	146		T3	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1097	1			T6	24		T10	1		T149	29
values[1]	721	1			T7	14		T51	43		T161	12
values[2]	664	1			T163	1		T184	19		T185	29
values[3]	2745	1			T8	38		T13	39		T14	10
values[4]	712	1			T5	1		T11	30		T15	13
values[5]	741	1			T6	12		T46	15		T51	6
values[6]	705	1			T12	2		T64	2		T187	3
values[7]	616	1			T11	10		T45	13		T150	4
values[8]	943	1			T10	1		T12	1		T39	7
values[9]	194	1			T56	16		T260	19		T176	3
minimum	18887	1			T1	13		T2	146		T3	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

4156

1

T6

18

T8

35

T11

17

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T6	13		T149	29		T65	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T10	1		T161	12		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T51	13		T156	14		T217	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	1		T51	9		T161	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T247	12		T284	1		T273	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T163	1		T184	8		T185	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T8	38		T13	39		T14	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T149	5		T161	3		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	18		T65	1		T165	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T5	1		T15	6		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T46	1		T51	3		T39	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	7		T53	1		T150	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T12	1		T59	1		T262	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T12	1		T64	1		T187	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	1		T150	4		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T45	13		T166	3		T41	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T39	2		T151	1		T170	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T10	1		T12	1		T39	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T260	10		T265	12		T264	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T56	9		T176	2		T264	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T64	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T6	11		T65	9		T187	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T217	12		T246	9		T209	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T51	9		T217	10		T253	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T7	13		T51	12		T173	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T247	8		T284	5		T273	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T184	11		T185	14		T18	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T52	16		T158	8		T285	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T151	8		T165	9		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	12		T65	1		T165	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T15	7		T243	2		T247	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T46	14		T51	3		T39	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	5		T53	8		T150	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T59	11		T262	13		T254	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T64	1		T165	10		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T11	9		T152	9		T324	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T41	6		T173	1		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T39	2		T151	10		T170	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T151	11		T187	6		T170	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T260	9		T265	13		T264	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T56	7		T176	1		T264	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T64	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T217	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T187	14		T323	1		T325	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T64	13		T305	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T149	29		T155	12		T217	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	1		T164	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T6	13		T65	13		T242	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T51	9		T161	12		T169	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T51	13		T253	2		T273	31
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	1		T161	12		T173	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1547	1			T8	38		T13	39		T14	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T149	5		T151	1		T165	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	18		T65	1		T166	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T161	3		T173	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T46	1		T51	3		T39	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	7		T15	6		T150	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T40	15		T59	1		T262	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T12	1		T53	1		T64	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T12	1		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T45	13		T173	1		T167	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T150	4		T39	2		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T10	1		T12	1		T39	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18733	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T217	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T187	17		T323	4		T325	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T64	10		T305	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T217	10		T253	7		T36	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T217	12		T246	9		T209	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	11		T65	9		T253	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T51	12		T244	4		T184	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T51	9		T253	10		T273	30
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	13		T173	5		T184	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T52	16		T158	8		T285	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T151	8		T165	9		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T11	12		T65	1		T261	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T173	7		T243	2		T326	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T46	14		T51	3		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T6	5		T15	7		T150	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T40	14		T59	11		T262	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T53	8		T64	1		T165	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	9		T152	9		T254	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T173	1		T260	17		T262	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T39	2		T151	10		T170	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T151	11		T187	6		T41	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T15	1		T39	5		T41	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T6	12		T149	2		T65	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T10	1		T161	1		T164	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T51	10		T156	1		T217	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	14		T51	13		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T247	9		T284	6		T273	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T163	1		T184	12		T185	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T8	3		T13	3		T14	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T149	1		T161	1		T151	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	13		T65	2		T165	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T5	1		T15	12		T164	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T46	15		T51	4		T39	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	6		T53	9		T150	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	1		T59	12		T262	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T12	1		T64	2		T187	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T11	10		T150	1		T152	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	1		T166	1		T41	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T39	4		T151	11		T170	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T10	1		T12	1		T39	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T260	10		T265	14		T264	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T56	8		T176	2		T264	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T64	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	12		T149	27		T65	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T161	11		T167	7		T217	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T51	12		T156	13		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	8		T161	11		T169	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T247	11		T273	16		T318	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T184	7		T185	14		T156	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T8	35		T13	36		T14	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T149	4		T161	2		T165	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	17		T165	11		T242	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	1		T224	15		T263	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T51	2		T40	13		T185	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T6	6		T150	10		T168	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T262	12		T271	17		T254	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T187	2		T165	11		T152	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T150	3		T152	9		T263	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T45	12		T166	2		T41	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T170	4		T157	4		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T39	1		T169	26		T187	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T260	9		T265	11		T264	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T56	8		T176	1		T264	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T64	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T217	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T187	18		T323	5		T325	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T64	11		T305	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T149	2		T155	1		T217	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	1		T164	1		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T6	12		T65	10		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T51	13		T161	1		T169	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T51	10		T253	11		T273	32
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T7	14		T161	1		T173	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T8	3		T13	3		T14	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T149	1		T151	9		T165	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	13		T65	2		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T5	1		T161	1		T173	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T46	15		T51	4		T39	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T6	6		T15	12		T150	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T40	16		T59	12		T262	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T12	1		T53	9		T64	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	10		T12	1		T152	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T45	1		T173	2		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T150	1		T39	4		T151	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T10	1		T12	1		T39	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18864	1			T1	13		T2	146		T3	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T217	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T187	13		T325	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T64	12		T305	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T149	27		T155	11		T217	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T167	7		T217	11		T267	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	12		T65	12		T242	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T51	8		T161	11		T169	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T51	12		T253	1		T273	29
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T161	11		T173	14		T184	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T8	35		T13	36		T14	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T149	4		T165	10		T152	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	17		T166	9		T287	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T161	2		T173	7		T263	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T51	2		T165	11		T242	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T6	6		T15	1		T150	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T40	13		T262	12		T271	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T187	2		T165	11		T152	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T152	9		T263	12		T254	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	12		T167	6		T260	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T150	3		T170	4		T167	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T39	1		T169	26		T187	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

23869

1

T1

13

T2

146

T3

20

auto[1]

auto[0]

4156

1

T6

18

T8

35

T11

17